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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / include / vpci_errs.h
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vpci_errs.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _ONTARIO_VPCI_ERRS_H
50#define _ONTARIO_VPCI_ERRS_H
51
52#pragma ident "@(#)vpci_errs.h 1.34 07/07/30 SMI"
53
54#ifdef __cplusplus
55extern "C" {
56#endif
57
58
59#define PCIE_ERR_INO 62
60#define JBC_ERR_INO 63
61
62/*
63 * Macro to generate unique error handle
64 * and load some of the diag ereport and sun4v erpt
65 * entries that are common to mondo 0x62 and 0x63.
66 * %g1 - fire cookie
67 * %g2 - r_fire_e_rpt
68 * %g3 - IGN
69 * %g4 - INO
70 * %g5 - scratch
71 * %g6 - scratch
72 * %g7 - data0
73 */
74
75/* BEGIN CSTYLED */
76#define GEN_ERR_HNDL_SETUP_ERPTS(FIRE_COOKIE, FIRE_rpt, IGN, INO, scr1, \
77 scr2, DATA0) \
78 .pushlocals ;\
79 set FIRE_COOKIE_JBC_ERPT, scr1 ;\
80 set PCIE_ERR_INO, scr2 ;\
81 cmp scr2, INO ;\
82 beq,a,pt %xcc, 1f ;\
83 set FIRE_COOKIE_PCIE_ERPT, scr1 ;\
841: ;\
85 add FIRE_COOKIE, scr1, FIRE_rpt ;\
86 GEN_SEQ_NUMBER(scr1, scr2); ;\
87 /* store the error handle in the error report */ ;\
88 stx scr1, [FIRE_rpt + PCIERPT_EHDL] /* store ehdlin erpt */ ;\
89 stx scr1, [FIRE_rpt + PCIERPT_SUN4V_EHDL] ;\
90 stx DATA0, [FIRE_rpt + PCIERPT_SYSINO] ;\
91 st INO, [FIRE_rpt + PCIERPT_MONDO_NUM] ;\
92 st IGN, [FIRE_rpt + PCIERPT_AGENTID] ;\
93 /* save the TOD/STICK count */ ;\
94 ROOT_STRUCT(scr1) ;\
95 ldx [scr1 + CONFIG_TOD], scr1 ;\
96 brnz,a,pn scr1, 1f ;\
97 ldx [scr1], scr1 /* aborted if no TOD */ ;\
981: rd STICK, scr2 /* stick */ ;\
99 stx scr1, [FIRE_rpt + PCIERPT_FPGA_TOD] ;\
100 stx scr2, [FIRE_rpt + PCIERPT_STICK] ;\
101 stx scr2, [FIRE_rpt + PCIERPT_SUN4V_STICK] ;\
102 rdhpr %hver, scr1 /* read cpu version */ ;\
103 stx scr1, [FIRE_rpt + PCIERPT_CPUVER] ;\
104 set ERPT_TYPE_VPCI, scr2 ;\
105 stx scr2, [FIRE_rpt + PCIERPT_REPORT_TYPE_62] ;\
106 .poplocals ;\
107
108#define CLEAR_FIRE_INTERRUPT(FIRE_COOKIE, MONDO, reg1) \
109 ldx [FIRE_COOKIE + FIRE_COOKIE_INTCLR], reg1 ;\
110 stx %g0, [reg1 + (MONDO<<3)]
111
112#define GENERATE_FMA_REPORT \
113 mov r_fire_e_rpt, %g1 ;\
114 ba,a generate_fma_report ;\
115 .empty
116
117#define PCIE_ERR_MONDO_OFFSET 8
118#define JBC_ERR_MONDO_OFFSET 0
119#define FIRE_LEAF_DEVID_MASK 1
120
121#define PCIE_ERR_MONDO_EREPORT(FIRE_COOKIE, FIRE_rpt, reg1, reg2) \
122 ldx [FIRE_rpt + PCIERPT_SYSINO], reg1 ;\
123 srlx reg1, FIRE_DEVINO_SHIFT, reg1 ;\
124 and reg1, FIRE_LEAF_DEVID_MASK, reg1 /* devid 0 or 1 */ ;\
125 ldx [FIRE_COOKIE + FIRE_COOKIE_VIRTUAL_INTMAP], reg2 ;\
126 add reg2, PCIE_ERR_MONDO_OFFSET, reg2 ;\
127 ldub [reg2 + reg1], reg1 ;\
128 brnz reg1, generate_guest_report /* yes, send a ereport*/;\
129 nop
130
131#define JBC_ERR_MONDO_EREPORT(FIRE_COOKIE, FIRE_rpt, reg1, reg2) \
132 ldx [FIRE_COOKIE + FIRE_COOKIE_VIRTUAL_INTMAP], reg2 ;\
133 lduh [reg2 + JBC_ERR_MONDO_OFFSET], reg2 ;\
134 brnz reg2, generate_guest_report_special ;\
135 nop
136
137#define FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_NBITS (42)
138
139#define FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_BITS(addr) \
140 sllx addr, (63 - FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_NBITS), addr ;\
141 srlx addr, (63 - FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_NBITS), addr
142
143#define FIRE_JBCINT_OUT_TRAN_ERROR_LOG_ADDR_BITS \
144 FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_BITS
145
146/* DESC.BLOCK bits 31:28 */
147#define HOSTBUS (1LL << 28)
148#define MMU (2LL << 28)
149#define INTR (3LL << 28)
150#define PCI (4LL << 28)
151#define BLK_UNKOWN (0xeLL << 28)
152
153/* HOSTBUS.op */
154#define PIO (1LL << 24)
155#define DMA (2LL << 24)
156#define OP_UNKNOWN (0xeLL << 24)
157
158/* MMU.op */
159#define TRANSLATION (1LL << 24)
160#define BYPASS (2LL << 24)
161#define TABLEWALK (3LL << 24)
162
163/* INTR.op */
164#define MSI32 (1LL << 24)
165#define MSI64 (2LL << 24)
166#define MSIQ (3LL << 24)
167#define PCIEMSG (4LL << 24)
168#define INT_OP_UNKNOWN (0xeLL << 24)
169
170/* phase */
171#define ADDR (1LL << 20)
172#define PDATA (2LL << 20)
173#define PHASE_UNKNOWN (0xeLL << 20)
174#define PHASE_IRRELEVANT (0xfLL << 20)
175
176/* conditions */
177#define ILL (1LL << 16)
178#define UNMAP (2LL << 16)
179#define INT (3LL << 16)
180#define UE (4LL << 16)
181#define PROT (5LL << 16)
182#define INV (6LL << 16)
183#define OV (5LL << 16)
184#define TO (5LL << 16)
185#define COND_UNKNOWN (0xeLL << 16)
186#define COND_IRRELEVENT (0xfLL << 16)
187
188/* directions */
189#define READ (1LL << 12)
190#define WRITE (2LL << 12)
191#define RDRW (3LL << 12)
192#define INGRESS (4LL << 12)
193#define EGRESS (5LL << 12)
194#define LINK (6LL << 12)
195#define DIR_UNKNOWN (0xeLL << 12)
196#define DIR_IRRELEVANT (0xfLL << 12)
197
198/* flags */
199#define SIZE (1LL << 0) /* size of the memory region affected */
200#define P (1LL << 0) /* PCI Status Register */
201#define M (1LL << 1) /* address field contains memory addr (RA) */
202#define E (1LL << 1) /* PCIe Status Register */
203#define D (1LL << 2) /* address field is a DMA virtual address */
204#define U (1LL << 2) /* UE Status reg */
205#define RST (1LL << 3) /* restartable */
206#define C (1LL << 3) /* reserved(note: CE Status Register */
207#define H (1LL << 4) /* contain PCIE headers or HDR1 */
208#define I (1LL << 5) /* HDR2 */
209#define R (1LL << 6) /* Root error status reg */
210#define S (1LL << 7) /* error source reg */
211#define Z (1LL << 8) /* error requires clearing before re-arm */
212
213
214/* PCI Express epkt bits */
215/* UE bits */
216#define TRAINING_ERROR (1LL << 0)
217#define DATA_LINK_ERROR (1LL << 4)
218#define POISONED_TLP (1LL << 12)
219#define FLOW_CONTROL_ERROR (1LL << 13)
220#define COMPLETION_TIMEOUT (1LL << 14)
221#define COMPLETER_ABORT (1LL << 15)
222#define UNEXPECTED_COMPLETION (1LL << 16)
223#define RECEIVER_OVERFLOW (1LL << 17)
224#define MALFORMED_TLP (1LL << 18)
225#define ECRC_ERROR (1LL << 19)
226#define UNSUPPORTED_REQUEST (1LL << 20)
227
228/* CE bits */
229#define RECEIVER_ERROR (1LL << 0)
230#define BAD_TLP (1LL << 6)
231#define BAD_DLLP (1LL << 7)
232#define REPLAY_NUM_ROLLOVER (1LL << 8)
233#define REPLAY_TIMER_TIMEOUT (1LL << 12)
234
235/* UE/CE bits */
236#define IS (1LL << 3) /* Interrupt Status */
237#define MDP (1LL << 8) /* Master Data Parity Error */
238#define ST (1LL << 11) /* Signaled Target Abort */
239#define RT (1LL << 12) /* Received Target Abort */
240#define RM (1LL << 13) /* Received Master Abort */
241#define SS (1LL << 14) /* Signaled System Error */
242#define DP (1LL << 15) /* Detected Parity Error */
243
244/* JBC Error Status Clear Register bit defs */
245
246#define SPARE_BIT_2_S (1LL << 63)
247#define SPARE_BIT_0_S (1LL << 62)
248#define SPARE_BIT_1_S (1LL << 61)
249#define PIO_UNMAP_RD_S (1LL << 60)
250#define ILL_ACC_RD_S (1LL << 59)
251#define EBUS_TO_S (1LL << 58)
252#define MB_PEA_S (1LL << 57)
253#define MB_PER_S (1LL << 56)
254#define MB_PEW_S (1LL << 55)
255#define UE_ASYN_S (1LL << 54)
256#define CE_ASYN_S (1LL << 53)
257#define JTE_S (1LL << 52)
258#define JBE_S (1LL << 51)
259#define JUE_S (1LL << 50)
260#define IJP_S (1LL << 49)
261#define ICISE_S (1LL << 48)
262#define CPE_S (1LL << 47)
263#define APE_S (1LL << 46)
264#define WR_DPE_S (1LL << 45)
265#define RD_DPE_S (1LL << 44)
266#define ILL_BMW_S (1LL << 43)
267#define ILL_BMR_S (1LL << 42)
268#define BJC_S (1LL << 41)
269#define PIO_UNMAP_S (1LL << 40)
270#define PIO_DPE_S (1LL << 39)
271#define PIO_CPE_S (1LL << 38)
272#define ILL_ACC_S (1LL << 37)
273#define UNSOL_RD_S (1LL << 36)
274#define UNSOL_INTR_S (1LL << 35)
275#define JTCEEW_S (1LL << 34)
276#define JTCEEI_S (1LL << 33)
277#define JTCEER_S (1LL << 32)
278#define SPARE_BIT_2_P (1LL << 31)
279#define SPARE_BIT_0_P (1LL << 30)
280#define SPARE_BIT_1_P (1LL << 29)
281#define PIO_UNMAP_RD_P (1LL << 28)
282#define ILL_ACC_RD_P (1LL << 27)
283#define EBUS_TO_P (1LL << 26)
284#define MB_PEA_P (1LL << 25)
285#define MB_PER_P (1LL << 24)
286#define MB_PEW_P (1LL << 23)
287#define UE_ASYN_P (1LL << 22)
288#define CE_ASYN_P (1LL << 21)
289#define JTE_P (1LL << 20)
290#define JBE_P (1LL << 19)
291#define JUE_P (1LL << 18)
292#define IJP_P (1LL << 17)
293#define ICISE_P (1LL << 16)
294#define CPE_P (1LL << 15)
295#define APE_P (1LL << 14)
296#define WR_DPE_P (1LL << 13)
297#define RD_DPE_P (1LL << 12)
298#define ILL_BMW_P (1LL << 11)
299#define ILL_BMR_P (1LL << 10)
300#define BJC_P (1LL << 9)
301#define PIO_UNMAP_P (1LL << 8)
302#define PIO_DPE_P (1LL << 7)
303#define PIO_CPE_P (1LL << 6)
304#define ILL_ACC_P (1LL << 5)
305#define UNSOL_RD_P (1LL << 4)
306#define UNSOL_INTR_P (1LL << 3)
307#define JTCEEW_P (1LL << 2)
308#define JTCEEI_P (1LL << 1)
309#define JTCEER_P (1LL << 0)
310
311/* JBC Interrupt Enable Register bit defs */
312#define SPARE_S_INT_EN (1LL << 61)
313#define PIO_UNMAP_RD_S_INT_EN (1LL << 60)
314#define ILL_ACC_RD_S_INT_EN (1LL << 59)
315#define EBUS_TO_S_LOG_EN (1LL << 58)
316#define MB_PEA_S_INT_EN (1LL << 57)
317#define MB_PER_S_INT_EN (1LL << 56)
318#define MB_PEW_S_INT_EN (1LL << 55)
319#define UE_ASYN_S_INT_EN (1LL << 54)
320#define CE_ASYN_S_INT_EN (1LL << 53)
321#define JTE_S_INT_EN (1LL << 52)
322#define JBE_S_INT_EN (1LL << 51)
323#define JUE_S_INT_EN (1LL << 50)
324#define IJP_S_INT_EN (1LL << 49)
325#define ICISE_S_INT_EN (1LL << 48)
326#define CPE_S_INT_EN (1LL << 47)
327#define APE_S_INT_EN (1LL << 46)
328#define WR_DPE_S_INT_EN (1LL << 45)
329#define RD_DPE_S_INT_EN (1LL << 44)
330#define ILL_BMW_S_INT_EN (1LL << 43)
331#define ILL_BMR_S_INT_EN (1LL << 42)
332#define BJC_S_INT_EN (1LL << 41)
333#define PIO_UNMAP_S_INT_EN (1LL << 40)
334#define PIO_DPE_S_INT_EN (1LL << 39)
335#define PIO_CPE_S_INT_EN (1LL << 38)
336#define ILL_ACC_S_INT_EN (1LL << 37)
337#define UNSOL_RD_S_INT_EN (1LL << 36)
338#define UNSOL_INTR_S_INT_EN (1LL << 35)
339#define JTCEEW_S_INT_EN (1LL << 34)
340#define JTCEEI_S_INT_EN (1LL << 33)
341#define JTCEER_S_INT_EN (1LL << 32)
342#define SPARE_P_INT_EN (3LL << 29)
343#define PIO_UNMAP_RD_P_INT_EN (1LL << 28)
344#define ILL_ACC_RD_P_INT_EN (1LL << 27)
345#define EBUS_TO_P_INT_EN (1LL << 26)
346#define MB_PEA_P_INT_EN (1LL << 25)
347#define MB_PER_P_INT_EN (1LL << 24)
348#define MB_PEW_P_INT_EN (1LL << 23)
349#define UE_ASYN_P_INT_EN (1LL << 22)
350#define CE_ASYN_P_INT_EN (1LL << 21)
351#define JTE_P_INT_EN (1LL << 20)
352#define JBE_P_INT_EN (1LL << 19)
353#define JUE_P_INT_EN (1LL << 18)
354#define IJP_P_INT_EN (1LL << 17)
355#define ICISE_P_INT_EN (1LL << 16)
356#define CPE_P_INT_EN (1LL << 15)
357#define APE_P_INT_EN (1LL << 14)
358#define WR_DPE_P_INT_EN (1LL << 13)
359#define RD_DPE_P_INT_EN (1LL << 12)
360#define ILL_BMW_P_INT_EN (1LL << 11)
361#define ILL_BMR_P_INT_EN (1LL << 10)
362#define BJC_P_INT_EN (1LL << 9)
363#define PIO_UNMAP_P_INT_EN (1LL << 8)
364#define PIO_DPE_P_INT_EN (1LL << 7)
365#define PIO_CPE_P_INT_EN (1LL << 6)
366#define ILL_ACC_P_INT_EN (1LL << 5)
367#define UNSOL_RD_P_INT_EN (1LL << 4)
368#define UNSOL_INTR_P_INT_EN (1LL << 3)
369#define JTCEEW_P_INT_EN (1LL << 2)
370#define JTCEEI_P_INT_EN (1LL << 1)
371#define JTCEER_P_INT_EN (1LL << 0)
372
373/* bit test masks for the JBC Core and Block Error Status Reg */
374#define DMCINT_BIT 0x1
375#define JBCINT_BIT 0x2
376#define MERGE_BIT 0x4
377#define CSR_BIT 0x8
378
379
380/* bit test masks for the Multi Core Error Status Reg */
381#define DMC_BIT (1LL << 0)
382#define PEC_BIT (1LL << 1)
383
384/* bit test mask for the DMC Core and Block Error Status Register */
385#define IMU_BIT (1LL << 0)
386#define MMU_BIT (1LL << 1)
387
388/* test bits for the IMU Interrupt Status Register */
389
390#define IMU_SPARE_S (1LL << 42)
391#define IMU_EQ_OVER_S (1LL << 41)
392#define IMU_EQ_NOT_EN_S (1LL << 40)
393#define IMU_MSI_MAL_ERR_S (1LL << 39)
394#define IMU_MSI_PAR_ERR_S (1LL << 38)
395#define IMU_PMEACK_MES_NOT_EN_S (1LL << 37)
396#define IMU_PMPME_MES_NOT_EN_S (1LL << 36)
397#define IMU_FATAL_MES_NOT_EN_S (1LL << 35)
398#define IMU_NONFATAL_MES_NOT_EN_S (1LL << 34)
399#define IMU_COR_MES_NOT_EN_S (1LL << 33)
400#define IMU_MSI_NOT_EN_S (1LL << 32)
401#define IMU_SPARE_P (1LL << 10)
402#define IMU_EQ_OVER_P (1LL << 9)
403#define IMU_EQ_NOT_EN_P (1LL << 8)
404#define IMU_MSI_MAL_ERR_P (1LL << 7)
405#define IMU_MSI_PAR_ERR_P (1LL << 6)
406#define IMU_PMEACK_MES_NOT_EN_P (1LL << 5)
407#define IMU_PMPME_MES_NOT_EN_P (1LL << 4)
408#define IMU_FATAL_MES_NOT_EN_P (1LL << 3)
409#define IMU_NONFATAL_MES_NOT_EN_P (1LL << 2)
410#define IMU_COR_MES_NOT_EN_P (1LL << 1)
411#define IMU_MSI_NOT_EN_P (1LL << 0)
412
413/* test bits for the MMUInterrupt Status Register (0x00641010, 0x00741010) */
414#define MMU_TBW_DPE_S (1LL << 47)
415#define MMU_TBW_ERR_S (1LL << 46)
416#define MMU_TBW_UDE_S (1LL << 45)
417#define MMU_TBW_DME_S (1LL << 44)
418#define MMU_SPARE3_S (1LL << 43)
419#define MMU_SPARE2_S (1LL << 42)
420#define MMU_TTC_CAE_S (1ll << 41)
421#define MMU_TTC_DPE_S (1LL << 40)
422#define MMU_TTE_PRT_S (1LL << 39)
423#define MMU_TTEINV_S (1LL << 38)
424#define MMU_TRN_OOR_S (1LL << 37)
425#define MMU_TRN_ERR_S (1LL << 36)
426#define MMU_SPARE1_S (1LL << 35)
427#define MMU_SPARE0_S (1LL << 34)
428#define MMU_BYP_OOR_S (1LL << 33)
429#define MMU_BYP_ERR_S (1LL << 32)
430#define MMU_TBW_DPE_P (1LL << 15)
431#define MMU_TBW_ERR_P (1LL << 14)
432#define MMU_TBW_UDE_P (1LL << 13)
433#define MMU_TBW_DME_P (1LL << 12)
434#define MMU_SPARE3_P (1LL << 11)
435#define MMU_SPARE2_P (1LL << 10)
436#define MMU_TTC_CAE_P (1LL << 9)
437#define MMU_TTC_DPE_P (1LL << 8)
438#define MMU_TTE_PRT_P (1LL << 7)
439#define MMU_TTE_INV_P (1LL << 6)
440#define MMU_TRN_OOR_P (1LL << 5)
441#define MMU_TRN_ERR_P (1LL << 4)
442#define MMU_SPARE1_P (1LL << 3)
443#define MMU_SPARE0_P (1LL << 2)
444#define MMU_BYP_OOR_P (1LL << 1)
445#define MMU_BYP_ERR_P (1LL << 0)
446
447/* ILU Interrupt Status Register (0x00651010, 0x00751010) */
448#define ILU_SPARE3_S (1LL << 39)
449#define ILU_SPARE2_S (1LL << 38)
450#define ILU_SPARE1_S (1LL << 37)
451#define ILU_IHB_PE_S (1LL << 36)
452#define ILU_SPARE3_P (1LL << 7)
453#define ILU_SPARE2_P (1LL << 6)
454#define ILU_SPARE1_P (1LL << 5)
455#define ILU_IHB_PE_P (1LL << 4)
456
457/* PEC Core and Block Interrupt Status Register (0x00651808, 0x00751808) */
458#define PEC_ILU_BIT (1LL << 3)
459#define PEC_UE_BIT (1LL << 2)
460#define PEC_CE_BIT (1LL << 1)
461#define PEC_OE_BIT (1LL << 0)
462
463/* TLU Uncorrectable Error Status Clear Register (0x00691018, 0x00791018) */
464#define TLU_UR_S (1LL << 52)
465#define TLU_MFP_S (1LL << 50)
466#define TLU_ROF_S (1LL << 49)
467#define TLU_UC_S (1LL << 48)
468#define TLU_CA_S (1LL << 47)
469#define TLU_CTO_S (1LL << 46)
470#define TLU_FCP_S (1LL << 45)
471#define TLU_PP_S (1LL << 44)
472#define TLU_DLP_S (1LL << 36)
473#define TLU_TE_S (1LL << 32)
474#define TLU_UR_P (1LL << 20)
475#define TLU_MFP_P (1LL << 18)
476#define TLU_ROF_P (1LL << 17)
477#define TLU_UC_P (1LL << 16)
478#define TLU_CA_P (1LL << 15)
479#define TLU_CTO_P (1LL << 14)
480#define TLU_FCP_P (1LL << 13)
481#define TLU_PP_P (1LL << 12)
482#define TLU_DLP_P (1LL << 4)
483#define TLU_TE_P (1LL << 0)
484
485/* TLU Correctable Error Status Reg (0x6a1018, 0x7a1018) */
486#define TLU_CE_RTO_S (1LL << 44)
487#define TLU_CE_RNR_S (1LL << 40)
488#define TLU_CE_BDP_S (1LL << 39)
489#define TLU_CE_BTP_S (1LL << 38)
490#define TLU_CE_RE_S (1LL << 32)
491#define TLU_CE_RTO_P (1LL << 12)
492#define TLU_CE_RNR_P (1LL << 8)
493#define TLU_CE_BDP_P (1LL << 7)
494#define TLU_CE_BTP_P (1LL << 6)
495#define TLU_CE_RE_P (1LL << 0)
496
497/* TLU Other Events Status Register (0x681010, 0x781010) */
498#define TLU_O_SPARE_S (1LL << 55)
499#define TLU_O_MFC_S (1LL << 54)
500#define TLU_O_CTO_S (1LL << 53)
501#define TLU_O_NFP_S (1LL << 52)
502#define TLU_O_LWC_S (1LL << 51)
503#define TLU_O_MRC_S (1LL << 50)
504#define TLU_O_WUC_S (1LL << 49)
505#define TLU_O_RUC_S (1LL << 48)
506#define TLU_O_CRS_S (1LL << 47)
507#define TLU_O_IIP_S (1LL << 46)
508#define TLU_O_EDP_S (1LL << 45)
509#define TLU_O_EHP_S (1LL << 44)
510#define TLU_O_LIN_S (1LL << 43)
511#define TLU_O_LRS_S (1LL << 42)
512#define TLU_O_LDN_S (1LL << 41)
513#define TLU_O_LUP_S (1LL << 40)
514#define TLU_O_LPU_S (3LL << 38)
515#define TLU_O_ERU_S (1LL << 37)
516#define TLU_O_ERO_S (1LL << 36)
517#define TLU_O_EMP_S (1LL << 35)
518#define TLU_O_EPE_S (1LL << 34)
519#define TLU_O_ERP_S (1LL << 33)
520#define TLU_O_EIP_S (1LL << 32)
521#define TLU_O_SPARE_P (1LL << 23)
522#define TLU_O_MFC_P (1LL << 22)
523#define TLU_O_CTO_P (1LL << 21)
524#define TLU_O_NFP_P (1LL << 20)
525#define TLU_O_LWC_P (1LL << 19)
526#define TLU_O_MRC_P (1LL << 18)
527#define TLU_O_WUC_P (1LL << 17)
528#define TLU_O_RUC_P (1LL << 16)
529#define TLU_O_CRS_P (1LL << 15)
530#define TLU_O_IIP_P (1LL << 14)
531#define TLU_O_EDP_P (1LL << 13)
532#define TLU_O_EHP_P (1LL << 12)
533#define TLU_O_LIN_P (1LL << 11)
534#define TLU_O_LRS_P (1LL << 10)
535#define TLU_O_LDN_P (1LL << 9)
536#define TLU_O_LUP_P (1LL << 8)
537#define TLU_O_LPU_P (3LL << 6)
538#define TLU_O_ERU_P (1LL << 5)
539#define TLU_O_ERO_P (1LL << 4)
540#define TLU_O_EMP_P (1LL << 3)
541#define TLU_O_EPE_P (1LL << 2)
542#define TLU_O_ERP_P (1LL << 1)
543#define TLU_O_EIP_P (1LL << 0)
544
545/* LPU Link Layer Interrupt and Status Register (0x6E2210, 0x7E2210 */
546#define LPU_LLI_INT_LINK_ERR_ACT (1LL << 31)
547#define LPU_LLI_INT_UNSPRTD_DLLP (1LL << 22)
548#define LPU_LLI_INT_DLLP_RCV_ERR (1LL << 21)
549#define LPU_LLI_INT_BAD_DLLP (1LL << 20)
550#define LPU_LLI_INT_TLP_RCV_ERR (1LL << 18)
551#define LPU_LLI_INT_SRC_ERR_TLP (1LL << 17)
552#define LPU_LLI_INT_BAD_TLP (1LL << 16)
553#define LPU_LLI_INT_RTRY_BUF_UDF_ERR (1LL << 9)
554#define LPU_LLI_INT_RTRY_BUF_OVF_ERR (1LL << 8)
555#define LPU_LLI_INT_EG_TLP_MIN_ERR (1LL << 7)
556#define LPU_LLI_INT_EG_TRNC_FRM_ERR (1LL << 6)
557#define LPU_LLI_INT_RTRY_BUF_PE (1LL << 5)
558#define LPU_LLI_INT_EGRESS_PE (1LL << 4)
559#define LPU_LLI_INT_RPLAY_TMR_TO (1LL << 2) /* Use TLU copy in CE reg */
560#define LPU_LLI_INT_RPLAY_NUM_RO (1LL << 1) /* Use TLU copy in CE reg */
561#define LPU_LLI_INT_DLNK_PES (1LL << 0)
562
563/* LPU Phy Layer Interrupt and Status Register (0x6E2610, 0x7E2610 */
564#define LPU_PHY_INT_PHY_LAYER_ERR (1LL << 31)
565#define LPU_PHY_INT_KCHAR_DLLP_ERR (1LL << 11) /* Note: Don't use it */
566#define LPU_PHY_INT_ILL_END_POS_ERR (1LL << 10)
567#define LPU_PHY_INT_LNK_ERR (1LL << 9)
568#define LPU_PHY_INT_TRN_ERR (1LL << 8)
569#define LPU_PHY_INT_EDB_DET (1LL << 7)
570#define LPU_PHY_INT_SDP_END (1LL << 6) /* Note: Don't use it */
571#define LPU_PHY_INT_STP_END_EDB (1LL << 5) /* Note: Don't use it */
572#define LPU_PHY_INT_INVLD_CHAR_ERR (1LL << 4)
573#define LPU_PHY_INT_MULTI_SDP (1LL << 3)
574#define LPU_PHY_INT_MULTI_STP (1LL << 2)
575#define LPU_PHY_INT_ILL_SDP_POS (1LL << 1)
576#define LPU_PHY_INT_ILL_STP_POS (1LL << 0)
577
578/* LPU Interrupt Status Register (0x6e2040, 0x7e2040) */
579#define LPU_INT_STAT_INTERRUPT (1LL << 31)
580#define LPU_INT_STAT_INT_PERF_CNTR_2_OVFLW (1LL << 7)
581#define LPU_INT_STAT_INT_PERF_CNTR_1_OVFLW (1LL << 6)
582#define LPU_INT_STAT_INT_LINK_LAYER (1LL << 5)
583#define LPU_INT_STAT_INT_PHY_ERROR (1LL << 4)
584#define LPU_INT_STAT_INT_LTSSM (1LL << 3)
585#define LPU_INT_STAT_INT_PHY_TX (1LL << 2)
586#define LPU_INT_STAT_INT_PHY_RX (1LL << 1)
587#define LPU_INT_STAT_INT_PHY_GB (1LL << 0)
588
589
590#define PRIMARY_ERRORS_MASK 0xffffffff
591#define SECONDARY_ERRORS_MASK 0xffffffff00000000LL
592#define PRIMARY_TO_SECONDARY_SHIFT_SZ (32)
593#define ALIGN_TO_64 (32)
594
595#define TLU_CE_GROUP (TLU_CE_RTO_S | TLU_CE_RNR_S | TLU_CE_BDP_S | \
596 TLU_CE_BTP_S | TLU_CE_RE_S | TLU_CE_RTO_P | \
597 TLU_CE_RNR_P | TLU_CE_BDP_P | TLU_CE_BTP_P | \
598 TLU_CE_RE_P)
599
600#define TLU_CE_GROUP_P (TLU_CE_GROUP & PRIMARY_ERRORS_MASK)
601#define TLU_CE_GROUP_S (TLU_CE_GROUP & SECONDARY_ERRORS_MASK)
602/*
603 * TLU CE Errors have duplicates in the LPU LInk Layer Interrupt and Status Reg
604 * we will create a special TLU_CE_DUP_GROUP to use for clearing the duplicate
605 * bits in the LPU reg
606 *
607 * one to one bits and dups
608 * TLU_CE_RTO_P ->> LPU_LLI_INT_RPLAY_TMR_TO bit 12, bit 2
609 * TLU_CE_RNR_P ->> LPU_LLI_INT_RPLAY_NUM_RO bit 8, bit 1
610 * TLU_CE_BDP_P ->> LPU_LLI_INT_BAD_DLLP bit 7, bit 20
611 * TLU_CE_BTP_P ->> LPU_LLI_INT_BAD_TLP bit 6, bit 16
612 *
613 * the bit zero and the many other dup bits
614 * TLU_CE_RE_P ->> LPU_LLI_INT_DLLP_RCV_ERR
615 * and LPU_LLI_INT_TLP_RCV_ERR
616 * and
617 */
618#define TLU_CE_DUP_LPU_LLI (LPU_LLI_INT_RPLAY_TMR_TO | \
619 LPU_LLI_INT_RPLAY_NUM_RO | \
620 LPU_LLI_INT_BAD_DLLP | LPU_LLI_INT_BAD_TLP)
621
622#define TLU_OE_RECEIVE_GROUP_P (TLU_O_MFC_P | TLU_O_MRC_P | TLU_O_WUC_P | \
623 TLU_O_CTO_P | TLU_O_RUC_P | TLU_O_CRS_P)
624
625#define TLU_OE_TRANS_GROUP_P (TLU_O_MFC_P | TLU_O_CTO_P | TLU_O_WUC_P | \
626 TLU_O_RUC_P | TLU_O_CRS_P)
627
628#define TLU_OE_NO_DUP_GROUP_P (TLU_O_SPARE_P | TLU_O_MFC_P | TLU_O_CTO_P | \
629 TLU_O_NFP_P | TLU_O_LWC_P | TLU_O_IIP_P | \
630 TLU_O_EDP_P | TLU_O_EHP_P | TLU_O_LRS_P | \
631 TLU_O_LDN_P | TLU_O_LUP_P | TLU_O_LPU_P)
632
633#define TLU_OE_DUP_LLI_P (TLU_O_ERU_P | TLU_O_ERO_P | TLU_O_EMP_P | \
634 TLU_O_EPE_P | TLU_O_ERP_P | TLU_O_EIP_P)
635
636#define TLU_OE_NO_DUP_SVVS_RPT_MSK (TLU_O_IIP_P | TLU_O_EDP_P | \
637 TLU_O_EHP_P)
638
639
640#define TLU_OE_LINK_INTERRUPT_GROUP (TLU_O_LIN_P | TLU_O_LIN_S)
641#define TLU_OE_LINK_INTERRUPT_GROUP_P (TLU_OE_LINK_INTERRUPT_GROUP & \
642 PRIMARY_ERRORS_MASK)
643
644
645#define TLU_OE_TRANS_SVVS_RPT_MSK (TLU_O_WUC_P | TLU_O_RUC_P)
646
647#define IMU_EQ_NOT_EN_GROUP (IMU_EQ_NOT_EN_P | IMU_EQ_NOT_EN_S)
648
649#define IMU_EQ_OVER_GROUP (IMU_EQ_OVER_P | IMU_EQ_OVER_S)
650
651#define IMU_MSI_MES_GROUP (IMU_MSI_MAL_ERR_P | IMU_MSI_MAL_ERR_S | \
652 IMU_MSI_PAR_ERR_P | IMU_MSI_PAR_ERR_S | \
653 IMU_PMEACK_MES_NOT_EN_P | \
654 IMU_PMEACK_MES_NOT_EN_S | \
655 IMU_PMPME_MES_NOT_EN_P | \
656 IMU_PMPME_MES_NOT_EN_S | \
657 IMU_FATAL_MES_NOT_EN_P | \
658 IMU_FATAL_MES_NOT_EN_S | \
659 IMU_NONFATAL_MES_NOT_EN_P | \
660 IMU_NONFATAL_MES_NOT_EN_S | \
661 IMU_COR_MES_NOT_EN_P | \
662 IMU_COR_MES_NOT_EN_S | \
663 IMU_MSI_NOT_EN_P | IMU_MSI_NOT_EN_S)
664
665#define IMU_EQ_NOT_EN_GROUP_P (IMU_EQ_NOT_EN_GROUP & PRIMARY_ERRORS_MASK)
666#define IMU_EQ_OVER_GROUP_P (IMU_EQ_OVER_GROUP & PRIMARY_ERRORS_MASK)
667#define IMU_MSI_MES_GROUP_P (IMU_MSI_MES_GROUP & PRIMARY_ERRORS_MASK)
668
669#define IMU_EQ_NOT_EN_GROUP_S (IMU_EQ_NOT_EN_GROUP & SECONDARY_ERRORS_MASK)
670#define IMU_EQ_OVER_GROUP_S (IMU_EQ_OVER_GROUP & SECONDARY_ERRORS_MASK)
671#define IMU_MSI_MES_GROUP_S (IMU_MSI_MES_GROUP & SECONDARY_ERRORS_MASK)
672
673#define MMU_ERR_GROUP (MMU_TBW_DPE_S | MMU_TBW_ERR_S | \
674 MMU_TBW_UDE_S | MMU_TBW_DME_S | \
675 MMU_SPARE3_S | MMU_SPARE2_S | \
676 MMU_TTC_CAE_S | MMU_TTC_DPE_S | \
677 MMU_TTE_PRT_S | MMU_TTEINV_S | \
678 MMU_TRN_OOR_S | MMU_TRN_ERR_S | \
679 MMU_SPARE1_S | MMU_SPARE0_S | \
680 MMU_BYP_OOR_S | MMU_BYP_ERR_S | \
681 MMU_TBW_DPE_P | MMU_TBW_ERR_P | \
682 MMU_TBW_UDE_P | MMU_TBW_DME_P | \
683 MMU_SPARE3_P | MMU_SPARE2_P | \
684 MMU_TTC_CAE_P | MMU_TTC_DPE_P | \
685 MMU_TTE_PRT_P | MMU_TTE_INV_P | \
686 MMU_TRN_OOR_P | MMU_TRN_ERR_P | \
687 MMU_SPARE1_P | MMU_SPARE0_P | \
688 MMU_BYP_OOR_P | MMU_BYP_ERR_P)
689
690#define MMU_ERR_GROUP_P (MMU_ERR_GROUP & PRIMARY_ERRORS_MASK)
691#define MMU_ERR_GROUP_S (MMU_ERR_GROUP & SECONDARY_ERRORS_MASK)
692
693#define TLU_UE_RECV_GROUP (TLU_UR_P | TLU_UR_S | TLU_MFP_P | TLU_MFP_S | \
694 TLU_ROF_P | TLU_ROF_S | TLU_UC_P | TLU_UC_S | \
695 TLU_PP_P | TLU_PP_S)
696
697#define TLU_UE_TRANS_GROUP (TLU_CTO_P | TLU_CTO_S)
698
699#define TLU_UE_RECV_GROUP_P (TLU_UE_RECV_GROUP & PRIMARY_ERRORS_MASK)
700#define TLU_UE_RECV_GROUP_S (TLU_UE_RECV_GROUP & SECONDARY_ERRORS_MASK)
701#define TLU_UE_TRANS_GROUP_P (TLU_UE_TRANS_GROUP & PRIMARY_ERRORS_MASK)
702#define TLU_UE_TRANS_GROUP_S (TLU_UE_TRANS_GROUP & SECONDARY_ERRORS_MASK)
703
704#define JBC_FATAL_GROUP (MB_PEA_P | MB_PEA_S | CPE_P | CPE_S | \
705 APE_P | APE_S | JTCEEW_S | JTCEEI_S | \
706 JTCEER_S | JTCEEW_P | JTCEEI_P | \
707 JTCEER_P | PIO_CPE_S | PIO_CPE_P | \
708 SPARE_BIT_0_S | SPARE_BIT_0_P | \
709 SPARE_BIT_1_S | SPARE_BIT_1_P)
710
711#define JBC_FATAL_LOGING_GROUP (MB_PEA_P | CPE_P | APE_P | JTCEER_P | \
712 JTCEEI_P | PIO_CPE_P)
713
714#define DMCINT_ODC_GROUP (PIO_UNMAP_S | PIO_UNMAP_P | PIO_UNMAP_RD_S | \
715 PIO_UNMAP_RD_P | PIO_DPE_S | PIO_DPE_P | \
716 ILL_ACC_S | ILL_ACC_P | ILL_ACC_RD_S | \
717 ILL_ACC_RD_P | SPARE_BIT_2_S | SPARE_BIT_2_P)
718
719#define DMCINT_ODC_SVVS_RPT_MSK (PIO_UNMAP_P | PIO_DPE_P | ILL_ACC_P | \
720 ILL_ACC_RD_P | PIO_UNMAP_RD_P)
721
722#define DMCINT_IDC_GROUP (UNSOL_RD_S | UNSOL_RD_P | UNSOL_INTR_S | \
723 UNSOL_INTR_P)
724
725#define DMCINT_IDC_SVVS_RPT_MSK (0)
726
727#define JBUSINT_IN_GROUP (UE_ASYN_S | UE_ASYN_P | CE_ASYN_S | \
728 CE_ASYN_P | JTE_S | JTE_P | JBE_S | \
729 JBE_P | JUE_S | JUE_P | ICISE_S | \
730 ICISE_P | WR_DPE_S | WR_DPE_P | \
731 RD_DPE_S | RD_DPE_P | ILL_BMW_S | \
732 ILL_BMW_P | ILL_BMR_S | ILL_BMR_P | \
733 BJC_S | BJC_P)
734
735#define JBUSINT_IN_SVVS_RPT_MSK (UE_ASYN_P | JTE_P | JBE_P | JUE_P | ICISE_P | \
736 WR_DPE_P | RD_DPE_P | ILL_BMW_P | ILL_BMR_P)
737
738#define JBUSINT_OUT_GROUP (IJP_S | IJP_P)
739
740#define JBUSINT_OUT_SVVS_RPT_MSK (IJP_P)
741
742#define MERGE_GROUP (MB_PER_S | MB_PER_P | MB_PEW_S | \
743 MB_PEW_P)
744
745#define MERGE_SVVS_RPT_MSK (MB_PER_P | MB_PEW_P)
746
747#define CSR_GROUP (EBUS_TO_S | EBUS_TO_P)
748
749#define CSR_SVVS_RPT_MSK (EBUS_TO_P)
750
751#define DMCINT_ERRORS (DMCINT_ODC_GROUP | DMCINT_IDC_GROUP )
752#define JBCINT_ERRORS (JBUSINT_IN_GROUP | JBUSINT_OUT_GROUP )
753#define MERGE_ERRORS (MERGE_GROUP)
754#define CSR_ERRORS (CSR_GROUP)
755
756#define IMU_RDS_ERROR_BITS (IMU_MSI_MAL_ERR_P | IMU_MSI_PAR_ERR_P | \
757 IMU_PMEACK_MES_NOT_EN_P | \
758 IMU_PMPME_MES_NOT_EN_P | \
759 IMU_FATAL_MES_NOT_EN_P | \
760 IMU_NONFATAL_MES_NOT_EN_P | \
761 IMU_COR_MES_NOT_EN_P | IMU_MSI_NOT_EN_P)
762
763#define JBC_FATAL_GROUP_P (JBC_FATAL_GROUP & PRIMARY_ERRORS_MASK)
764#define DMCINT_ODC_GROUP_P (DMCINT_ODC_GROUP & PRIMARY_ERRORS_MASK)
765#define DMCINT_IDC_GROUP_P (DMCINT_IDC_GROUP & PRIMARY_ERRORS_MASK)
766#define JBUSINT_IN_GROUP_P (JBUSINT_IN_GROUP & PRIMARY_ERRORS_MASK)
767#define JBUSINT_OUT_GROUP_P (JBUSINT_OUT_GROUP & PRIMARY_ERRORS_MASK)
768#define MERGE_GROUP_P (MERGE_GROUP & PRIMARY_ERRORS_MASK)
769#define CSR_GROUP_P (CSR_GROUP & PRIMARY_ERRORS_MASK)
770
771
772#define JBC_FATAL_GROUP_S (JBC_FATAL_GROUP & SECONDARY_ERRORS_MASK)
773#define DMCINT_ODC_GROUP_S (DMCINT_ODC_GROUP & SECONDARY_ERRORS_MASK)
774#define DMCINT_IDC_GROUP_S (DMCINT_IDC_GROUP & SECONDARY_ERRORS_MASK)
775#define JBUSINT_IN_GROUP_S (JBUSINT_IN_GROUP & SECONDARY_ERRORS_MASK)
776#define JBUSINT_OUT_GROUP_S (JBUSINT_OUT_GROUP & SECONDARY_ERRORS_MASK)
777#define MERGE_GROUP_S (MERGE_GROUP & SECONDARY_ERRORS_MASK)
778#define CSR_GROUP_S (CSR_GROUP & SECONDARY_ERRORS_MASK)
779
780
781#define ILU_GROUP (ILU_SPARE3_P | ILU_SPARE2_P | \
782 ILU_SPARE1_P | ILU_IHB_PE_P | \
783 ILU_SPARE3_S | ILU_SPARE2_S | \
784 ILU_SPARE1_S | ILU_IHB_PE_S)
785
786#define ILU_GROUP_P (ILU_GROUP & PRIMARY_ERRORS_MASK)
787#define ILU_GROUP_S (ILU_GROUP & SECONDARY_ERRORS_MASK)
788
789/*
790 * The Fire registers are at :
791 *
792 * Leaf A (AID=0x1e) 0x80.0f00.0000
793 * Leaf B (AID=0x1f) 0x80.0f80.0000
794 *
795 * PCIE addresses are at:
796 * Leaf A 0xe0.0000.0000
797 * Leaf B 0xf0.0000.0000
798*/
799
800/* mondo guest epkt macro's */
801#define EPKT_FILL_HEADER(FIRE_E_rpt, scr) \
802 ldx [FIRE_E_rpt + PCIERPT_EHDL], scr ;\
803 stx scr, [FIRE_E_rpt + PCIERPT_SUN4V_EHDL] ;\
804 ldx [FIRE_E_rpt + PCIERPT_STICK], scr ;\
805 stx scr, [FIRE_E_rpt + PCIERPT_SUN4V_STICK]
806
807/* Mondo 62 related macro's */
808#define LOG_DMC_IMU_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
809 set FIRE_DLC_IMU_ICS_IMU_INT_EN_REG, tmp2 ;\
810 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
811 stx tmp1, [FIRE_rpt + PCIERPT_IMU_INTERRUPT_ENABLE] ;\
812 set FIRE_DLC_IMU_ICS_IMU_ERROR_LOG_EN_REG, tmp1 ;\
813 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
814 stx tmp1, [FIRE_rpt + PCIERPT_IMU_ERR_LOG_ENABLE] ;\
815 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS,\
816 tmp2 ;\
817 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
818 stx tmp1, [FIRE_rpt + PCIERPT_IMU_ERR_STATUS_SET]
819
820
821#define LOG_IMU_SCS_ERROR_LOG_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
822 tmp2) \
823 set FIRE_DLC_IMU_ICS_IMU_SCS_ERROR_LOG_REG, tmp2 ;\
824 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
825 stx tmp1, [FIRE_rpt + PCIERPT_IMU_SCS_ERR_LOG]
826
827#define CLEAR_IMU_EQ_NOT_EN_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
828 tmp2) \
829 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
830 tmp2 ;\
831 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
832 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
833
834#define CLEAR_IMU_EQ_NOT_EN_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
835 tmp2) \
836 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
837 tmp2 ;\
838 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
839 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
840 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
841
842#define CLEAR_IMU_SCS_ERROR_LOG_REGS_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
843 tmp1, tmp2) \
844 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
845 tmp2 ;\
846 set IMU_EQ_NOT_EN_GROUP_P, tmp1 ;\
847 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ , tmp1 ;\
848 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
849
850#define LOG_IMU_EQS_ERROR_LOG_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
851 tmp2) \
852 set FIRE_DLC_IMU_ICS_IMU_EQS_ERROR_LOG_REG, tmp2 ;\
853 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
854 stx tmp1, [FIRE_rpt + PCIERPT_IMU_EQS_ERR_LOG]
855
856#define CLEAR_IMU_EQ_OVER_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
857 tmp2) \
858 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
859 tmp2 ;\
860 set IMU_EQ_OVER_GROUP_P, tmp1 ;\
861 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
862
863#define CLEAR_IMU_EQ_OVER_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
864 tmp2) \
865 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
866 tmp2 ;\
867 set IMU_EQ_OVER_GROUP_P, tmp1 ;\
868 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
869 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
870
871#define LOG_IMU_RDS_ERROR_LOG_REG(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
872 tmp2) \
873 set FIRE_DLC_IMU_ICS_IMU_RDS_ERROR_LOG_REG, tmp2 ;\
874 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
875 stx tmp1, [FIRE_rpt + PCIERPT_IMU_RDS_ERR_LOG]
876
877#define CLEAR_IMU_MSI_MES_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
878 tmp2) \
879 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
880 tmp2 ;\
881 set IMU_MSI_MES_GROUP_P, tmp1 ;\
882 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
883
884#define CLEAR_IMU_MSI_MES_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
885 tmp2) \
886 set FIRE_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS,\
887 tmp2 ;\
888 set IMU_MSI_MES_GROUP_P, tmp1 ;\
889 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
890 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
891
892#define LOG_DMC_MMU_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
893 set FIRE_DLC_MMU_LOG, tmp2 ;\
894 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
895 stx tmp1, [FIRE_rpt + PCIERPT_MMU_ERR_LOG_ENABLE] ;\
896 set FIRE_DLC_MMU_INT_EN, tmp2 ;\
897 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
898 stx tmp1, [FIRE_rpt + PCIERPT_MMU_INTR_ENABLE] ;\
899 set FIRE_DLC_MMU_ERR_RW1S_ALIAS, tmp2 ;\
900 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
901 stx tmp1, [FIRE_rpt + PCIERPT_MMU_ERR_STATUS_SET]
902
903#define LOG_MMU_TRANS_FAULT_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
904 tmp2) \
905 set FIRE_DLC_MMU_FLTA, tmp2 ;\
906 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
907 stx tmp1, [FIRE_rpt + PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS];\
908 set FIRE_DLC_MMU_FLTS, tmp2 ;\
909 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
910 stx tmp1, [FIRE_rpt + PCIERPT_MMU_TRANSLATION_FAULT_STATUS]
911
912#define CLEAR_MMU_ERR_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
913 set FIRE_DLC_MMU_ERR_RW1C_ALIAS, tmp2 ;\
914 set MMU_ERR_GROUP_P, tmp1 ;\
915 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
916
917#define CLEAR_MMU_ERR_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
918 set FIRE_DLC_MMU_ERR_RW1C_ALIAS, tmp2 ;\
919 set MMU_ERR_GROUP_P, tmp1 ;\
920 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
921 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
922
923#define LOG_ILU_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
924 set FIRE_DLC_ILU_CIB_ILU_LOG_EN, tmp2 ;\
925 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
926 stx tmp1, [FIRE_rpt + PCIERPT_ILU_ERR_LOG_ENABLE] ;\
927 set FIRE_DLC_ILU_CIB_ILU_INT_EN, tmp2 ;\
928 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
929 stx tmp1, [FIRE_rpt + PCIERPT_ILU_INTR_ENABLE] ;\
930 set FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1S_ALIAS, tmp2 ;\
931 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
932 stx tmp1, [FIRE_rpt + PCIERPT_ILU_ERR_STATUS_SET]
933
934#define CLEAR_ILU_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
935 set FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS, tmp2 ;\
936 set ILU_GROUP_P, tmp1 ;\
937 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
938
939/* ILU_IHB_PE_P */
940#define LOG_ILU_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
941 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
942 set (PCI | INGRESS | U), tmp1 ;\
943 sllx tmp1, ALIGN_TO_64, tmp1 ;\
944 add tmp1, IS, tmp1 ;\
945 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
946 set DATA_LINK_ERROR, tmp1 ;\
947 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE]
948
949#define CLEAR_ILU_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
950 set FIRE_DLC_ILU_CIB_ILU_LOG_ERR_RW1C_ALIAS, tmp2 ;\
951 set ILU_GROUP_P, tmp1 ;\
952 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
953 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
954
955#define LOG_TLU_UE_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
956 set FIRE_PLC_TLU_CTB_TLR_UE_LOG, tmp2 ;\
957 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
958 stx tmp1, [FIRE_rpt + \
959 PCIERPT_TLU_UE_LOG_ENABLE] ;\
960 set FIRE_PLC_TLU_CTB_TLR_UE_INT_EN, tmp2 ;\
961 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
962 stx tmp1, [FIRE_rpt + \
963 PCIERPT_TLU_UE_INTR_ENABLE] ;\
964 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1S_ALIAS, tmp2 ;\
965 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
966 stx tmp1, [FIRE_rpt + \
967 PCIERPT_TLU_UE_STATUS_SET]
968
969#define LOG_TLU_UE_RCV_HDR_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
970 tmp2) \
971 set FIRE_PLC_TLU_CTB_TLR_RUE_HDR1, tmp2 ;\
972 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
973 stx tmp1, [FIRE_rpt + PCIERPT_TLU_RCV_UE_ERR_HDR1_LOG] ;\
974 set FIRE_PLC_TLU_CTB_TLR_RUE_HDR2, tmp2 ;\
975 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
976 stx tmp1, [FIRE_rpt + PCIERPT_TLU_RCV_UE_ERR_HDR2_LOG]
977
978/*
979 * bit 14, TLU_CTO_P PCI | READ | U | H | I
980 * UE/CE Regs = Conpletion Timeout, PCIe Status = IS
981 */
982#define LOG_TLU_UE_TRANS_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
983 tmp2) \
984 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
985 set FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR, tmp2 ;\
986 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
987 .pushlocals ;\
988 set TLU_CTO_P, tmp2 ;\
989 btst tmp2, tmp1 ;\
990 bnz,a,pt %xcc, 1f ;\
991 clr tmp1 ;\
992 ba,a 9f ;\
9931: ;\
994 set (PCI | READ | U | H | I), tmp1 ;\
995 sllx tmp1, ALIGN_TO_64, tmp1 ;\
996 add tmp1, IS, tmp1 ;\
997 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
998 set COMPLETION_TIMEOUT, tmp1 ;\
999 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
1000 set FIRE_PLC_TLU_CTB_TLR_TUE_HDR1, tmp2 ;\
1001 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1002 stx tmp1, [FIRE_rpt + PCIERPT_HDR1] ;\
1003 set FIRE_PLC_TLU_CTB_TLR_TUE_HDR2, tmp2 ;\
1004 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
10059: ;\
1006 .poplocals ;\
1007 stx tmp1, [FIRE_rpt + PCIERPT_HDR2]
1008
1009
1010#define LOG_TLU_UE_TRANS_EPKT_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1011 tmp2) \
1012 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1013 set FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR, tmp2 ;\
1014 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1015 .pushlocals ;\
1016 set TLU_CTO_P, tmp2 ;\
1017 btst tmp2, tmp1 ;\
1018 bnz,a,pn %xcc, 1f ;\
1019 clr tmp1 ;\
1020 ba,a 8f ;\
10211: ;\
1022 set (PCI | READ | U), tmp1 ;\
1023 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1024 add tmp1, IS, tmp1 ;\
1025 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1026 set COMPLETION_TIMEOUT, tmp1 ;\
1027 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
10288: ;\
1029 .poplocals
1030
1031
1032#define LOG_TLU_UE_FCP_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1033 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1034 set (PCI | LINK | U), tmp1 ;\
1035 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1036 add tmp1, IS, tmp1 ;\
1037 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1038 set FLOW_CONTROL_ERROR, tmp1 ;\
1039 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE]
1040
1041#define LOG_TLU_UE_CA_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1042 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1043 set (PCI | LINK | U), tmp1 ;\
1044 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1045 add tmp1, IS, tmp1 ;\
1046 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1047 set COMPLETER_ABORT, tmp1 ;\
1048 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE]
1049
1050#define LOG_TLU_UE_DLP_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1051 tmp2) \
1052 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1053 set (PCI | LINK | U), tmp1 ;\
1054 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1055 add tmp1, IS, tmp1 ;\
1056 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1057 set DATA_LINK_ERROR, tmp1 ;\
1058 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE]
1059
1060
1061#define LOG_TLU_UE_TE_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1062 tmp2) \
1063 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1064 set (PCI | LINK | U), tmp1 ;\
1065 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1066 add tmp1, IS, tmp1 ;\
1067 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1068 set DATA_LINK_ERROR, tmp1 ;\
1069 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE]
1070
1071#define CLEAR_TLU_UE_FCP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1072 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1073 set TLU_FCP_P, tmp1 ;\
1074 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1075
1076#define CLEAR_TLU_UE_FCP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1077 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1078 set TLU_FCP_P, tmp1 ;\
1079 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1080 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1081
1082#define CLEAR_TLU_UE_CA_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1083 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1084 set TLU_CA_P, tmp1 ;\
1085 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1086
1087#define CLEAR_TLU_UE_CA_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1088 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1089 set TLU_CA_P, tmp1 ;\
1090 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1091 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1092
1093#define CLEAR_TLU_UE_TE_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1094 tmp2) \
1095 /* clear the dup */ ;\
1096 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT, tmp2 ;\
1097 set LPU_PHY_INT_TRN_ERR, tmp1 ;\
1098 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1099 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1100 set TLU_TE_P, tmp1 ;\
1101 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1102
1103
1104#define CLEAR_TLU_UE_TE_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1105 tmp2) \
1106 /* clear the dup */ ;\
1107 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT, tmp2 ;\
1108 set LPU_PHY_INT_TRN_ERR, tmp1 ;\
1109 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1110 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1111 set TLU_TE_P, tmp1 ;\
1112 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1113 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1114
1115#define CLEAR_TLU_UE_DLP_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1116 tmp2) \
1117 /* clear the dup */ ;\
1118 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, tmp2 ;\
1119 set LPU_LLI_INT_DLNK_PES, tmp1 ;\
1120 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1121 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1122 set TLU_DLP_P, tmp1 ;\
1123 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1124
1125#define CLEAR_TLU_UE_DLP_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1126 tmp2) ;\
1127 /* clear the dup */ ;\
1128 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, tmp2 ;\
1129 set LPU_LLI_INT_DLNK_PES, tmp1 ;\
1130 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1131 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1132 set TLU_DLP_P, tmp1 ;\
1133 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1134 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1135
1136#define CLEAR_TLU_UE_RECV_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1137 tmp2) ;\
1138 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1139 set TLU_UE_RECV_GROUP_P, tmp1 ;\
1140 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1141
1142#define CLEAR_TLU_UE_RECV_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1143 tmp2) \
1144 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1145 set TLU_UE_RECV_GROUP_P, tmp1 ;\
1146 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1147 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1148
1149#define LOG_TLU_UE_TRANS_HDR_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1150 tmp2) \
1151 set FIRE_PLC_TLU_CTB_TLR_TUE_HDR1, tmp2 ;\
1152 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1153 stx tmp1, [FIRE_rpt + PCIERPT_TLU_TRANS_UE_ERR_HDR1_LOG] ;\
1154 set FIRE_PLC_TLU_CTB_TLR_TUE_HDR2, tmp2 ;\
1155 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1156 stx tmp1, [FIRE_rpt + PCIERPT_TLU_TRANS_UE_ERR_HDR2_LOG]
1157
1158
1159#define CLEAR_TLU_UE_TRANS_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1160 tmp2) \
1161 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1162 set TLU_UE_TRANS_GROUP_P, tmp1 ;\
1163 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1164
1165#define CLEAR_TLU_UE_TRANS_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1166 tmp2) \
1167 set FIRE_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS, tmp2 ;\
1168 set TLU_UE_TRANS_GROUP_P, tmp1 ;\
1169 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1170 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1171
1172/*
1173 * IMU RDS Error Log Register:Offset: 0x00631028
1174 *
1175 * T [63:58] The lowest 6 bits of the Type of the errored
1176 * transaction as seen by the IMU in the RDS pipe stage
1177 * L [57:48] The length of the errored transaction.
1178 * R [47:32] The REQ ID of the errored transaction.
1179 * t [31:24] The TLP tag of the errored transaction.
1180 * B [23:16] The Message code of the error, if the error is a message
1181 * otherwise the First and Last Byte Enabled if the error is a MSI
1182 * x [15:0] the first 2 bytes MSI data if the error is a MSI, (byte 1,
1183 * byte 0)
1184 *
1185 *
1186 * 6 5 4 3 2 1 0
1187 * 3210987654321098765432109876543210987654321098765432109876543210
1188 * TTTTTTLLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBBxxxxxxxxxxxxxxxx
1189 *
1190 * RDS above, convert to HDR1 below
1191 *
1192 * 00TTTTTT00000000000000LLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB
1193 *
1194 */
1195
1196
1197/*
1198 *
1199 * IMU SCS Error Log Register:Offset: 0x00631030
1200 *
1201 * T [63:58] Low 6 bits of the Type of Error transaction as seen
1202 * by the IMU SCS.
1203 * L [57:48] The length of the errored transaction.
1204 * R [47:32] The REQ ID of the errored transaction.
1205 * t [31:24] The TLP tag of the errored transaction.
1206 * B [23:16] The Message code of the error, if the error is a message
1207 * otherwise the First and Last Byte Enabled if the error is a MSI
1208 * x [5:0] EQ number that the transaction tried to go into but
1209 * was not enabled.
1210 *
1211 * 6 5 4 3 2 1 0
1212 * 3210987654321098765432109876543210987654321098765432109876543210
1213 * TTTTTTLLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB xxxxxx
1214 *
1215 * SCS above, convert to HDR1 below
1216 *
1217 * 00TTTTTT00000000000000LLLLLLLLLLRRRRRRRRRRRRRRRRttttttttBBBBBBBB
1218 *
1219 */
1220
1221#define FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(FIRE_E_rpt, \
1222 FIRE_LEAF_BASE_ADDRx, REG1, REG2, ERR_LOG_REG) \
1223 set ERR_LOG_REG, REG1 ;\
1224 ldx [FIRE_LEAF_BASE_ADDRx + REG1], REG2 ;\
1225 /* move LRtB into right place */ ;\
1226 srlx REG2, 16, REG1 ;\
1227 sllx REG1, (63-41), REG1 ;\
1228 srlx REG1, (63-41), REG1 ;\
1229 /* move T into right place */ ;\
1230 srlx REG2, 58, REG2 ;\
1231 sllx REG2, 56, REG2 ;\
1232 add REG2, REG1, REG1 ;\
1233 stx REG1, [FIRE_E_rpt + PCIERPT_HDR1]
1234/*
1235 * Bit 8
1236 */
1237#define LOG_IMU_EQ_NOT_EN_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1238 tmp1, tmp2) \
1239 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1240 set (INTR | MSIQ | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
1241 H), tmp1 ;\
1242 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1243 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1244 FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(FIRE_rpt, FIRE_LEAF_BASE_ADDR,\
1245 tmp1, tmp2, FIRE_DLC_IMU_ICS_IMU_SCS_ERROR_LOG_REG);
1246
1247#define LOG_IMU_EQ_NOT_EN_GROUP_EPKT_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1248 tmp1, tmp2) \
1249 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1250 set (INTR | MSIQ | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT), \
1251 tmp1 ;\
1252 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1253 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
1254
1255#define LOG_IMU_EQ_OVER_GROUP_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1256 tmp1, tmp2) \
1257 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1258 set (INTR | MSIQ | PHASE_UNKNOWN | OV | DIR_IRRELEVANT), \
1259 tmp1 ;\
1260 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1261 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
1262
1263
1264#define IMU_RDS_ERR_LOG_MSIINFO_SHIFT (58)
1265#define MSI64BITPATTERN (0x78) /* 1111000 64 bit msi */
1266#define MSI32BITPATTERN (0x2c) /* 1011000 32 bit msi */
1267
1268#define LOG_IMU_MSI_MES_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1269 tmp1, tmp2) \
1270 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1271 .pushlocals ;\
1272 set FIRE_DLC_IMU_ICS_IMU_ENABLED_ERROR_STATUS_REG, tmp2 ;\
1273 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1274 btst IMU_MSI_NOT_EN_P, tmp1 ;\
1275 bnz %xcc, 1f ;\
1276 btst IMU_COR_MES_NOT_EN_P, tmp1 ;\
1277 bnz %xcc, 2f ;\
1278 btst IMU_NONFATAL_MES_NOT_EN_P, tmp1 ;\
1279 bnz %xcc, 2f ;\
1280 btst IMU_FATAL_MES_NOT_EN_P, tmp1 ;\
1281 bnz %xcc, 2f ;\
1282 btst IMU_PMPME_MES_NOT_EN_P, tmp1 ;\
1283 bnz %xcc, 2f ;\
1284 btst IMU_PMEACK_MES_NOT_EN_P, tmp1 ;\
1285 bnz %xcc, 2f ;\
1286 btst IMU_MSI_PAR_ERR_P, tmp1 ;\
1287 bnz %xcc, 4f ;\
1288 btst IMU_MSI_MAL_ERR_P, tmp1 ;\
1289 bnz %xcc, 5f ;\
1290 clr tmp1 ;\
1291 ba,a 9f ;\
1292 .empty ;\
12931: ;\
1294 ldx [FIRE_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1295 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1296 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1297 bne,pn %xcc, 1f ;\
1298 nop ;\
1299 set (INTR | MSI64| PHASE_UNKNOWN | ILL | H), tmp1 ;\
1300 ba 8f ;\
1301 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13021: ;\
1303 set (INTR | MSI32| PHASE_UNKNOWN | ILL | H), tmp1 ;\
1304 ba 8f ;\
1305 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13062: ;\
1307 set (INTR | PCIEMSG | PHASE_UNKNOWN | ILL | INGRESS | H), \
1308 tmp1 ;\
1309 ba 8f ;\
1310 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13114: ;\
1312 ldx [FIRE_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1313 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1314 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1315 bne,pn %xcc, 1f ;\
1316 nop ;\
1317 set (INTR | MSI64 | PDATA | INT | DIR_UNKNOWN | H), tmp1 ;\
1318 ba 8f ;\
1319 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13201: ;\
1321 cmp tmp1, MSI32BITPATTERN /* is it 1011000 - 32 bit msi */;\
1322 set (INTR | MSI32 | PDATA | INT | DIR_UNKNOWN | H), tmp1 ;\
1323 bne,pn %xcc, 1f ;\
1324 nop ;\
1325 ba 8f ;\
1326 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13271: ;\
1328 set (INTR | INT_OP_UNKNOWN | PDATA | INT | DIR_UNKNOWN | H),\
1329 tmp1 ;\
1330 ba 8f ;\
1331 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13325: ;\
1333 ldx [FIRE_rpt + PCIERPT_IMU_RDS_ERR_LOG], tmp1 ;\
1334 srlx tmp1, IMU_RDS_ERR_LOG_MSIINFO_SHIFT, tmp1 ;\
1335 cmp tmp1, MSI64BITPATTERN /* is it 1111000 - 64 bit msi */;\
1336 bne,pn %xcc, 2f ;\
1337 nop ;\
1338 set (INTR | MSI64 | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
1339 H), tmp1 ;\
1340 ba 8f ;\
1341 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13422: ;\
1343 cmp tmp1, MSI32BITPATTERN /* is it 1011000 - 32 bit msi */;\
1344 set (INTR | MSI32 | PHASE_UNKNOWN | ILL | DIR_IRRELEVANT | \
1345 H), tmp1 ;\
1346 bne,pn %xcc, 2f ;\
1347 nop ;\
1348 ba 8f ;\
1349 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13502: ;\
1351 set (INTR | INT_OP_UNKNOWN | PHASE_UNKNOWN | ILL | \
1352 DIR_IRRELEVANT | H), tmp1 ;\
1353 sllx tmp1, ALIGN_TO_64, tmp1 ;\
13548: ;\
1355 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1356 FILL_PCIE_HDR_FIELDS_FROM_ERR_LOG(FIRE_rpt, FIRE_LEAF_BASE_ADDR,\
1357 tmp1, tmp2, FIRE_DLC_IMU_ICS_IMU_RDS_ERROR_LOG_REG) ;\
13589: ;\
1359 .poplocals
1360
1361/*
1362 * bit 17, TLU_ROF_P PCI | INGRESS | U | H | I
1363 * UE/CE Regs = Receiver Overflow, PCIe Status = IS
1364 * bit 20, TLU_UR_P PCI | INGRESS | U | H | I
1365 * UE/CE Regs = Unsupported Request, PCIe Status = IS
1366 */
1367#define LOG_TLU_UE_RECV_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1368 tmp1, tmp2) \
1369 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1370 set (PCI | INGRESS | U | H | I), tmp1 ;\
1371 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1372 add tmp1, IS, tmp1 ;\
1373 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1374 set FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR, tmp1 ;\
1375 ldx [FIRE_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1376 .pushlocals ;\
1377 set TLU_UR_P, tmp1 ;\
1378 btst tmp1, tmp2 ;\
1379 bnz %xcc, 1f ;\
1380 .empty ;\
1381 set TLU_UC_P, tmp1 ;\
1382 btst tmp1, tmp2 ;\
1383 bnz %xcc, 2f ;\
1384 .empty ;\
1385 set TLU_MFP_P, tmp1 ;\
1386 btst tmp1, tmp2 ;\
1387 bnz %xcc, 3f ;\
1388 .empty ;\
1389 set TLU_PP_P, tmp1 ;\
1390 btst tmp1, tmp2 ;\
1391 bnz %xcc, 4f ;\
1392 .empty ;\
1393 set TLU_ROF_P, tmp1 ;\
1394 btst tmp1, tmp2 ;\
1395 bnz %xcc, 5f ;\
1396 clr tmp2 ;\
1397 ba,a 9f ;\
1398 .empty ;\
13991: ;\
1400 set UNSUPPORTED_REQUEST, tmp1 ;\
1401 ba 8f ;\
1402 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14032: ;\
1404 set UNEXPECTED_COMPLETION, tmp1 ;\
1405 ba 8f ;\
1406 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14073: ;\
1408 set MALFORMED_TLP, tmp1 ;\
1409 ba 8f ;\
1410 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14114: ;\
1412 set DP, tmp1 ;\
1413 add tmp1, IS, tmp1 ;\
1414 /* rewrite the 4 bytes containing the PCIe err status */ ;\
1415 /* to include the Detected Parity bit */ ;\
1416 stuw tmp1, [FIRE_rpt + (PCIERPT_SUN4V_DESC + 4)] ;\
1417 set POISONED_TLP, tmp1 ;\
1418 ba 8f ;\
1419 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14205: ;\
1421 set RECEIVER_OVERFLOW, tmp1 ;\
1422 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14238: ;\
1424 set FIRE_PLC_TLU_CTB_TLR_RUE_HDR1, tmp1 ;\
1425 ldx [FIRE_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1426 stx tmp2, [FIRE_rpt + PCIERPT_HDR1] ;\
1427 set FIRE_PLC_TLU_CTB_TLR_RUE_HDR2, tmp1 ;\
1428 ldx [FIRE_LEAF_BASE_ADDR + tmp1], tmp2 ;\
14299: ;\
1430 .poplocals ;\
1431 stx tmp2, [FIRE_rpt + PCIERPT_HDR2]
1432
1433
1434/*
1435 * no header info fopr secondary errors
1436 */
1437#define LOG_TLU_UE_RECV_GROUP_EPKT_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1438 tmp1, tmp2) \
1439 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1440 set (PCI | INGRESS | U), tmp1 ;\
1441 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1442 add tmp1, IS, tmp1 ;\
1443 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1444 set FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR, tmp1 ;\
1445 ldx [FIRE_LEAF_BASE_ADDR + tmp1], tmp2 ;\
1446 .pushlocals ;\
1447 set TLU_UR_P, tmp1 ;\
1448 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1449 btst tmp1, tmp2 ;\
1450 bnz %xcc, 1f ;\
1451 .empty ;\
1452 set TLU_UC_P, tmp1 ;\
1453 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1454 btst tmp1, tmp2 ;\
1455 bnz %xcc, 2f ;\
1456 .empty ;\
1457 set TLU_MFP_P, tmp1 ;\
1458 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1459 btst tmp1, tmp2 ;\
1460 bnz %xcc, 3f ;\
1461 .empty ;\
1462 set TLU_PP_P, tmp1 ;\
1463 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1464 btst tmp1, tmp2 ;\
1465 bnz %xcc, 4f ;\
1466 set TLU_ROF_P, tmp1 ;\
1467 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1468 btst tmp1, tmp2 ;\
1469 bnz %xcc, 5f ;\
1470 clr tmp2 ;\
1471 ba,a 8f ;\
1472 .empty ;\
14731: ;\
1474 set UNSUPPORTED_REQUEST, tmp1 ;\
1475 ba 8f ;\
1476 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14772: ;\
1478 set UNEXPECTED_COMPLETION, tmp1 ;\
1479 ba 8f ;\
1480 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14813: ;\
1482 set MALFORMED_TLP, tmp1 ;\
1483 ba 8f ;\
1484 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14854: ;\
1486 set DP, tmp1 ;\
1487 add tmp1, IS, tmp1 ;\
1488 /* rewrite the 4 bytes containing the PCIe err status */ ;\
1489 /* to include the Detected Parity bit */ ;\
1490 stuw tmp1, [FIRE_rpt + (PCIERPT_SUN4V_DESC + 4)] ;\
1491 set POISONED_TLP, tmp1 ;\
1492 ba 8f ;\
1493 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14945: ;\
1495 set RECEIVER_OVERFLOW, tmp1 ;\
1496 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
14978: ;\
1498 .poplocals
1499
1500#define LOG_TLU_CE_GROUP_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1501 set FIRE_PLC_TLU_CTB_TLR_CE_LOG, tmp2 ;\
1502 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1503 stx tmp1, [FIRE_rpt + PCIERPT_TLU_CE_LOG_ENABLE] ;\
1504 set FIRE_PLC_TLU_CTB_TLR_CE_INT_EN, tmp2 ;\
1505 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1506 stx tmp1, [FIRE_rpt + PCIERPT_TLU_CE_INTERRUPT_ENABLE] ;\
1507 set FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1S_ALIAS, tmp2 ;\
1508 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1509 stx tmp1, [FIRE_rpt + PCIERPT_TLU_CE_STATUS]
1510
1511/*
1512 * Dup bits for figure 1-11 bits 12, 8:6 of thr LPU LLI
1513 */
1514#define CE_DUPS_FOR_BITS_12_8_7_6_OF_LPU_LLI (LPU_LLI_INT_RPLAY_NUM_RO | \
1515 LPU_LLI_INT_RPLAY_TMR_TO | LPU_LLI_INT_BAD_TLP | \
1516 LPU_LLI_INT_BAD_DLLP)
1517/*
1518 * bit 0 dup bits
1519 * 21 and 18 of the LPU LLI
1520 */
1521#define CE_DUPS_FOR_BIT_0_LPU_LLI (LPU_LLI_INT_TLP_RCV_ERR | \
1522 LPU_LLI_INT_DLLP_RCV_ERR)
1523/*
1524 * and the other bit 0 dups 11:9 and 7:0,
1525 * the third draft of PRM has bits 13, and 12 listed
1526 * the prm is wrong
1527 */
1528#define CE_DUPS_FOR_BIT_O_LPU_PHY (LPU_PHY_INT_ILL_STP_POS | \
1529 LPU_PHY_INT_ILL_SDP_POS | LPU_PHY_INT_MULTI_STP | \
1530 LPU_PHY_INT_MULTI_SDP | LPU_PHY_INT_INVLD_CHAR_ERR | \
1531 LPU_PHY_INT_STP_END_EDB | LPU_PHY_INT_SDP_END | \
1532 LPU_PHY_INT_EDB_DET | LPU_PHY_INT_LNK_ERR | \
1533 LPU_PHY_INT_ILL_END_POS_ERR | LPU_PHY_INT_KCHAR_DLLP_ERR)
1534
1535#define CLEAR_TLU_CE_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1536 /* clear any dups for bits 12, 8:6 */ ;\
1537 set CE_DUPS_FOR_BITS_12_8_7_6_OF_LPU_LLI, tmp1 ;\
1538 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, tmp2 ;\
1539 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1540 /* clear any dups for bit 0 */ ;\
1541 set CE_DUPS_FOR_BIT_0_LPU_LLI, tmp1 ;\
1542 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1543 set CE_DUPS_FOR_BIT_O_LPU_PHY, tmp1 ;\
1544 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT, tmp2 ;\
1545 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1546 set TLU_CE_GROUP_P, tmp1 ;\
1547 set FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1C_ALIAS, tmp2 ;\
1548 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1549
1550#define CLEAR_TLU_CE_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2) \
1551 /* clear any dups for bits 12, 8:6 */ ;\
1552 set CE_DUPS_FOR_BITS_12_8_7_6_OF_LPU_LLI, tmp1 ;\
1553 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, tmp2 ;\
1554 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1555 /* clear any dups for bit 0 */ ;\
1556 set CE_DUPS_FOR_BIT_0_LPU_LLI, tmp1 ;\
1557 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1558 set CE_DUPS_FOR_BIT_O_LPU_PHY, tmp1 ;\
1559 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT, tmp2 ;\
1560 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2] ;\
1561 set TLU_CE_GROUP_P, tmp1 ;\
1562 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1563 set FIRE_PLC_TLU_CTB_TLR_CE_ERR_RW1C_ALIAS, tmp2 ;\
1564 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1565
1566#define LOG_TLU_CE_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1567 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1568 .pushlocals ;\
1569 set FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR, tmp2 ;\
1570 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1571 set TLU_CE_RTO_P, tmp1 ;\
1572 btst tmp1, tmp2 ;\
1573 bnz %xcc, 1f ;\
1574 .empty ;\
1575 set TLU_CE_RNR_P, tmp1 ;\
1576 btst tmp1, tmp2 ;\
1577 bnz %xcc, 2f ;\
1578 .empty ;\
1579 set TLU_CE_BDP_P, tmp1 ;\
1580 btst tmp1, tmp2 ;\
1581 bnz %xcc, 3f ;\
1582 btst TLU_CE_BTP_P, tmp2 ;\
1583 bnz %xcc, 4f ;\
1584 .empty ;\
1585 set (PCI | INGRESS | C), tmp1 ;\
1586 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1587 add tmp1, IS, tmp1 ;\
1588 set RECEIVER_ERROR, tmp2 ;\
1589 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1590 ba 8f ;\
1591 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
15921: ;\
1593 set (PCI | EGRESS | C), tmp1 ;\
1594 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1595 add tmp1, IS, tmp1 ;\
1596 set REPLAY_TIMER_TIMEOUT, tmp2 ;\
1597 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1598 ba 8f ;\
1599 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16002: ;\
1601 set (PCI | EGRESS | C), tmp1 ;\
1602 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1603 add tmp1, IS, tmp1 ;\
1604 set REPLAY_NUM_ROLLOVER, tmp2 ;\
1605 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1606 ba 8f ;\
1607 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16083: ;\
1609 set (PCI | INGRESS), tmp1 ;\
1610 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1611 add tmp1, IS, tmp1 ;\
1612 set BAD_DLLP, tmp2 ;\
1613 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1614 ba 8f ;\
1615 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16164: ;\
1617 set (PCI | INGRESS), tmp1 ;\
1618 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1619 add tmp1, IS, tmp1 ;\
1620 set BAD_TLP, tmp2 ;\
1621 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1622 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16238: ;\
1624 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1625 .poplocals
1626
1627
1628#define LOG_TLU_CE_GROUP_EPKT_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1629 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1630 .pushlocals ;\
1631 set FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR, tmp2 ;\
1632 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1633 set TLU_CE_RTO_P, tmp1 ;\
1634 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1635 btst tmp1, tmp2 ;\
1636 bnz %xcc, 1f ;\
1637 .empty ;\
1638 set TLU_CE_RNR_P, tmp1 ;\
1639 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1640 btst tmp1, tmp2 ;\
1641 bnz %xcc, 2f ;\
1642 .empty ;\
1643 set TLU_CE_BDP_P, tmp1 ;\
1644 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1645 btst tmp1, tmp2 ;\
1646 bnz %xcc, 3f ;\
1647 set TLU_CE_BTP_P, tmp1 ;\
1648 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1649 btst tmp1, tmp2 ;\
1650 bnz %xcc, 4f ;\
1651 .empty ;\
1652 set (PCI | INGRESS | C), tmp1 ;\
1653 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1654 add tmp1, IS, tmp1 ;\
1655 set RECEIVER_ERROR, tmp2 ;\
1656 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1657 ba 8f ;\
1658 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16591: ;\
1660 set (PCI | EGRESS | C), tmp1 ;\
1661 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1662 add tmp1, IS, tmp1 ;\
1663 set REPLAY_TIMER_TIMEOUT, tmp2 ;\
1664 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1665 ba 8f ;\
1666 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16672: ;\
1668 set (PCI | EGRESS | C), tmp1 ;\
1669 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1670 add tmp1, IS, tmp1 ;\
1671 set REPLAY_NUM_ROLLOVER, tmp2 ;\
1672 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1673 ba 8f ;\
1674 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16753: ;\
1676 set (PCI | INGRESS), tmp1 ;\
1677 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1678 add tmp1, IS, tmp1 ;\
1679 set BAD_DLLP, tmp2 ;\
1680 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1681 ba 8f ;\
1682 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16834: ;\
1684 set (PCI | INGRESS), tmp1 ;\
1685 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1686 add tmp1, IS, tmp1 ;\
1687 set BAD_TLP, tmp2 ;\
1688 sllx tmp2, ALIGN_TO_64, tmp2 ;\
1689 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
16908: ;\
1691 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1692 .poplocals
1693
1694#define LOG_TLU_OE_GROUP_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, tmp2)\
1695 set FIRE_PLC_TLU_CTB_TLR_OE_LOG, tmp2 ;\
1696 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1697 stx tmp1, [FIRE_rpt + PCIERPT_TLU_OTHER_EVENT_LOG_ENABLE] ;\
1698 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1S_ALIAS, tmp2 ;\
1699 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1700 stx tmp1, [FIRE_rpt + PCIE_ERR_TLU_OTHER_EVENT_STATUS_SET] ;\
1701 set FIRE_PLC_TLU_CTB_TLR_OE_INT_EN, tmp2 ;\
1702 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1703 stx tmp1, [FIRE_rpt + PCIERPT_TLU_OTHER_EVENT_INTR_ENABLE] ;\
1704
1705#define LOG_TLU_OE_INTR_STATUS_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1706 tmp2, MASK) \
1707 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, tmp2 ;\
1708 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1709 set MASK, tmp2 ;\
1710 and tmp1, tmp2, tmp1 ;\
1711 stx tmp1, [FIRE_rpt + PCIERPT_TLU_OTHER_EVENT_INTR_STATUS] ;\
1712
1713#define LOG_TLU_OE_INTR_STATUS_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1714 tmp2, INTR_MASK) \
1715 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, tmp2 ;\
1716 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1717 set INTR_MASK, tmp2 ;\
1718 sllx tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp2 ;\
1719 and tmp1, tmp2, tmp1 ;\
1720 stx tmp1, [FIRE_rpt + PCIERPT_TLU_OTHER_EVENT_INTR_STATUS] ;\
1721
1722#define LOG_TLU_OE_RECV_GROUP_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1723 tmp2) \
1724 set FIRE_PLC_TLU_CTB_TLR_ROE_HDR1, tmp2 ;\
1725 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1726 stx tmp1, [FIRE_rpt + PCIERPT_TLU_RCV_OTHER_EVENT_HDR1_LOG] ;\
1727 set FIRE_PLC_TLU_CTB_TLR_ROE_HDR2, tmp2 ;\
1728 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1729 stx tmp1, [FIRE_rpt + PCIERPT_TLU_RCV_OTHER_EVENT_HDR2_LOG]
1730
1731#define CLEAR_TLU_OE_RECV_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1732 tmp2) \
1733 set TLU_OE_RECEIVE_GROUP_P, tmp1 ;\
1734 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1735 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1736
1737#define CLEAR_TLU_OE_RECV_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1738 tmp2) \
1739 set TLU_OE_RECEIVE_GROUP_P, tmp1 ;\
1740 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1741 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1742 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1743
1744#define CLEAR_TLU_OE_DUP_LLI_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
1745 tmp2) ;\
1746 set TLU_OE_DUP_LLI_P, tmp1 ;\
1747 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1748 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1749
1750#define CLEAR_TLU_OE_DUP_LLI_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
1751 tmp2) ;\
1752 set TLU_OE_DUP_LLI_P, tmp1 ;\
1753 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1754 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1755 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1756
1757#define CLEAR_TLU_OE_NO_DUP_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
1758 tmp2) \
1759 set TLU_OE_NO_DUP_GROUP_P, tmp1 ;\
1760 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1761 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1762
1763#define CLEAR_TLU_OE_NO_DUP_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
1764 tmp2) \
1765 set TLU_OE_NO_DUP_GROUP_P, tmp1 ;\
1766 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1767 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1768 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1769
1770#define LOG_TLU_OE_TRANS_GROUP_REGS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1,\
1771 tmp2) \
1772 set FIRE_PLC_TLU_CTB_TLR_TOE_HDR1, tmp2 ;\
1773 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1774 stx tmp1, [FIRE_rpt + PCIERPT_TLU_TRANS_OTHER_EVENT_HDR1_LOG];\
1775 set FIRE_PLC_TLU_CTB_TLR_TOE_HDR2, tmp2 ;\
1776 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1777 stx tmp1, [FIRE_rpt + PCIERPT_TLU_TRANS_OTHER_EVENT_HDR2_LOG]
1778
1779#define LOG_TLU_OE_TRANS_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1780 tmp1, tmp2) \
1781 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1782 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, tmp2 ;\
1783 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1784 set TLU_O_WUC_P, tmp1 ;\
1785 btst tmp1, tmp2 ;\
1786 .pushlocals ;\
1787 bnz %xcc, 1f ;\
1788 set TLU_O_RUC_P, tmp1 ;\
1789 btst tmp1, tmp2 ;\
1790 bnz %xcc, 2f ;\
1791 clr tmp1 ;\
1792 ba 8f ;\
1793 nop ;\
17941: ;\
1795 set (PCI | WRITE | U), tmp1 ;\
1796 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1797 add tmp1, IS, tmp1 ;\
1798 add tmp1, ST, tmp1 ;\
1799 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1800 set COMPLETER_ABORT, tmp1 ;\
1801 ba 8f ;\
1802 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
18032: ;\
1804 set (PCI | READ | U), tmp1 ;\
1805 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1806 add tmp1, IS, tmp1 ;\
1807 add tmp1, ST, tmp1 ;\
1808 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1809 set COMPLETER_ABORT, tmp1 ;\
1810 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
18118: ;\
1812 .poplocals ;\
1813 nop
1814
1815#define LOG_TLU_OE_TRANS_GROUP_EPKT_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1816 tmp1, tmp2) \
1817 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1818 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, tmp2 ;\
1819 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1820 set TLU_O_WUC_P, tmp1 ;\
1821 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1822 btst tmp1, tmp2 ;\
1823 .pushlocals ;\
1824 bnz %xcc, 1f ;\
1825 set TLU_O_RUC_P, tmp1 ;\
1826 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1827 btst tmp1, tmp2 ;\
1828 bnz %xcc, 2f ;\
1829 clr tmp1 ;\
1830 ba 8f ;\
1831 nop ;\
18321: ;\
1833 set (PCI | WRITE | U), tmp1 ;\
1834 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1835 add tmp1, IS, tmp1 ;\
1836 add tmp1, ST, tmp1 ;\
1837 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1838 set COMPLETER_ABORT, tmp1 ;\
1839 ba 8f ;\
1840 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
18412: ;\
1842 set (PCI | READ | U), tmp1 ;\
1843 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1844 add tmp1, IS, tmp1 ;\
1845 add tmp1, ST, tmp1 ;\
1846 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1847 set COMPLETER_ABORT, tmp1 ;\
1848 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
18498: ;\
1850 .poplocals ;\
1851 nop
1852
1853#define CLEAR_TLU_OE_TRANS_GROUP_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1854 tmp2) \
1855 set TLU_OE_TRANS_GROUP_P, tmp1 ;\
1856 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1857 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1858
1859
1860#define CLEAR_TLU_OE_TRANS_GROUP_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1861 tmp2) \
1862 set TLU_OE_TRANS_GROUP_P, tmp1 ;\
1863 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1864 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, tmp2 ;\
1865 stx tmp1, [FIRE_LEAF_BASE_ADDR + tmp2]
1866
1867#define LOG_TLU_OE_NO_DUP_EPKT_P_S(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
1868 tmp2) \
1869 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
1870 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, tmp2 ;\
1871 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
1872 set TLU_O_IIP_P, tmp1 ;\
1873 btst tmp1, tmp2 ;\
1874 .pushlocals ;\
1875 bnz %xcc, 1f ;\
1876 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1877 btst tmp1, tmp2 ;\
1878 bnz %xcc, 1f ;\
1879 set TLU_O_EDP_P, tmp1 ;\
1880 btst tmp1, tmp2 ;\
1881 bnz %xcc, 2f ;\
1882 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1883 btst tmp1, tmp2 ;\
1884 bnz %xcc, 2f ;\
1885 set TLU_O_EHP_P, tmp1 ;\
1886 btst tmp1, tmp2 ;\
1887 bnz %xcc, 2f ;\
1888 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1889 btst tmp1, tmp2 ;\
1890 bnz %xcc, 2f ;\
1891 set TLU_O_LRS_P, tmp1 ;\
1892 btst tmp1, tmp2 ;\
1893 bnz %xcc, 3f ;\
1894 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1895 btst tmp1, tmp2 ;\
1896 bnz %xcc, 3f ;\
1897 set TLU_O_LDN_P, tmp1 ;\
1898 btst tmp1, tmp2 ;\
1899 bnz %xcc, 3f ;\
1900 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1901 btst tmp1, tmp2 ;\
1902 bnz %xcc, 3f ;\
1903 set TLU_O_LUP_P, tmp1 ;\
1904 btst tmp1, tmp2 ;\
1905 bnz %xcc, 3f ;\
1906 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
1907 btst tmp1, tmp2 ;\
1908 bnz %xcc, 3f ;\
1909 clr tmp1 ;\
1910 ba,a 8f ;\
1911 .empty ;\
19121: ;\
1913 set (PCI | INGRESS | U), tmp1 ;\
1914 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1915 add tmp1, IS, tmp1 ;\
1916 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1917 set DATA_LINK_ERROR, tmp1 ;\
1918 ba 8f ;\
1919 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
19202: ;\
1921 set (PCI | EGRESS | U), tmp1 ;\
1922 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1923 add tmp1, IS, tmp1 ;\
1924 add tmp1, ST, tmp1 ;\
1925 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1926 set DATA_LINK_ERROR, tmp1 ;\
1927 ba 8f ;\
1928 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
19293: ;\
1930 set (PCI | LINK | U), tmp1 ;\
1931 sllx tmp1, ALIGN_TO_64, tmp1 ;\
1932 add tmp1, IS, tmp1 ;\
1933 add tmp1, ST, tmp1 ;\
1934 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
1935 set DATA_LINK_ERROR, tmp1 ;\
1936 stx tmp1, [FIRE_rpt + PCIERPT_ERROR_TYPE] ;\
19378: ;\
1938 .poplocals ;\
1939 nop
1940
1941/* LPU Link Performance Counter Control register (0x6e2110, 7e2110) */
1942#define SET_PERF_CNTR2_OVER_FLOW (1LL << 6)
1943#define SET_PERF_CNTR1_OVER_FLOW (1LL << 5)
1944#define RST_PERF_CNTR2_OVER_FLOW (1LL << 3)
1945#define RST_PERF_CNTR2 (1LL << 2)
1946#define RST_PERF_CNTR1_OVER_FLOW (1LL << 1)
1947#define RST_PERF_CNTR1 (1LL << 0)
1948
1949#define LOG_PCIERPT_LPU_INTR_STATUS(FIRE_rpt, FIRE_LEAF_BASE_ADDR, LOGBIT, \
1950 scr1, scr2) \
1951 set LOGBIT, scr1 ;\
1952 stx scr1, [FIRE_rpt + PCIERPT_LPU_INTR_STATUS]
1953
1954#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2(FIRE_rpt, \
1955 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
1956 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2, scr2 ;\
1957 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
1958 stx scr1, [FIRE_LEAF_BASE_ADDR + \
1959 PCIE_ERR_LPU_LINK_PERF_COUNTER2]
1960
1961#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1(FIRE_rpt, \
1962 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
1963 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1, scr2 ;\
1964 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
1965 stx scr1, [FIRE_LEAF_BASE_ADDR + \
1966 PCIE_ERR_LPU_LINK_PERF_COUNTER1]
1967
1968#define CLEAR_PERF_CNTR_2_OVFLW(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1969 scr1, scr2)\
1970 set RST_PERF_CNTR2_OVER_FLOW, scr2 ;\
1971 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR_CTL, scr1 ;\
1972 stx scr2, [FIRE_LEAF_BASE_ADDR + scr1]
1973
1974#define CLEAR_PERF_CNTR_1_OVFLW(FIRE_rpt, FIRE_LEAF_BASE_ADDR, \
1975 scr1, scr2)\
1976 set RST_PERF_CNTR1_OVER_FLOW, scr2 ;\
1977 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR_CTL, scr1 ;\
1978 stx scr2, [FIRE_LEAF_BASE_ADDR + scr1]
1979
1980
1981/* LPU Link Layer Interrupt and Status Register clear bits */
1982#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT_CLR_BITS \
1983 ( \
1984 (1LL << 22) | \
1985 (1LL << 21) | \
1986 (1LL << 20) | \
1987 (1LL << 18) | \
1988 (1LL << 17) | \
1989 (1LL << 16) | \
1990 (1LL << 9) | \
1991 (1LL << 8) | \
1992 (1LL << 7) | \
1993 (1LL << 6) | \
1994 (1LL << 5) | \
1995 (1LL << 4) | \
1996 (1LL << 2) | \
1997 (1LL << 1) | \
1998 (1LL << 0) )
1999
2000#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(FIRE_rpt, \
2001 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2002 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT_CLR_BITS, scr1 ;\
2003 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, scr2 ;\
2004 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2005
2006#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(FIRE_rpt, \
2007 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2008 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, scr2 ;\
2009 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2010 stx scr1, [FIRE_rpt + \
2011 PCIERPT_LPU_LINK_LAYER_INTERRUPT_AND_STATUS]
2012
2013#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT(FIRE_rpt, \
2014 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2015 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT, scr2 ;\
2016 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2017 stx scr1, [FIRE_rpt + PCIERPT_LPU_PHY_ERR_INT]
2018
2019#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT_CLR_BITS \
2020 ( \
2021 (1LL << 11) | \
2022 (1LL << 10) | \
2023 (1LL << 9) | \
2024 (1LL << 8) | \
2025 (1LL << 7) | \
2026 (1LL << 6) | \
2027 (1LL << 5) | \
2028 (1LL << 4) | \
2029 (1LL << 3) | \
2030 (1LL << 2) | \
2031 (1LL << 1) | \
2032 (1LL << 0) )
2033
2034#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT(FIRE_rpt, \
2035 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2036 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT_CLR_BITS, scr1;\
2037 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT, scr2 ;\
2038 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2039
2040#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CLR_BITS \
2041 ( \
2042 (1LL << 15) | \
2043 (1LL << 14) | \
2044 (1LL << 13) | \
2045 (1LL << 12) | \
2046 (1LL << 11) | \
2047 (1LL << 10) | \
2048 (1LL << 9) | \
2049 (1LL << 8) | \
2050 (1LL << 7) | \
2051 (1LL << 6) | \
2052 (1LL << 5) | \
2053 (1LL << 4) | \
2054 (1LL << 3) | \
2055 (1LL << 2) | \
2056 (1LL << 1) | \
2057 (1LL << 0) )
2058
2059
2060#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM(FIRE_rpt, \
2061 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2062 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_CLR_BITS, scr1 ;\
2063 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_INT, scr2 ;\
2064 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2065
2066#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM(FIRE_rpt, \
2067 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2068 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM_INT, scr2 ;\
2069 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2070 stx scr1, [FIRE_rpt + PCIERPT_LPU_LTSSM_STATUS]
2071
2072
2073#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT_CLR_BITS \
2074 ( \
2075 (1LL << 11) | \
2076 (1LL << 10) | \
2077 (1LL << 9) | \
2078 (1LL << 8) | \
2079 (1LL << 7) | \
2080 (1LL << 6) | \
2081 (1LL << 5) | \
2082 (1LL << 4) | \
2083 (1LL << 3) | \
2084 (1LL << 2) | \
2085 (1LL << 1) | \
2086 (1LL << 0) )
2087
2088#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT(FIRE_rpt, \
2089 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2090 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT_CLR_BITS, scr1;\
2091 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT, scr2 ;\
2092 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2093
2094#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT(FIRE_rpt, \
2095 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2096 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT, scr2 ;\
2097 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2098 stx scr1, [FIRE_rpt + PCIERPT_LPU_TX_PHY_INT]
2099
2100#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT_CLR_BITS \
2101 ( \
2102 (1LL << 2) | \
2103 (1LL << 1) | \
2104 (1LL << 0) )
2105
2106#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT(FIRE_rpt, \
2107 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2108 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT_CLR_BITS, scr1;\
2109 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT, scr2 ;\
2110 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2111
2112#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT(FIRE_rpt, \
2113 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2114 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT, scr2 ;\
2115 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2116 stx scr1, [FIRE_rpt + PCIERPT_LPU_RX_PHY_INT]
2117
2118/* bits 23:16 and 15:0 */
2119#define FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT_CLR_BITS \
2120 ( \
2121 ( 0xFFLL << 16) | \
2122 (0xFFFFLL << 0) )
2123
2124#define CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT(FIRE_rpt, \
2125 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2126 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT_CLR_BITS, scr1;\
2127 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_INT, scr2 ;\
2128 stx scr1, [FIRE_LEAF_BASE_ADDR + scr2]
2129
2130#define LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT(FIRE_rpt, \
2131 FIRE_LEAF_BASE_ADDR, scr1, scr2) \
2132 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_INT, scr2 ;\
2133 ldx [FIRE_LEAF_BASE_ADDR + scr2], scr1 ;\
2134 stx scr1, [FIRE_rpt + PCIERPT_LPU_GB_PHY_INT]
2135
2136/*
2137 * log MMU header and addr fields for the errors that need them
2138 */
2139#define MMU_FAULT_LOGGING_GROUP (MMU_TBW_DPE_P | MMU_TBW_ERR_P | \
2140 MMU_TBW_UDE_P | MMU_TBW_DME_P | \
2141 MMU_TTE_PRT_P | MMU_TTE_INV_P | \
2142 MMU_TRN_OOR_P | MMU_TRN_ERR_P | \
2143 MMU_BYP_OOR_P | MMU_BYP_ERR_P)
2144
2145#define LOG_MMU_FAULT_ADDR_AND_FAULT_STATUS(FIRE_E_rpt, \
2146 FIRE_LEAF_BASE_ADDRx, REG1, REG2) \
2147 set FIRE_DLC_MMU_FLTA, REG1 ;\
2148 ldx [FIRE_LEAF_BASE_ADDRx + REG1], REG2 ;\
2149 /* bits 63:2 hold the va, align value for ereport */ ;\
2150 srlx REG2, 2, REG2 ;\
2151 sllx REG2, 2, REG2 ;\
2152 stx REG2, [FIRE_E_rpt + PCIERPT_WORD4] ;\
2153 sllx REG2, 32, REG2 ;\
2154 stx REG2, [FIRE_E_rpt + PCIERPT_HDR2] ;\
2155 set FIRE_DLC_MMU_FLTS, REG1 ;\
2156 ldx [FIRE_LEAF_BASE_ADDRx + REG1], REG2 ;\
2157 /* bits 22:16 hold transaction type move to 62:56 */ ;\
2158 srlx REG2, 16, REG2 ;\
2159 sllx REG2, 56, REG2 ;\
2160 ldx [FIRE_LEAF_BASE_ADDRx + REG1], REG1 ;\
2161 /* bits 15:0 hold BDF, move to 31:16, zero upper 32 bits */ ;\
2162 sllx REG1, (63 - 15), REG1 ;\
2163 srlx REG1, 32, REG1 ;\
2164 and REG1, REG2, REG1 ;\
2165 stx REG2, [FIRE_E_rpt + PCIERPT_HDR1]
2166
2167#define LOG_MMU_ERR_GROUP_EPKT_P(FIRE_rpt, FIRE_LEAF_BASE_ADDR, tmp1, \
2168 tmp2) \
2169 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2170 set FIRE_DLC_MMU_EN_ERR, tmp2 ;\
2171 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
2172 .pushlocals ;\
2173 btst MMU_BYP_ERR_P, tmp1 ;\
2174 bnz %xcc, 1f ;\
2175 btst MMU_BYP_OOR_P, tmp1 ;\
2176 bnz %xcc, 2f ;\
2177 btst MMU_TTE_INV_P, tmp1 ;\
2178 bnz %xcc, 4f ;\
2179 btst MMU_TTE_PRT_P, tmp1 ;\
2180 bnz %xcc, 5f ;\
2181 btst MMU_TTC_DPE_P, tmp1 ;\
2182 bnz %xcc, 6f ;\
2183 btst MMU_TTC_CAE_P, tmp1 ;\
2184 bnz %xcc, 7f ;\
2185 nop ;\
2186 ba,a 8f ;\
2187 .empty ;\
21881: ;\
2189 set (MMU | BYPASS | PHASE_UNKNOWN | ILL | DIR_UNKNOWN | D | \
2190 H), tmp1 ;\
2191 ba 1f ;\
2192 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21932: ;\
2194 set (MMU | BYPASS | ADDR | ILL | RDRW | D | H), tmp1 ;\
2195 ba 1f ;\
2196 sllx tmp1, ALIGN_TO_64, tmp1 ;\
21973: ;\
2198 set (MMU | TRANSLATION | ADDR | ILL | RDRW | D | H), tmp1 ;\
2199 ba 1f ;\
2200 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22014: ;\
2202 set (MMU | TRANSLATION | PDATA | INV | DIR_UNKNOWN | D | H),\
2203 tmp1 ;\
2204 ba 1f ;\
2205 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22065: ;\
2207 set (MMU | TRANSLATION | PDATA | PROT | WRITE | D | H), \
2208 tmp1 ;\
2209 ba 1f ;\
2210 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22116: ;\
2212 set (MMU | TRANSLATION | ADDR | PHASE_IRRELEVANT| \
2213 DIR_IRRELEVANT), tmp1 ;\
2214 ba 1f ;\
2215 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22167: ;\
2217 set (MMU | TRANSLATION | PDATA | COND_IRRELEVENT | \
2218 DIR_IRRELEVANT), tmp1 ;\
2219 ba 1f ;\
2220 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22218: ;\
2222 set MMU_TBW_DME_P, tmp2 ;\
2223 btst tmp2, tmp1 ;\
2224 bnz %xcc, 2f ;\
2225 set MMU_TBW_UDE_P, tmp2 ;\
2226 btst tmp2, tmp1 ;\
2227 bnz %xcc, 2f ;\
2228 set MMU_TBW_ERR_P, tmp2 ;\
2229 btst tmp2, tmp1 ;\
2230 bnz %xcc, 3f ;\
2231 set MMU_TBW_DPE_P, tmp2 ;\
2232 btst tmp2, tmp1 ;\
2233 bnz %xcc, 4f ;\
2234 btst MMU_TRN_ERR_P, tmp1 ;\
2235 bnz %xcc, 5f ;\
2236 btst MMU_TRN_OOR_P, tmp1 ;\
2237 bnz %xcc, 6f ;\
2238 clr tmp1 ;\
2239 ba,a 1f ;\
2240 .empty ;\
22412: ;\
2242 set (MMU | TABLEWALK | PHASE_UNKNOWN | ILL | \
2243 DIR_IRRELEVANT | D | H), tmp1 ;\
2244 ba 1f ;\
2245 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22463: ;\
2247 set (MMU | TABLEWALK | PHASE_UNKNOWN | COND_UNKNOWN | \
2248 DIR_IRRELEVANT | D | H), tmp1 ;\
2249 ba 1f ;\
2250 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22514: ;\
2252 set (MMU | TABLEWALK | PDATA | INT | DIR_IRRELEVANT | D | H),\
2253 tmp1 ;\
2254 ba 1f ;\
2255 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22565: ;\
2257 set (MMU | TRANSLATION | PHASE_UNKNOWN | ILL | \
2258 DIR_IRRELEVANT | D | H), tmp1 ;\
2259 ba 1f ;\
2260 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22616: ;\
2262 set (MMU | TRANSLATION | ADDR | ILL | RDRW | D | H), tmp1 ;\
2263 sllx tmp1, ALIGN_TO_64, tmp1 ;\
22641: ;\
2265 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC] ;\
2266 set FIRE_DLC_MMU_EN_ERR, tmp2 ;\
2267 ldx [FIRE_LEAF_BASE_ADDR + tmp2], tmp1 ;\
2268 set MMU_FAULT_LOGGING_GROUP, tmp2 ;\
2269 btst tmp2, tmp1 ;\
2270 bz %xcc, 1f ;\
2271 .empty ;\
2272 LOG_MMU_FAULT_ADDR_AND_FAULT_STATUS(FIRE_rpt, FIRE_LEAF_BASE_ADDR,\
2273 tmp1, tmp2); ;\
22741: ;\
2275 .poplocals
2276
2277/* Mondo 63 related macro's */
2278#define LOG_JBUS_FATAL_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2279 set FIRE_FATAL_ERROR_LOG_REG_1, tmp1 ;\
2280 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2281 stx tmp2, [FIRE_rpt + PCIERPT_FATAL_ERR_LOG_REG_1] ;\
2282 set FIRE_FATAL_STATE_ERROR_LOG_REG, tmp1 ;\
2283 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2284 stx tmp2, [FIRE_rpt + PCIERPT_FATAL_ERR_LOG_REG_2]
2285
2286#define CLEAR_JBUS_FATAL_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2287 setx JBC_FATAL_GROUP, tmp2, tmp1 ;\
2288 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2289 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2290
2291
2292#define LOG_DMCINT_ODC_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2293 set FIRE_DMCINT_ODCD_ERROR_LOG_REG, tmp1 ;\
2294 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2295 and tmp2, DMCINT_IDC_GROUP_P, tmp1 ;\
2296 stx tmp1, [FIRE_rpt + PCIERPT_DMCINT_ODCD_ERR_LOG]
2297
2298#define CLEAR_DMCINT_ODC_P(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2299 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2300 set DMCINT_ODC_GROUP_P, tmp1 ;\
2301 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2302
2303/*
2304 * jbc_core_and_block_err_status = reg1
2305 * bit 8, PIO_UNMAP_P HOSTBUS | PIO | ADDR | UNMAP | WRITE | M
2306 * bit 7, PIO_DPE_P HOSTBUS | PIO | PDATA | INT | WRITE | M
2307 * bit 5, ILL_ACC_P HOSTBUS | PIO | PHASE_UNKNOWN | ILL | WRITE | M
2308 * bit 27, ILL_ACC_RD_P HOSTBUS | PIO | PHASE_UNKNOWN | ILL | READ | M
2309 * bit 28, PIO_UNMAP_RD_P HOSTBUS | PIO | ADDR | UNMAP | READ | M
2310 *
2311 * reg1 = jbc_core_and_block_err_status
2312 */
2313#define LOG_DMCINT_ODC_EPKT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2)\
2314 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2315 .pushlocals ;\
2316 set FIRE_DMCINT_ODCD_ERROR_LOG_REG, tmp1 ;\
2317 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
23181: ;\
2319 btst PIO_UNMAP_P, reg1 ;\
2320 bnz %xcc, 1f ;\
2321 btst PIO_DPE_P, reg1 ;\
2322 bnz %xcc, 2f ;\
2323 btst ILL_ACC_P, reg1 ;\
2324 bnz %xcc, 3f ;\
2325 .empty ;\
2326 set ILL_ACC_RD_P, tmp1 ;\
2327 btst tmp1, reg1 ;\
2328 bnz %xcc, 4f ;\
2329 .empty ;\
2330 set PIO_UNMAP_RD_P, tmp1 ;\
2331 btst tmp1, reg1 ;\
2332 bnz %xcc, 5f ;\
2333 clr tmp1 ;\
2334 ba 8f ;\
2335 clr tmp2 ;\
23361: ;\
2337 set (HOSTBUS | PIO | ADDR | UNMAP | WRITE | M), tmp1 ;\
2338 ba 8f ;\
2339 sllx tmp1, ALIGN_TO_64, tmp1 ;\
23402: ;\
2341 set (HOSTBUS | PIO | PDATA | INT | WRITE | M), tmp1 ;\
2342 ba 8f ;\
2343 sllx tmp1, ALIGN_TO_64, tmp1 ;\
23443: ;\
2345 set (HOSTBUS | PIO | PHASE_UNKNOWN | ILL | WRITE | M), tmp1 ;\
2346 ba 8f ;\
2347 sllx tmp1, ALIGN_TO_64, tmp1 ;\
23484: ;\
2349 set (HOSTBUS | PIO | PHASE_UNKNOWN | ILL | READ | M), tmp1 ;\
2350 ba 8f ;\
2351 sllx tmp1, ALIGN_TO_64, tmp1 ;\
23525: ;\
2353 set (HOSTBUS | PIO | ADDR | UNMAP | READ | M), tmp1 ;\
2354 sllx tmp1, ALIGN_TO_64, tmp1 ;\
23558: ;\
2356 .poplocals ;\
2357 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_PADDR] ;\
2358 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
2359
2360
2361
2362#define CLEAR_DMCINT_ODC_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2363 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2364 set DMCINT_ODC_GROUP_P, tmp1 ;\
2365 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2366 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2367
2368
2369#define LOG_DMCINT_IDC_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2370 set FIRE_DMCINT_IDC_ERROR_LOG_REG, tmp1 ;\
2371 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2372 stx tmp2, [FIRE_rpt + PCIERPT_DMCINT_IDC_ERR_LOG]
2373
2374#define CLEAR_DMCINT_IDC_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2375 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2376 set DMCINT_IDC_GROUP_P, tmp1 ;\
2377 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2378
2379#define CLEAR_DMCINT_IDC_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2380 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2381 set DMCINT_IDC_GROUP_P, tmp1 ;\
2382 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2383 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2384
2385#define LOG_JBCINT_IN_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1 tmp2) \
2386 set FIRE_JBCINT_IN_TRAN_ERROR_LOG_REG, tmp1 ;\
2387 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2388 stx tmp2, [FIRE_rpt + PCIERPT_JBCINT_IN_TRANS_ERR_LOG] ;\
2389 set FIRE_JBCINT_IN_STATE_ERROR_LOG_REG, tmp1 ;\
2390 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2391 stx tmp2, [FIRE_rpt + PCIERPT_JBCINT_IN_TRANS_ERR_LOG_REG_2]
2392
2393#define CLEAR_JBCINT_IN_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2394 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp1 ;\
2395 add JBUS_BASE_ADDR, tmp1, tmp2 ;\
2396 set JBUSINT_IN_GROUP_P, tmp1 ;\
2397 stx tmp1, [tmp2]
2398
2399/*
2400 * bit 22, UE_ASYN_P hostbus/dma/data/ue/read/MS, size = 64byte;
2401 * bit 20, JTE_P OS Needs to panic, not hypervisor
2402 * bit 19, JBE_P HOSTBUS | DMA | PHASE_UNKNOWN | COND_UNKNOWN
2403 * bit 18, JUE_P HOSTBUS | OP_UNKNOWN | ADDR | UNMAP | RDRW | M
2404 * bit 16, ICISE_P HOSTBUS | DMA | PDATA | UE | READ | M
2405 * bit 13, WR_DPE_P HOSTBUS | PIO | PDATA | INT | WRITE | M
2406 * bit 12, RD_DPE_P HOSTBUS | PIO | PDATA | INT | READ | M
2407 * bit 11, ILL_BMW_P HOSTBUS | PIO | PDATA | ILL | WRITE | M
2408 * bit 10, ILL_BMR_P HOSTBUS | PIO | PDATA | ILL | WRITE | M
2409 */
2410#define LOG_JBCINT_IN_EPKT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2)\
2411 .pushlocals ;\
2412 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2413 set FIRE_JBCINT_IN_TRAN_ERROR_LOG_REG, tmp1 ;\
2414 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2415 /* strip off upper bits, leaving address */ ;\
2416 FIRE_JBCINT_IN_TRAN_ERROR_LOG_ADDR_BITS(tmp2) ;\
2417 btst ILL_BMR_P, reg1 ;\
2418 bnz %xcc, 1f ;\
2419 set ILL_BMW_P, tmp1 ;\
2420 btst tmp1, reg1 ;\
2421 bnz %xcc, 1f ;\
2422 set RD_DPE_P, tmp1 ;\
2423 btst tmp1, reg1 ;\
2424 bnz %xcc, bit_RD_DPE_P ;\
2425 set ICISE_P, tmp1 ;\
2426 btst tmp1, reg1 ;\
2427 bnz 2f ;\
2428 set WR_DPE_P, tmp1 ;\
2429 btst tmp1, reg1 ;\
2430 bnz %xcc, 3f ;\
2431 set JUE_P, tmp1 ;\
2432 btst tmp1, reg1 ;\
2433 bnz %xcc, 4f ;\
2434 set JBE_P, tmp1 ;\
2435 btst tmp1, reg1 ;\
2436 bnz %xcc, 5f ;\
2437 set JTE_P, tmp1 ;\
2438 btst tmp1, reg1 ;\
2439 bnz %xcc, 6f ;\
2440 set UE_ASYN_P, tmp1 ;\
2441 btst tmp1, reg1 ;\
2442 bnz %xcc, 7f ;\
2443 set IJP_P, tmp1 ;\
2444 btst tmp1, reg1 ;\
2445 bnz %xcc, 8f ;\
2446 clr tmp1 ;\
2447 ba 9f ;\
2448 clr tmp2 ;\
24491: ;\
2450 set (HOSTBUS | PIO | PDATA | ILL | WRITE | M), tmp1 ;\
2451 ba 9f ;\
2452 sllx tmp1, ALIGN_TO_64, tmp1 ;\
2453bit_RD_DPE_P: ;\
2454 set (HOSTBUS | PIO | PDATA | INT | READ | M), tmp1 ;\
2455 ba 9f ;\
2456 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24572: ;\
2458 set (HOSTBUS | DMA | PDATA | UE | READ | M), tmp1 ;\
2459 ba 9f ;\
2460 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24613: ;\
2462 set (HOSTBUS | PIO | PDATA | INT | WRITE | M), tmp1 ;\
2463 ba 9f ;\
2464 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24654: ;\
2466 set (HOSTBUS | OP_UNKNOWN | ADDR | UNMAP | RDRW | M), tmp1 ;\
2467 ba 9f ;\
2468 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24695: ;\
2470 set (HOSTBUS | DMA | PHASE_UNKNOWN | COND_UNKNOWN), tmp1 ;\
2471 ba 9f ;\
2472 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24736: ;\
2474 set (HOSTBUS | OP_UNKNOWN | PDATA | UE | COND_IRRELEVENT), \
2475 tmp1 ;\
2476 ba 9f ;\
2477 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24787: ;\
2479 set (HOSTBUS | DMA | PDATA | UE | READ | M | S), tmp1 ;\
2480 sllx tmp1, ALIGN_TO_64, tmp1 ;\
2481 ba 9f ;\
2482 add 64, tmp1, tmp1 ;\
24838: ;\
2484 set (HOSTBUS | DMA | ADDR | ILL | WRITE | M), tmp1 ;\
2485 sllx tmp1, ALIGN_TO_64, tmp1 ;\
24869: ;\
2487 .poplocals ;\
2488 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_PADDR] ;\
2489 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
2490
2491
2492#define CLEAR_JBCINT_IN_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2493 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2494 set JBUSINT_IN_GROUP_P, tmp1 ;\
2495 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2496 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2497
2498#define LOG_JBCINT_OUT_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1, tmp2) \
2499 set FIRE_JBCINT_OUT_TRAN_ERROR_LOG_REG, tmp1 ;\
2500 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2501 stx tmp2, [FIRE_rpt + PCIERPT_JBCINT_OUT_TRANS_ERR_LOG] ;\
2502 set FIRE_JBCINT_OUT_STATE_ERROR_LOG_REG, tmp1 ;\
2503 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2504 stx tmp2, [FIRE_rpt + PCIERPT_JBCINT_OUT_TRANS_ERR_LOG_REG_2]
2505
2506/*
2507 * bit 17, IJP_P HOSTBUS | DMA | ADDR | ILL | WRITE | M
2508 */
2509#define LOG_JBCINT_OUT_EPKT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2)\
2510 .pushlocals ;\
2511 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2512 set FIRE_JBCINT_OUT_TRAN_ERROR_LOG_REG, tmp1 ;\
2513 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2514 /* strip off upper bits, leaving address */ ;\
2515 FIRE_JBCINT_OUT_TRAN_ERROR_LOG_ADDR_BITS(tmp2) ;\
2516 set IJP_P, tmp1 ;\
2517 btst tmp1, reg1 ;\
2518 bnz %xcc, 1f ;\
2519 clr tmp1 ;\
2520 ba 9f ;\
2521 clr tmp2 ;\
25221: ;\
2523 set (HOSTBUS | DMA | ADDR | ILL | WRITE | M), tmp1 ;\
2524 sllx tmp1, ALIGN_TO_64, tmp1 ;\
25259: ;\
2526 .poplocals ;\
2527 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_PADDR] ;\
2528 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
2529
2530
2531#define CLEAR_JBCINT_OUT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2532 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2533 set JBUSINT_OUT_GROUP_P, tmp1 ;\
2534 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2535
2536#define CLEAR_JBCINT_OUT_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2537 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2538 set JBUSINT_OUT_GROUP_P, tmp1 ;\
2539 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2540 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2541
2542#define LOG_MERGE_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1 tmp2) \
2543 set FIRE_MERGE_TRAN_ERROR_LOG_REG, tmp1 ;\
2544 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2545 stx tmp2, [FIRE_rpt + PCIERPT_MERGE_TRANS_ERR_LOG]
2546
2547#define CLEAR_MERGE_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2548 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2549 set MERGE_GROUP_P, tmp1 ;\
2550 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2551
2552/*
2553 * bit 24, MB_PER_P HOSTBUS | DMA | PDATA | INT | READ | M | S size =64
2554 * bit 23, MB_PEW_P HOSTBUS | DMA | PDATA | INT | WRITE | M | S size =64
2555 */
2556#define LOG_MERGE_ERROR_EPKT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2)\
2557 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2558 .pushlocals ;\
2559 set FIRE_MERGE_TRAN_ERROR_LOG_REG, tmp1 ;\
2560 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2561 set MB_PER_P, tmp1 ;\
2562 btst tmp1, reg1 ;\
2563 bnz %xcc, 1f ;\
2564 set MB_PEW_P, tmp1 ;\
2565 btst tmp1, reg1 ;\
2566 bnz %xcc, 2f ;\
2567 clr tmp1 ;\
2568 ba 8f ;\
2569 clr tmp2 ;\
25701: ;\
2571 set (HOSTBUS | DMA | PDATA | INT | READ | M | S), tmp1 ;\
2572 sllx tmp1, ALIGN_TO_64, tmp1 ;\
2573 ba 8f ;\
2574 add 64, tmp1, tmp1 ;\
25752: ;\
2576 set (HOSTBUS | DMA | PDATA | INT | WRITE | M | S), tmp1 ;\
2577 sllx tmp1, ALIGN_TO_64, tmp1 ;\
2578 add 64, tmp1, tmp1 ;\
25798: ;\
2580 .poplocals ;\
2581 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_PADDR] ;\
2582 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
2583
2584
2585#define CLEAR_MERGE_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2586 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2587 set MERGE_GROUP_P, tmp1 ;\
2588 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2589 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2590
2591#define LOG_CSR_REGS(FIRE_rpt, JBUS_BASE_ADDR, tmp1 tmp2) \
2592 set FIRE_DMCINT_IDC_ERROR_LOG_REG, tmp1 ;\
2593 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2594 stx tmp2, [FIRE_rpt + PCIERPT_CSR_ERR_LOG]
2595
2596#define CLEAR_CSR_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2597 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2598 set CSR_GROUP_P, tmp1 ;\
2599 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2600
2601#define CLEAR_CSR_S(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2) \
2602 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS, tmp2 ;\
2603 set CSR_GROUP_P, tmp1 ;\
2604 sllx tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, tmp1 ;\
2605 stx tmp1, [JBUS_BASE_ADDR + tmp2]
2606
2607#define EBUS_ADDRESS_SHIFT_SZ (39)
2608
2609/* bit 26, EBUS_TO_P HOSTBUS | PIO | PHASE_UNKNOWN | TO | RDRW | M */
2610#define LOG_CSR_ERRORS_P_EPKT_P(FIRE_rpt, JBUS_BASE_ADDR, reg1, tmp1, tmp2)\
2611 EPKT_FILL_HEADER(FIRE_rpt, tmp1); ;\
2612 set FIRE_CSR_ERROR_LOG_REG, tmp1 ;\
2613 ldx [JBUS_BASE_ADDR + tmp1], tmp2 ;\
2614 /* 25 bit address */ ;\
2615 sllx tmp2, EBUS_ADDRESS_SHIFT_SZ, tmp2 ;\
2616 srlx tmp2, EBUS_ADDRESS_SHIFT_SZ, tmp2 ;\
2617 set (HOSTBUS | PIO | PHASE_UNKNOWN | TO | RDRW | M), tmp1 ;\
2618 sllx tmp1, ALIGN_TO_64, tmp1 ;\
2619 stx tmp2, [FIRE_rpt + PCIERPT_ERROR_PADDR] ;\
2620 stx tmp1, [FIRE_rpt + PCIERPT_SUN4V_DESC]
2621/* END CSTYLED */
2622
2623
2624#ifdef __cplusplus
2625}
2626#endif
2627
2628#endif /* _ONTARIO_VPCI_ERRS_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.