projects / OpenSPARC-T2-SAM / blame
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1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * Hypervisor Software File: hcall_niagara.s | |
| 5 | * | |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 7 | * | |
| 8 | * - Do no alter or remove copyright notices | |
| 9 | * | |
| 10 | * - Redistribution and use of this software in source and binary forms, with | |
| 11 | * or without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistribution of source code must retain the above copyright notice, | |
| 15 | * this list of conditions and the following disclaimer. | |
| 16 | * | |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
| 18 | * this list of conditions and the following disclaimer in the | |
| 19 | * documentation and/or other materials provided with the distribution. | |
| 20 | * | |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 22 | * may be used to endorse or promote products derived from this software | |
| 23 | * without specific prior written permission. | |
| 24 | * | |
| 25 | * This software is provided "AS IS," without a warranty of any kind. | |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 37 | * | |
| 38 | * You acknowledge that this software is not designed, licensed or | |
| 39 | * intended for use in the design, construction, operation or maintenance of | |
| 40 | * any nuclear facility. | |
| 41 | * | |
| 42 | * ========== Copyright Header End ============================================ | |
| 43 | */ | |
| 44 | /* | |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
| 46 | * Use is subject to license terms. | |
| 47 | */ | |
| 48 | ||
| 49 | .ident "@(#)hcall_niagara.s 1.97 07/04/18 SMI" | |
| 50 | ||
| 51 | /* | |
| 52 | * Niagara API calls | |
| 53 | */ | |
| 54 | ||
| 55 | #include <sys/asm_linkage.h> | |
| 56 | #include <asi.h> | |
| 57 | #include <dram.h> | |
| 58 | #include <jbi_regs.h> | |
| 59 | #include <offsets.h> | |
| 60 | #include <guest.h> | |
| 61 | #include <util.h> | |
| 62 | ||
| 63 | /* | |
| 64 | * niagara_getperf | |
| 65 | * | |
| 66 | * arg0 JBUS/DRAM performance register ID (%o0) | |
| 67 | * -- | |
| 68 | * ret0 status (%o0) | |
| 69 | * ret1 Perf register value (%o1) | |
| 70 | */ | |
| 71 | ENTRY_NP(hcall_niagara_getperf) | |
| 72 | ! check if JBUS/DRAM perf registers are accessible | |
| 73 | GUEST_STRUCT(%g1) | |
| 74 | set GUEST_PERFREG_ACCESSIBLE, %g2 | |
| 75 | ldx [%g1 + %g2], %g2 | |
| 76 | brz,pn %g2, herr_noaccess | |
| 77 | .empty | |
| 78 | ||
| 79 | ! check if perfreg within range | |
| 80 | cmp %o0, NIAGARA_PERFREG_MAX | |
| 81 | bgeu,pn %xcc, herr_inval | |
| 82 | .empty | |
| 83 | ||
| 84 | set niagara_perf_paddr_table - niagara_getperf_1, %g2 | |
| 85 | niagara_getperf_1: | |
| 86 | rd %pc, %g3 | |
| 87 | add %g2, %g3, %g2 | |
| 88 | sllx %o0, 4, %o0 ! table entry offset | |
| 89 | add %o0, %g2, %g2 | |
| 90 | ldx [%g2], %g3 ! get perf reg paddr | |
| 91 | ldx [%g3], %o1 ! read perf reg | |
| 92 | HCALL_RET(EOK) | |
| 93 | SET_SIZE(hcall_niagara_getperf) | |
| 94 | ||
| 95 | /* | |
| 96 | * niagara_setperf | |
| 97 | * | |
| 98 | * arg0 JBUS/DRAM performance register ID (%o0) | |
| 99 | * arg1 perf register value (%o1) | |
| 100 | * -- | |
| 101 | * ret0 status (%o0) | |
| 102 | */ | |
| 103 | ENTRY_NP(hcall_niagara_setperf) | |
| 104 | ! check if JBUS/DRAM perf registers are accessible | |
| 105 | GUEST_STRUCT(%g1) | |
| 106 | set GUEST_PERFREG_ACCESSIBLE, %g2 | |
| 107 | ldx [%g1 + %g2], %g2 | |
| 108 | brz,pn %g2, herr_noaccess | |
| 109 | .empty | |
| 110 | ||
| 111 | ! check if perfreg within range | |
| 112 | cmp %o0, NIAGARA_PERFREG_MAX | |
| 113 | bgeu,pn %xcc, herr_inval | |
| 114 | .empty | |
| 115 | ||
| 116 | set niagara_perf_paddr_table - niagara_setperf_1, %g2 | |
| 117 | niagara_setperf_1: | |
| 118 | rd %pc, %g3 | |
| 119 | add %g2, %g3, %g2 | |
| 120 | sllx %o0, 4, %o0 ! table entry offset | |
| 121 | add %o0, %g2, %g2 | |
| 122 | ldx [%g2], %g3 ! get perf reg paddr | |
| 123 | ldx [%g2+8], %g1 ! get perf reg write mask | |
| 124 | and %g1, %o1, %g1 | |
| 125 | stx %g1, [%g3] ! write perf reg | |
| 126 | HCALL_RET(EOK) | |
| 127 | SET_SIZE(hcall_niagara_setperf) | |
| 128 | ||
| 129 | /* | |
| 130 | * Niagara JBUS/DRAM performance register physical address/mask table | |
| 131 | * (order must match performance register ID assignment) | |
| 132 | */ | |
| 133 | .section ".text" | |
| 134 | .align 8 | |
| 135 | niagara_perf_paddr_table: | |
| 136 | .xword JBI_PERF_CTL, 0xff | |
| 137 | .xword JBI_PERF_COUNT, 0xffffffffffffffff | |
| 138 | .xword DRAM_PERF_CTL0, 0xff | |
| 139 | .xword DRAM_PERF_COUNT0, 0xffffffffffffffff | |
| 140 | .xword DRAM_PERF_CTL1, 0xff | |
| 141 | .xword DRAM_PERF_COUNT1, 0xffffffffffffffff | |
| 142 | .xword DRAM_PERF_CTL2, 0xff | |
| 143 | .xword DRAM_PERF_COUNT2, 0xffffffffffffffff | |
| 144 | .xword DRAM_PERF_CTL3, 0xff | |
| 145 | .xword DRAM_PERF_COUNT3, 0xffffffffffffffff |