projects / OpenSPARC-T2-SAM / blame
| Commit | Line | Data |
|---|---|---|
| 920dae64 AT |
1 | \ ========== Copyright Header Begin ========================================== |
| 2 | \ | |
| 3 | \ Hypervisor Software File: offsets.in | |
| 4 | \ | |
| 5 | \ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | \ | |
| 7 | \ - Do no alter or remove copyright notices | |
| 8 | \ | |
| 9 | \ - Redistribution and use of this software in source and binary forms, with | |
| 10 | \ or without modification, are permitted provided that the following | |
| 11 | \ conditions are met: | |
| 12 | \ | |
| 13 | \ - Redistribution of source code must retain the above copyright notice, | |
| 14 | \ this list of conditions and the following disclaimer. | |
| 15 | \ | |
| 16 | \ - Redistribution in binary form must reproduce the above copyright notice, | |
| 17 | \ this list of conditions and the following disclaimer in the | |
| 18 | \ documentation and/or other materials provided with the distribution. | |
| 19 | \ | |
| 20 | \ Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 21 | \ may be used to endorse or promote products derived from this software | |
| 22 | \ without specific prior written permission. | |
| 23 | \ | |
| 24 | \ This software is provided "AS IS," without a warranty of any kind. | |
| 25 | \ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 26 | \ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 27 | \ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 28 | \ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 29 | \ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 30 | \ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 31 | \ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 32 | \ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 33 | \ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 34 | \ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 35 | \ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 36 | \ | |
| 37 | \ You acknowledge that this software is not designed, licensed or | |
| 38 | \ intended for use in the design, construction, operation or maintenance of | |
| 39 | \ any nuclear facility. | |
| 40 | \ | |
| 41 | \ ========== Copyright Header End ============================================ | |
| 42 | \ | |
| 43 | \ Copyright 2007 by Sun Microsystems, Inc. All rights reserved. | |
| 44 | \ Use is subject to license terms. | |
| 45 | \ | |
| 46 | \ offsets.in: input file to produce offsets.h using the stabs program | |
| 47 | \ | |
| 48 | #pragma ident "@(#)offsets.in 1.87 07/07/09 SMI" | |
| 49 | ||
| 50 | #ifndef _OFFSETS_H | |
| 51 | #define _OFFSETS_H | |
| 52 | #endif | |
| 53 | ||
| 54 | #include <sys/htypes.h> | |
| 55 | #include <sun4v/mmu.h> | |
| 56 | #include <sun4v/errs_defs.h> | |
| 57 | #include <support.h> | |
| 58 | #include <traps.h> | |
| 59 | #include <mmu.h> | |
| 60 | #include <cache.h> | |
| 61 | #include <cpu_errs_defs.h> | |
| 62 | #include <vpci_errs_defs.h> | |
| 63 | #include <hypervisor.h> | |
| 64 | #include <svc.h> | |
| 65 | #include <vdev_ops.h> | |
| 66 | #include <vdev_intr.h> | |
| 67 | #include <fire.h> | |
| 68 | #include <cpu_errs.h> | |
| 69 | #include <svc_vbsc.h> | |
| 70 | #include <ncs.h> | |
| 71 | #include <cyclic.h> | |
| 72 | #include <vcpu.h> | |
| 73 | #include <strand.h> | |
| 74 | #include <guest.h> | |
| 75 | #include <ldc.h> | |
| 76 | #include <pcie.h> | |
| 77 | #include <hvctl.h> | |
| 78 | #include <md.h> | |
| 79 | #include <md/md_impl.h> | |
| 80 | #include <vdev_simdisk.h> | |
| 81 | #include <vdev_snet.h> | |
| 82 | ||
| 83 | nametable NAMETABLE_SIZE | |
| 84 | ||
| 85 | config CONFIG_SIZE | |
| 86 | membase CONFIG_MEMBASE | |
| 87 | memsize CONFIG_MEMSIZE | |
| 88 | physmemsize CONFIG_PHYSMEMSIZE | |
| 89 | reloc CONFIG_RELOC | |
| 90 | parse_hvmd CONFIG_PARSE_HVMD | |
| 91 | active_hvmd CONFIG_ACTIVE_HVMD | |
| 92 | guests CONFIG_GUESTS | |
| 93 | mblocks CONFIG_MBLOCKS | |
| 94 | vcpus CONFIG_VCPUS | |
| 95 | strands CONFIG_STRANDS | |
| 96 | vstate CONFIG_VSTATE | |
| 97 | maus CONFIG_MAUS | |
| 98 | ldcb_pa CONFIG_LDCB_PA | |
| 99 | pcie_busses CONFIG_PCIE_BUSSES | |
| 100 | strand_startset CONFIG_STRAND_STARTSET | |
| 101 | hv_ldcs CONFIG_HV_LDCS | |
| 102 | sp_ldcs CONFIG_SP_LDCS | |
| 103 | sp_ldc_max_cid CONFIG_SP_LDC_MAX_CID | |
| 104 | hvuart_addr CONFIG_HVUART_ADDR | |
| 105 | tod CONFIG_TOD | |
| 106 | todfrequency CONFIG_TODFREQUENCY | |
| 107 | stickfrequency CONFIG_STICKFREQUENCY | |
| 108 | dummytsbp CONFIG_DUMMYTSB | |
| 109 | guests_dtnode CONFIG_GUESTS_DTNODE | |
| 110 | cpus_dtnode CONFIG_CPUS_DTNODE | |
| 111 | hv_ldcs_dtnode CONFIG_HV_LDCS_DTNODE | |
| 112 | sp_ldcs_dtnode CONFIG_SP_LDCS_DTNODE | |
| 113 | ldcb_dtnode CONFIG_LDCB_DTNODE | |
| 114 | svc CONFIG_SVCS | |
| 115 | vintr CONFIG_VINTR | |
| 116 | devs_dtnode CONFIG_DEVS_DTNODE | |
| 117 | svcs_dtnode CONFIG_SVCS_DTNODE | |
| 118 | error_svch CONFIG_ERROR_SVCH | |
| 119 | vbsc_dbgerror CONFIG_VBSC_DBGERROR | |
| 120 | vbsc_svch CONFIG_VBSC_SVCH | |
| 121 | error_lock CONFIG_ERRORLOCK | |
| 122 | hdnametable CONFIG_HDNAMETABLE | |
| 123 | memscrub_max CONFIG_MEMSCRUB_MAX | |
| 124 | intrtgt CONFIG_INTRTGT | |
| 125 | devinstancesp CONFIG_DEVINSTANCES | |
| 126 | erpt_pa CONFIG_ERPT_PA | |
| 127 | erpt_size CONFIG_ERPT_SIZE | |
| 128 | sram_erpt_buf_inuse CONFIG_SRAM_ERPT_BUF_INUSE | |
| 129 | cyclic_maxd CONFIG_CYCLIC_MAXD | |
| 130 | ce_blackout CONFIG_CE_BLACKOUT | |
| 131 | ce_poll_time CONFIG_CE_POLL_TIME | |
| 132 | single_strand_lock CONFIG_SINGLE_STRAND_LOCK | |
| 133 | strand_present CONFIG_STPRES | |
| 134 | strand_active CONFIG_STACTIVE | |
| 135 | strand_idle CONFIG_STIDLE | |
| 136 | strand_halt CONFIG_STHALT | |
| 137 | print_spinlock CONFIG_PRINT_SPINLOCK | |
| 138 | errs_to_send CONFIG_ERRS_TO_SEND | |
| 139 | heartbeat_cpu CONFIG_HEARTBEAT_CPU | |
| 140 | hvctl_hv_seq CONFIG_HVCTL_HV_SEQ | |
| 141 | hvctl_zeus_seq CONFIG_HVCTL_ZEUS_SEQ | |
| 142 | hvctl_major CONFIG_HVCTL_MAJOR | |
| 143 | hvctl_minor CONFIG_HVCTL_MINOR | |
| 144 | hvctl_state CONFIG_HVCTL_STATE | |
| 145 | hvctl_rand_num CONFIG_HVCTL_RAND_NUM | |
| 146 | hvctl_ibuf CONFIG_HVCTL_IBUF | |
| 147 | hvctl_obuf CONFIG_HVCTL_OBUF | |
| 148 | hvctl_ip CONFIG_HVCTL_IP | |
| 149 | hvctl_ldc CONFIG_HVCTL_LDC | |
| 150 | hvctl_ldc_lock CONFIG_HVCTL_LDC_LOCK | |
| 151 | del_reconf_gid CONFIG_DEL_RECONF_GID | |
| 152 | scrub_sync CONFIG_SCRUB_SYNC | |
| 153 | fpga_status_lock CONFIG_FPGA_STATUS_LOCK | |
| 154 | ignore_plx_link_hack CONFIG_IGNORE_PLX_LINK_HACK | |
| 155 | ||
| 156 | mau MAU_SIZE | |
| 157 | pid MAU_PID | |
| 158 | state MAU_STATE | |
| 159 | handle MAU_HANDLE | |
| 160 | ino MAU_INO | |
| 161 | cpuset MAU_CPUSET | |
| 162 | cpu_active MAU_CPU_ACTIVE | |
| 163 | queue MAU_QUEUE | |
| 164 | ihdlr MAU_IHDLR | |
| 165 | ||
| 166 | rwindow RWINDOW_SIZE | |
| 167 | ||
| 168 | vcpu_trapstate VCPUTRAPSTATE_SIZE | |
| 169 | tpc VCTS_TPC | |
| 170 | tnpc VCTS_TNPC | |
| 171 | tstate VCTS_TSTATE | |
| 172 | tt VCTS_TT | |
| 173 | htstate VCTS_HTSTATE | |
| 174 | ||
| 175 | vcpu_globals VCPU_GLOBALS_SIZE | |
| 176 | g VCPU_GLOBALS_G | |
| 177 | ||
| 178 | vcpustate VCPUSTATE_SIZE | |
| 179 | tl VS_TL | |
| 180 | trapstack VS_TRAPSTACK | |
| 181 | gl VS_GL | |
| 182 | globals VS_GLOBALS | |
| 183 | tba VS_TBA | |
| 184 | y VS_Y | |
| 185 | asi VS_ASI | |
| 186 | softint VS_SOFTINT | |
| 187 | pil VS_PIL | |
| 188 | gsr VS_GSR | |
| 189 | tick VS_TICK | |
| 190 | stick VS_STICK | |
| 191 | stickcompare VS_STICKCOMPARE | |
| 192 | scratchpad VS_SCRATCHPAD | |
| 193 | cwp VS_CWP | |
| 194 | wstate VS_WSTATE | |
| 195 | cansave VS_CANSAVE | |
| 196 | canrestore VS_CANRESTORE | |
| 197 | otherwin VS_OTHERWIN | |
| 198 | cleanwin VS_CLEANWIN | |
| 199 | wins VS_WINS | |
| 200 | globals VS_GLOBALS | |
| 201 | cpu_mondo_head VS_CPU_MONDO_HEAD | |
| 202 | cpu_mondo_tail VS_CPU_MONDO_TAIL | |
| 203 | dev_mondo_head VS_DEV_MONDO_HEAD | |
| 204 | dev_mondo_tail VS_DEV_MONDO_TAIL | |
| 205 | error_resumable_head VS_ERROR_RESUMABLE_HEAD | |
| 206 | error_resumable_tail VS_ERROR_RESUMABLE_TAIL | |
| 207 | error_nonresumable_head VS_ERROR_NONRESUMABLE_HEAD | |
| 208 | error_nonresumable_tail VS_ERROR_NONRESUMABLE_TAIL | |
| 209 | ||
| 210 | vcpu VCPU_SIZE | |
| 211 | guest CPU_GUEST | |
| 212 | root CPU_ROOT | |
| 213 | strand CPU_STRAND | |
| 214 | res_id CPU_RES_ID | |
| 215 | strand_slot CPU_STRAND_SLOT | |
| 216 | vid CPU_VID | |
| 217 | parttag CPU_PARTTAG | |
| 218 | maup CPU_MAU | |
| 219 | start_pc CPU_START_PC | |
| 220 | start_arg CPU_START_ARG | |
| 221 | rtba CPU_RTBA | |
| 222 | mmu_area CPU_MMU_AREA | |
| 223 | mmu_area_ra CPU_MMU_AREA_RA | |
| 224 | pending_senders CPU_PENDING_SENDERS | |
| 225 | cpuq_base CPU_CPUQ_BASE | |
| 226 | cpuq_size CPU_CPUQ_SIZE | |
| 227 | cpuq_mask CPU_CPUQ_MASK | |
| 228 | cpuq_base_ra CPU_CPUQ_BASE_RA | |
| 229 | devq_base CPU_DEVQ_BASE | |
| 230 | devq_size CPU_DEVQ_SIZE | |
| 231 | devq_mask CPU_DEVQ_MASK | |
| 232 | devq_base_ra CPU_DEVQ_BASE_RA | |
| 233 | devq_lock CPU_DEVQ_LOCK | |
| 234 | devq_shdw_tail CPU_DEVQ_SHDW_TAIL | |
| 235 | errqnr_base CPU_ERRQNR_BASE | |
| 236 | errqnr_size CPU_ERRQNR_SIZE | |
| 237 | errqnr_mask CPU_ERRQNR_MASK | |
| 238 | errqnr_base_ra CPU_ERRQNR_BASE_RA | |
| 239 | errqr_base CPU_ERRQR_BASE | |
| 240 | errqr_size CPU_ERRQR_SIZE | |
| 241 | errqr_mask CPU_ERRQR_MASK | |
| 242 | errqr_base_ra CPU_ERRQR_BASE_RA | |
| 243 | status CPU_STATUS | |
| 244 | command CPU_COMMAND | |
| 245 | lastpoke CPU_CMD_LASTPOKE | |
| 246 | arg0 CPU_CMD_ARG0 | |
| 247 | arg1 CPU_CMD_ARG1 | |
| 248 | arg2 CPU_CMD_ARG2 | |
| 249 | arg3 CPU_CMD_ARG3 | |
| 250 | arg4 CPU_CMD_ARG4 | |
| 251 | arg5 CPU_CMD_ARG5 | |
| 252 | arg6 CPU_CMD_ARG6 | |
| 253 | arg7 CPU_CMD_ARG7 | |
| 254 | vintr CPU_VINTR | |
| 255 | ntsbs_ctx0 CPU_NTSBS_CTX0 | |
| 256 | ntsbs_ctxn CPU_NTSBS_CTXn | |
| 257 | tsbds_ctx0 CPU_TSBDS_CTX0 | |
| 258 | tsbds_ctxn CPU_TSBDS_CTXn | |
| 259 | mmustat_area CPU_MMUSTAT_AREA | |
| 260 | mmustat_area_ra CPU_MMUSTAT_AREA_RA | |
| 261 | svcregs CPU_SVCREGS | |
| 262 | scr CPU_SCR | |
| 263 | ttrace_buf_size CPU_TTRACEBUF_SIZE | |
| 264 | ttrace_buf_ra CPU_TTRACEBUF_RA | |
| 265 | ttrace_buf_pa CPU_TTRACEBUF_PA | |
| 266 | ttrace_offset CPU_TTRACE_OFFSET | |
| 267 | ldc_intr_pend CPU_LDC_INTR_PEND | |
| 268 | ldc_endpoint CPU_LDC_ENDPOINT | |
| 269 | state_save_area CPU_STATE_SAVE_AREA | |
| 270 | launch_with_retry CPU_LAUNCH_WITH_RETRY | |
| 271 | util CPU_UTIL | |
| 272 | ||
| 273 | \#define CPU_SCR0 (CPU_SCR + (0 * CPU_SCR_INCR)) | |
| 274 | \#define CPU_SCR1 (CPU_SCR + (1 * CPU_SCR_INCR)) | |
| 275 | \#define CPU_SCR2 (CPU_SCR + (2 * CPU_SCR_INCR)) | |
| 276 | \#define CPU_SCR3 (CPU_SCR + (3 * CPU_SCR_INCR)) | |
| 277 | ||
| 278 | vcpu_util VCPU_UTIL_SIZE | |
| 279 | stick_last VCUTIL_STICK_LAST | |
| 280 | yield_count VCUTIL_YIELD_COUNT | |
| 281 | yield_start VCUTIL_YIELD_START | |
| 282 | ||
| 283 | \#define CPU_UTIL_STICK_LAST (CPU_UTIL + VCUTIL_STICK_LAST) | |
| 284 | \#define CPU_UTIL_YIELD_COUNT (CPU_UTIL + VCUTIL_YIELD_COUNT) | |
| 285 | \#define CPU_UTIL_YIELD_START (CPU_UTIL + VCUTIL_YIELD_START) | |
| 286 | ||
| 287 | sched_slot SCHED_SLOT_SIZE | |
| 288 | action SCHED_SLOT_ACTION | |
| 289 | arg SCHED_SLOT_ARG | |
| 290 | ||
| 291 | hvctl_header HVCTL_HEADER_SIZE | |
| 292 | op HVCTL_HEADER_OP | |
| 293 | ||
| 294 | hvctl_msg HVCTL_MSG_SIZE | |
| 295 | hdr HVCTL_MSG_HDR | |
| 296 | msg HVCTL_MSG_MSG | |
| 297 | ||
| 298 | hvm_sched HVM_SCHED_SIZE | |
| 299 | vcpup HVM_SCHED_VCPUP | |
| 300 | ||
| 301 | hvm_scrub HVM_SCRUB_SIZE | |
| 302 | start_pa HVM_SCRUB_START_PA | |
| 303 | len HVM_SCRUB_START_LEN | |
| 304 | ||
| 305 | hvm_guestcmd HVM_GUESTCMD_SIZE | |
| 306 | vcpup HVM_GUESTCMD_VCPUP | |
| 307 | arg HVM_GUESTCMD_ARG | |
| 308 | ||
| 309 | hvm_stopguest HVM_STOPGUEST_SIZE | |
| 310 | guestp HVM_STOPGUEST_GUESTP | |
| 311 | ||
| 312 | hvm HVM_SIZE | |
| 313 | cmd HVM_CMD | |
| 314 | from_strandp HVM_FROM_STRANDP | |
| 315 | args HVM_ARGS | |
| 316 | ||
| 317 | xcall_mbox XCALL_MBOX_SIZE | |
| 318 | command XCMB_COMMAND | |
| 319 | mondobuf XCMB_MONDOBUF | |
| 320 | ||
| 321 | mini_stack MINI_STACK_SIZE | |
| 322 | ptr MINI_STACK_PTR | |
| 323 | val MINI_STACK_VAL | |
| 324 | ||
| 325 | pcie_device PCIE_DEVICE_SIZE | |
| 326 | res PCIE_DEVICE_RES | |
| 327 | guestp PCIE_DEVICE_GUESTP | |
| 328 | ||
| 329 | strand STRAND_SIZE | |
| 330 | configp STRAND_CONFIGP | |
| 331 | id STRAND_ID | |
| 332 | current_slot STRAND_CURRENT_SLOT | |
| 333 | slot STRAND_SLOT | |
| 334 | xc_mb STRAND_XCALL_MBOX | |
| 335 | hv_txmondo STRAND_HV_TXMONDO | |
| 336 | hv_rxmondo STRAND_HV_RXMONDO | |
| 337 | scrub_basepa STRAND_SCRUB_BASEPA | |
| 338 | scrub_size STRAND_SCRUB_SIZE | |
| 339 | mini_stack STRAND_MINI_STACK | |
| 340 | scr STRAND_SCR | |
| 341 | ue_tmp1 STRAND_UE_TMP1 | |
| 342 | ue_tmp2 STRAND_UE_TMP2 | |
| 343 | ue_globals STRAND_UE_GLOBALS | |
| 344 | err_seq_no STRAND_ERR_SEQ_NO | |
| 345 | regerr STRAND_REGERR | |
| 346 | l2_bank STRAND_L2BANK | |
| 347 | rpt_flags STRAND_RPTFLAGS | |
| 348 | wip STRAND_WIP | |
| 349 | err_flag STRAND_ERR_FLAG | |
| 350 | err_ret STRAND_ERR_RET | |
| 351 | err_poll_itt STRAND_ERR_POLL_ITT | |
| 352 | err_poll_ret STRAND_ERR_POLL_RET | |
| 353 | err_sparc_afsr STRAND_ERR_SPARC_AFSR | |
| 354 | err_sparc_afar STRAND_ERR_SPARC_AFAR | |
| 355 | l2_line_state STRAND_L2_LINE_STATE | |
| 356 | ce_rpt STRAND_CE_RPT | |
| 357 | ue_rpt STRAND_UE_RPT | |
| 358 | io_prot STRAND_IO_PROT | |
| 359 | io_error STRAND_IO_ERROR | |
| 360 | nrpending STRAND_NRPENDING | |
| 361 | rerouted_ehdl STRAND_REROUTED_EHDL | |
| 362 | rerouted_addr STRAND_REROUTED_ADDR | |
| 363 | rerouted_stick STRAND_REROUTED_STICK | |
| 364 | rerouted_attr STRAND_REROUTED_ATTR | |
| 365 | abort_pc STRAND_ABORT_PC | |
| 366 | fail_gl STRAND_FAIL_GL | |
| 367 | fail_tl STRAND_FAIL_TL | |
| 368 | trapstate STRAND_FAIL_TRAPSTATE | |
| 369 | trapglobals STRAND_FAIL_TRAPGLOBALS | |
| 370 | strand_stack STRAND_STACK | |
| 371 | cyclic STRAND_CYCLIC | |
| 372 | ||
| 373 | \#define STRAND_SCR0 (STRAND_SCR + (0 * STRAND_SCR_INCR)) | |
| 374 | \#define STRAND_SCR1 (STRAND_SCR + (1 * STRAND_SCR_INCR)) | |
| 375 | \#define STRAND_SCR2 (STRAND_SCR + (2 * STRAND_SCR_INCR)) | |
| 376 | \#define STRAND_SCR3 (STRAND_SCR + (3 * STRAND_SCR_INCR)) | |
| 377 | ||
| 378 | mapping MAPPING_SIZE | |
| 379 | _map_entry_aligned MAPPING_ENTRY_ALIGNED | |
| 380 | icpuset MAPPING_ICPUSET | |
| 381 | dcpuset MAPPING_DCPUSET | |
| 382 | ||
| 383 | map_entry_aligned | |
| 384 | _map_data MAP_ENTRY_ALIGNED_DATA | |
| 385 | ||
| 386 | map_data | |
| 387 | va MAP_DATA_VA | |
| 388 | tte MAP_DATA_TTE | |
| 389 | ||
| 390 | \#define MAPPING_VA (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_VA) | |
| 391 | \#define MAPPING_TTE (MAPPING_ENTRY_ALIGNED + MAP_ENTRY_ALIGNED_DATA + MAP_DATA_TTE) | |
| 392 | ||
| 393 | sun4v_cpu_erpt ESUN4V_SIZE | |
| 394 | g_ehdl ESUN4V_G_EHDL | |
| 395 | g_stick ESUN4V_G_STICK | |
| 396 | edesc ESUN4V_EDESC | |
| 397 | attr ESUN4V_ATTR | |
| 398 | addr ESUN4V_ADDR | |
| 399 | sz ESUN4V_SZ | |
| 400 | g_cpuid ESUN4V_G_CPUID | |
| 401 | g_secs ESUN4V_G_SECS | |
| 402 | word5 ESUN4V_WORD5 | |
| 403 | word6 ESUN4V_WORD6 | |
| 404 | word7 ESUN4V_WORD7 | |
| 405 | ||
| 406 | evbsc EVBSC_SIZE | |
| 407 | report_type EVBSC_REPORT_TYPE | |
| 408 | fpga_tod EVBSC_FPGA_TOD | |
| 409 | ehdl EVBSC_EHDL | |
| 410 | cpuserial EVBSC_CPUSERIAL | |
| 411 | stick EVBSC_STICK | |
| 412 | cpuver EVBSC_CPUVER | |
| 413 | sparc_afsr EVBSC_SPARC_AFSR | |
| 414 | sparc_afar EVBSC_SPARC_AFAR | |
| 415 | jbi_err_log EVBSC_JBI_ERR_LOG | |
| 416 | l2_afsr EVBSC_L2_AFSR | |
| 417 | l2_afar EVBSC_L2_AFAR | |
| 418 | dram_afsr EVBSC_DRAM_AFSR | |
| 419 | dram_afar EVBSC_DRAM_AFAR | |
| 420 | dram_loc EVBSC_DRAM_LOC | |
| 421 | dram_cntr EVBSC_DRAM_CNTR | |
| 422 | tstate EVBSC_TSTATE | |
| 423 | htstate EVBSC_HTSTATE | |
| 424 | tpc EVBSC_TPC | |
| 425 | cpuid EVBSC_CPUID | |
| 426 | tt EVBSC_TT | |
| 427 | tl EVBSC_TL | |
| 428 | erren EVBSC_ERREN | |
| 429 | ediag_buf EVBSC_DIAG_BUF | |
| 430 | ||
| 431 | \#define BANK_SHIFT 6 | |
| 432 | ||
| 433 | \#define STRAND_EVBSC_L2_AFSR(n) STRAND_VBSC_ERPT + EVBSC_L2_AFSR + (n * EVBSC_L2_AFSR_INCR) | |
| 434 | ||
| 435 | \#define STRAND_EVBSC_L2_AFAR(n) STRAND_VBSC_ERPT + EVBSC_L2_AFAR + (n * EVBSC_L2_AFAR_INCR) | |
| 436 | ||
| 437 | \#define STRAND_EVBSC_DRAM_AFSR(n) STRAND_VBSC_ERPT + EVBSC_DRAM_AFSR + (n * EVBSC_DRAM_AFSR_INCR) | |
| 438 | ||
| 439 | \#define STRAND_EVBSC_DRAM_AFAR(n) STRAND_VBSC_ERPT + EVBSC_DRAM_AFAR + (n * EVBSC_DRAM_AFAR_INCR) | |
| 440 | ||
| 441 | \#define STRAND_EVBSC_DRAM_CNTR(n) STRAND_VBSC_ERPT + EVBSC_DRAM_CNTR + (n * EVBSC_DRAM_CNTR_INCR) | |
| 442 | ||
| 443 | \#define STRAND_EVBSC_DRAM_LOC(n) STRAND_VBSC_ERPT + EVBSC_DRAM_LOC + (n * EVBSC_DRAM_LOC_INCR) | |
| 444 | ||
| 445 | \#define STRAND_EVBSC_DCACHE_DATA(n) DCACHE_DATA + (n * DCACHE_DATA_INCR) | |
| 446 | ||
| 447 | \#define STRAND_EVBSC_ICACHE_DIAG_DATA(n) DIAG_BUF_ICACHE + ICACHE_DIAG_DATA + (n * ICACHE_DIAG_DATA_INCR) | |
| 448 | ||
| 449 | strand_erpt STRANDERPT_SIZE | |
| 450 | strand_sun4v_erpt STRAND_SUN4V_ERPT | |
| 451 | strand_vbsc_erpt STRAND_VBSC_ERPT | |
| 452 | unsent_pkt STRAND_UNSENT_PKT | |
| 453 | ||
| 454 | epkt EPKTSIZE | |
| 455 | sysino PCIERPT_SYSINO | |
| 456 | sun4v_ehdl PCIERPT_SUN4V_EHDL | |
| 457 | sun4v_stick PCIERPT_SUN4V_STICK | |
| 458 | sun4v_desc PCIERPT_SUN4V_DESC | |
| 459 | sun4v_specfic PCIERPT_SUN4V_SPECFIC | |
| 460 | word4 PCIERPT_WORD4 | |
| 461 | HDR1 PCIERPT_HDR1 | |
| 462 | HDR2 PCIERPT_HDR2 | |
| 463 | ||
| 464 | \#define PCIERPT_ERROR_TYPE PCIERPT_WORD4 | |
| 465 | \#define PCIERPT_ERROR_VADDR PCIERPT_WORD4 | |
| 466 | \#define PCIERPT_ERROR_PADDR PCIERPT_WORD4 | |
| 467 | \#define PCIERPT_ERROR_RADDR PCIERPT_WORD4 | |
| 468 | ||
| 469 | jbc_err JBC_ERR_SIZE | |
| 470 | report_type JBC_ERR_REPORT_TYPE_63 | |
| 471 | fpga_tod JBC_ERR_FPGA_TOD | |
| 472 | pciehdl JBC_ERR_EHDL | |
| 473 | pcistick JBC_ERR_STICK | |
| 474 | cpuver JBC_ERR_CPUVER | |
| 475 | agentid JBC_ERR_AGENTID | |
| 476 | mondo_num JBC_ERR_MONDO_NUM | |
| 477 | jbc_err_log_enable JBC_ERR_JBC_ERR_LOG_ENABLE | |
| 478 | jbc_intr_enable JBC_ERR_JBC_INTR_ENABLE | |
| 479 | jbc_intr_status JBC_ERR_JBC_INTR_STATUS | |
| 480 | jbc_error_status_set_reg JBC_ERR_JBC_ERROR_STATUS_SET_REG | |
| 481 | jbc_core_and_block_err_status JBC_ERR_JBC_CORE_AND_BLOCK_ERR_STATUS | |
| 482 | merge_trans_err_log JBC_ERR_MERGE_TRANS_ERR_LOG | |
| 483 | jbcint_in_trans_err_log JBC_ERR_JBCINT_IN_TRANS_ERR_LOG | |
| 484 | jbcint_in_trans_err_log_reg_2 JBC_ERR_JBCINT_IN_TRANS_ERR_LOG_REG_2 | |
| 485 | jbcint_out_trans_err_log JBC_ERR_JBCINT_OUT_TRANS_ERR_LOG | |
| 486 | jbcint_out_trans_err_log_reg_2 JBC_ERR_JBCINT_OUT_TRANS_ERR_LOG_REG_2 | |
| 487 | dmcint_odcd_err_log JBC_ERR_DMCINT_ODCD_ERR_LOG | |
| 488 | dmcint_idc_err_log JBC_ERR_DMCINT_IDC_ERR_LOG | |
| 489 | csr_err_log JBC_ERR_CSR_ERR_LOG | |
| 490 | fatal_err_log_reg_1 JBC_ERR_FATAL_ERR_LOG_REG_1 | |
| 491 | fatal_err_log_reg_2 JBC_ERR_FATAL_ERR_LOG_REG_2 | |
| 492 | ||
| 493 | pcie_err PCIE_ERR_SIZE | |
| 494 | report_type PCIE_ERR_REPORT_TYPE_62 | |
| 495 | dmcint_odcd_err_log PCIE_ERR_DMCINT_ODCD_ERR_LOG | |
| 496 | dmcint_idc_err_log PCIE_ERR_DMCINT_IDC_ERR_LOG | |
| 497 | fatal_err_log_reg_1 PCIE_ERR_FATAL_ERR_LOG_REG_1 | |
| 498 | fatal_err_log_reg_2 PCIE_ERR_FATAL_ERR_LOG_REG_2 | |
| 499 | multi_core_err_status PCIE_ERR_MULTI_CORE_ERR_STATUS | |
| 500 | dmc_core_and_block_err_status PCIE_ERR_DMC_CORE_AND_BLOCK_ERR_STATUS | |
| 501 | imu_interrupt_enable PCIE_ERR_IMU_INTERRUPT_ENABLE | |
| 502 | imu_err_log_enable PCIE_ERR_IMU_ERR_LOG_ENABLE | |
| 503 | imu_enabled_err_status PCIE_ERR_IMU_ENABLED_ERR_STATUS | |
| 504 | imu_err_status_set PCIE_ERR_IMU_ERR_STATUS_SET | |
| 505 | imu_scs_err_log PCIE_ERR_IMU_SCS_ERR_LOG | |
| 506 | imu_eqs_err_log PCIE_ERR_IMU_EQS_ERR_LOG | |
| 507 | imu_rds_err_log PCIE_ERR_IMU_RDS_ERR_LOG | |
| 508 | mmu_err_log_enable PCIE_ERR_MMU_ERR_LOG_ENABLE | |
| 509 | mmu_intr_enable PCIE_ERR_MMU_INTR_ENABLE | |
| 510 | mmu_intr_status PCIE_ERR_MMU_INTR_STATUS | |
| 511 | mmu_err_status_set PCIE_ERR_MMU_ERR_STATUS_SET | |
| 512 | mmu_translation_fault_address PCIE_ERR_MMU_TRANSLATION_FAULT_ADDRESS | |
| 513 | mmu_translation_fault_status PCIE_ERR_MMU_TRANSLATION_FAULT_STATUS | |
| 514 | pec_core_and_block_intr_status PCIE_ERR_PEC_CORE_AND_BLOCK_INTR_STATUS | |
| 515 | ilu_err_log_enable PCIE_ERR_ILU_ERR_LOG_ENABLE | |
| 516 | ilu_intr_enable PCIE_ERR_ILU_INTR_ENABLE | |
| 517 | ilu_intr_status PCIE_ERR_ILU_INTR_STATUS | |
| 518 | ilu_err_status_set PCIE_ERR_ILU_ERR_STATUS_SET | |
| 519 | tlu_ue_log_enable PCIE_ERR_TLU_UE_LOG_ENABLE | |
| 520 | tlu_ue_intr_enable PCIE_ERR_TLU_UE_INTR_ENABLE | |
| 521 | tlu_ue_status PCIE_ERR_TLU_UE_STATUS | |
| 522 | tlu_ue_status_set PCIE_ERR_TLU_UE_STATUS_SET | |
| 523 | tlu_ce_log_enable PCIE_ERR_TLU_CE_LOG_ENABLE | |
| 524 | tlu_ce_interrupt_enable PCIE_ERR_TLU_CE_INTERRUPT_ENABLE | |
| 525 | tlu_ce_interrupt_status PCIE_ERR_TLU_CE_INTR_STATUS | |
| 526 | tlu_ce_status PCIE_ERR_TLU_CE_STATUS | |
| 527 | tlu_receive_ue_header1_log PCIE_ERR_TLU_RCV_UE_ERR_HDR1_LOG | |
| 528 | tlu_receive_ue_header2_log PCIE_ERR_TLU_RCV_UE_ERR_HDR2_LOG | |
| 529 | tlu_transmit_ue_header1_log PCIE_ERR_TLU_TRANS_UE_ERR_HDR1_LOG | |
| 530 | tlu_transmit_ue_header2_log PCIE_ERR_TLU_TRANS_UE_ERR_HDR2_LOG | |
| 531 | lpu_phy_layer_intr_and_status PCIE_ERR_LPU_PHY_LAYER_INTR_AND_STATUS | |
| 532 | tlu_other_event_log_enable PCIE_ERR_TLU_OTHER_EVENT_LOG_ENABLE | |
| 533 | tlu_other_event_intr_enable PCIE_ERR_TLU_OTHER_EVENT_INTR_ENABLE | |
| 534 | tlu_other_event_intr_status PCIE_ERR_TLU_OTHER_EVENT_INTR_STATUS | |
| 535 | tlu_other_event_status_set PCIE_ERR_TLU_OTHER_EVENT_STATUS_SET | |
| 536 | tlu_receive_other_event_header1_log PCIE_ERR_TLU_RCV_OTHER_EVENT_HDR1_LOG | |
| 537 | tlu_receive_other_event_header2_log PCIE_ERR_TLU_RCV_OTHER_EVENT_HDR2_LOG | |
| 538 | tlu_transmit_other_event_header1_log PCIE_ERR_TLU_TRANS_OTHER_EVENT_HDR1_LOG | |
| 539 | tlu_transmit_other_event_header2_log PCIE_ERR_TLU_TRANS_OTHER_EVENT_HDR2_LOG | |
| 540 | lpu_link_layer_interrupt_and_status PCIE_ERR_LPU_LINK_LAYER_INTR_AND_STATUS | |
| 541 | lpu_intr_status PCIE_ERR_LPU_INTR_STATUS | |
| 542 | lpu_link_perf_counter2 PCIE_ERR_LPU_LINK_PERF_COUNTER2 | |
| 543 | lpu_link_perf_counter1 PCIE_ERR_LPU_LINK_PERF_COUNTER1 | |
| 544 | lpu_link_layer_interrupt_and_status PCIE_ERR_LPU_LINK_LAYER_INTERRUPT_AND_STATUS | |
| 545 | lpu_phy_layer_interrupt_and_status PCIE_ERR_LPU_PHY_ERR_INT | |
| 546 | lpu_ltssm_interrupt_and_status PCIE_ERR_LPU_LTSSM_STATUS | |
| 547 | lpu_transmit_phy_interrupt_and_status PCIE_ERR_LPU_TX_PHY_INT | |
| 548 | lpu_receive_phy_interrupt_ans_status PCIE_ERR_LPU_RX_PHY_INT | |
| 549 | lpu_gigablaze_glue_interupt_and_status PCIE_ERR_LPU_GB_PHY_INT | |
| 550 | diagbuf PCIE_ERR_DIAGBUF | |
| 551 | ||
| 552 | pci_erpt PCIERPT_SIZE | |
| 553 | pciepkt PCI_ERPT_PCIEPKT | |
| 554 | _u PCI_ERPT_U | |
| 555 | unsent_pkt PCI_UNSENT_PKT | |
| 556 | ||
| 557 | \#define PCIERPT_REPORT_TYPE_63 (PCI_ERPT_U + JBC_ERR_REPORT_TYPE_63) | |
| 558 | \#define PCIERPT_FPGA_TOD (PCI_ERPT_U + JBC_ERR_FPGA_TOD) | |
| 559 | \#define PCIERPT_EHDL (PCI_ERPT_U + JBC_ERR_EHDL) | |
| 560 | \#define PCIERPT_STICK (PCI_ERPT_U + JBC_ERR_STICK) | |
| 561 | \#define PCIERPT_CPUVER (PCI_ERPT_U + JBC_ERR_CPUVER ) | |
| 562 | \#define PCIERPT_AGENTID (PCI_ERPT_U + JBC_ERR_AGENTID) | |
| 563 | \#define PCIERPT_MONDO_NUM (PCI_ERPT_U + JBC_ERR_MONDO_NUM) | |
| 564 | \#define PCIERPT_JBC_ERR_LOG_ENABLE (PCI_ERPT_U + JBC_ERR_JBC_ERR_LOG_ENABLE) | |
| 565 | \#define PCIERPT_JBC_INTR_ENABLE (PCI_ERPT_U + JBC_ERR_JBC_INTR_ENABLE) | |
| 566 | \#define PCIERPT_JBC_INTR_STATUS (PCI_ERPT_U + JBC_ERR_JBC_INTR_STATUS) | |
| 567 | \#define PCIERPT_JBC_ERROR_STATUS_SET_REG (PCI_ERPT_U + JBC_ERR_JBC_ERROR_STATUS_SET_REG) | |
| 568 | \#define PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + JBC_ERR_JBC_CORE_AND_BLOCK_ERR_STATUS) | |
| 569 | \#define PCIERPT_MERGE_TRANS_ERR_LOG (PCI_ERPT_U + JBC_ERR_MERGE_TRANS_ERR_LOG) | |
| 570 | \#define PCIERPT_JBCINT_IN_TRANS_ERR_LOG (PCI_ERPT_U + JBC_ERR_JBCINT_IN_TRANS_ERR_LOG) | |
| 571 | \#define PCIERPT_JBCINT_IN_TRANS_ERR_LOG_REG_2 (PCI_ERPT_U + JBC_ERR_JBCINT_IN_TRANS_ERR_LOG_REG_2) | |
| 572 | \#define PCIERPT_JBCINT_OUT_TRANS_ERR_LOG (PCI_ERPT_U + JBC_ERR_JBCINT_OUT_TRANS_ERR_LOG) | |
| 573 | \#define PCIERPT_JBCINT_OUT_TRANS_ERR_LOG_REG_2 (PCI_ERPT_U + JBC_ERR_JBCINT_OUT_TRANS_ERR_LOG_REG_2) | |
| 574 | \#define PCIERPT_DMCINT_ODCD_ERR_LOG (PCI_ERPT_U + JBC_ERR_DMCINT_ODCD_ERR_LOG) | |
| 575 | \#define PCIERPT_DMCINT_IDC_ERR_LOG (PCI_ERPT_U + JBC_ERR_DMCINT_IDC_ERR_LOG) | |
| 576 | \#define PCIERPT_CSR_ERR_LOG (PCI_ERPT_U + JBC_ERR_CSR_ERR_LOG) | |
| 577 | \#define PCIERPT_FATAL_ERR_LOG_REG_1 (PCI_ERPT_U + JBC_ERR_FATAL_ERR_LOG_REG_1) | |
| 578 | \#define PCIERPT_FATAL_ERR_LOG_REG_2 (PCI_ERPT_U + JBC_ERR_FATAL_ERR_LOG_REG_2) | |
| 579 | \#define PCIERPT_REPORT_TYPE_62 (PCI_ERPT_U + PCIE_ERR_REPORT_TYPE_62) | |
| 580 | \#define PCIERPT_MULTI_CORE_ERR_STATUS (PCI_ERPT_U + PCIE_ERR_MULTI_CORE_ERR_STATUS) | |
| 581 | \#define PCIERPT_DMC_CORE_AND_BLOCK_ERR_STATUS (PCI_ERPT_U + PCIE_ERR_DMC_CORE_AND_BLOCK_ERR_STATUS) | |
| 582 | \#define PCIERPT_IMU_INTERRUPT_ENABLE (PCI_ERPT_U + PCIE_ERR_IMU_INTERRUPT_ENABLE) | |
| 583 | \#define PCIERPT_IMU_ERR_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_IMU_ERR_LOG_ENABLE) | |
| 584 | \#define PCIERPT_IMU_ENABLED_ERR_STATUS (PCI_ERPT_U + PCIE_ERR_IMU_ENABLED_ERR_STATUS) | |
| 585 | \#define PCIERPT_IMU_ERR_STATUS_SET (PCI_ERPT_U + PCIE_ERR_IMU_ERR_STATUS_SET) | |
| 586 | \#define PCIERPT_IMU_SCS_ERR_LOG (PCI_ERPT_U + PCIE_ERR_IMU_SCS_ERR_LOG) | |
| 587 | \#define PCIERPT_IMU_EQS_ERR_LOG (PCI_ERPT_U + PCIE_ERR_IMU_EQS_ERR_LOG) | |
| 588 | \#define PCIERPT_IMU_RDS_ERR_LOG (PCI_ERPT_U + PCIE_ERR_IMU_RDS_ERR_LOG) | |
| 589 | \#define PCIERPT_MMU_ERR_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_MMU_ERR_LOG_ENABLE) | |
| 590 | \#define PCIERPT_MMU_INTR_ENABLE (PCI_ERPT_U + PCIE_ERR_MMU_INTR_ENABLE) | |
| 591 | \#define PCIERPT_MMU_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_MMU_INTR_STATUS) | |
| 592 | \#define PCIERPT_MMU_ERR_STATUS_SET (PCI_ERPT_U + PCIE_ERR_MMU_ERR_STATUS_SET) | |
| 593 | \#define PCIERPT_MMU_TRANSLATION_FAULT_ADDRESS (PCI_ERPT_U + PCIE_ERR_MMU_TRANSLATION_FAULT_ADDRESS) | |
| 594 | \#define PCIERPT_MMU_TRANSLATION_FAULT_STATUS (PCI_ERPT_U + PCIE_ERR_MMU_TRANSLATION_FAULT_STATUS) | |
| 595 | \#define PCIERPT_PEC_CORE_AND_BLOCK_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_PEC_CORE_AND_BLOCK_INTR_STATUS) | |
| 596 | \#define PCIERPT_ILU_ERR_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_ILU_ERR_LOG_ENABLE) | |
| 597 | \#define PCIERPT_ILU_INTR_ENABLE (PCI_ERPT_U + PCIE_ERR_ILU_INTR_ENABLE) | |
| 598 | \#define PCIERPT_ILU_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_ILU_INTR_STATUS) | |
| 599 | \#define PCIERPT_ILU_ERR_STATUS_SET (PCI_ERPT_U + PCIE_ERR_ILU_ERR_STATUS_SET) | |
| 600 | \#define PCIERPT_TLU_UE_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_UE_LOG_ENABLE) | |
| 601 | \#define PCIERPT_TLU_UE_INTR_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_UE_INTR_ENABLE) | |
| 602 | \#define PCIERPT_TLU_UE_STATUS (PCI_ERPT_U + PCIE_ERR_TLU_UE_STATUS) | |
| 603 | \#define PCIERPT_TLU_UE_STATUS_SET (PCI_ERPT_U + PCIE_ERR_TLU_UE_STATUS_SET) | |
| 604 | \#define PCIERPT_TLU_CE_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_CE_LOG_ENABLE) | |
| 605 | \#define PCIERPT_TLU_CE_INTERRUPT_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_CE_INTERRUPT_ENABLE) | |
| 606 | \#define PCIERPT_TLU_CE_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_TLU_CE_INTR_STATUS) | |
| 607 | \#define PCIERPT_TLU_CE_STATUS (PCI_ERPT_U + PCIE_ERR_TLU_CE_STATUS) | |
| 608 | \#define PCIERPT_TLU_RCV_UE_ERR_HDR1_LOG (PCI_ERPT_U + PCIE_ERR_TLU_RCV_UE_ERR_HDR1_LOG) | |
| 609 | \#define PCIERPT_TLU_RCV_UE_ERR_HDR2_LOG (PCI_ERPT_U + PCIE_ERR_TLU_RCV_UE_ERR_HDR2_LOG) | |
| 610 | \#define PCIERPT_TLU_TRANS_UE_ERR_HDR1_LOG (PCI_ERPT_U + PCIE_ERR_TLU_TRANS_UE_ERR_HDR1_LOG) | |
| 611 | \#define PCIERPT_TLU_TRANS_UE_ERR_HDR2_LOG (PCI_ERPT_U + PCIE_ERR_TLU_TRANS_UE_ERR_HDR2_LOG) | |
| 612 | \#define PCIERPT_LPU_PHY_LAYER_INTR_AND_STATUS (PCI_ERPT_U + PCIE_ERR_LPU_PHY_LAYER_INTR_AND_STATUS) | |
| 613 | \#define PCIERPT_TLU_OTHER_EVENT_LOG_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_OTHER_EVENT_LOG_ENABLE) | |
| 614 | \#define PCIERPT_TLU_OTHER_EVENT_INTR_ENABLE (PCI_ERPT_U + PCIE_ERR_TLU_OTHER_EVENT_INTR_ENABLE) | |
| 615 | \#define PCIERPT_TLU_OTHER_EVENT_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_TLU_OTHER_EVENT_INTR_STATUS) | |
| 616 | \#define PCIERPT_TLU_OTHER_EVENT_STATUS_SET (PCI_ERPT_U + PCIE_ERR_TLU_OTHER_EVENT_STATUS_SET) | |
| 617 | \#define PCIERPT_TLU_RCV_OTHER_EVENT_HDR1_LOG (PCI_ERPT_U + PCIE_ERR_TLU_RCV_OTHER_EVENT_HDR1_LOG) | |
| 618 | \#define PCIERPT_TLU_RCV_OTHER_EVENT_HDR2_LOG (PCI_ERPT_U + PCIE_ERR_TLU_RCV_OTHER_EVENT_HDR2_LOG) | |
| 619 | \#define PCIERPT_TLU_TRANS_OTHER_EVENT_HDR1_LOG (PCI_ERPT_U + PCIE_ERR_TLU_TRANS_OTHER_EVENT_HDR1_LOG) | |
| 620 | \#define PCIERPT_TLU_TRANS_OTHER_EVENT_HDR2_LOG (PCI_ERPT_U + PCIE_ERR_TLU_TRANS_OTHER_EVENT_HDR2_LOG) | |
| 621 | \#define PCIERPT_LPU_LINK_LAYER_INTR_AND_STATUS (PCI_ERPT_U + PCIE_ERR_LPU_LINK_LAYER_INTR_AND_STATUS) | |
| 622 | \#define PCIERPT_LPU_INTR_STATUS (PCI_ERPT_U + PCIE_ERR_LPU_INTR_STATUS) | |
| 623 | \#define PCIERPT_LPU_LINK_PERF_COUNTER2 (PCI_ERPT_U + PCIE_ERR_LPU_LINK_PERF_COUNTER2) | |
| 624 | \#define PCIERPT_LPU_LINK_PERF_COUNTER1 (PCI_ERPT_U + PCIE_ERR_LPU_LINK_PERF_COUNTER1) | |
| 625 | \#define PCIERPT_LPU_LINK_LAYER_INTERRUPT_AND_STATUS (PCI_ERPT_U + PCIE_ERR_LPU_LINK_LAYER_INTERRUPT_AND_STATUS) | |
| 626 | \#define PCIERPT_LPU_PHY_ERR_INT (PCI_ERPT_U + PCIE_ERR_LPU_PHY_ERR_INT) | |
| 627 | \#define PCIERPT_LPU_LTSSM_STATUS (PCI_ERPT_U + PCIE_ERR_LPU_LTSSM_STATUS) | |
| 628 | \#define PCIERPT_LPU_TX_PHY_INT (PCI_ERPT_U + PCIE_ERR_LPU_TX_PHY_INT) | |
| 629 | \#define PCIERPT_LPU_RX_PHY_INT (PCI_ERPT_U + PCIE_ERR_LPU_RX_PHY_INT) | |
| 630 | \#define PCIERPT_LPU_GB_PHY_INT (PCI_ERPT_U + PCIE_ERR_LPU_GB_PHY_INT) | |
| 631 | \#define PCIERPT_DIAGBUF (PCI_ERPT_U + PCIE_ERR_DIAGBUF) | |
| 632 | ||
| 633 | ldc_conspkt LDC_CONSPKT_SIZE | |
| 634 | type LDC_CONS_TYPE | |
| 635 | size LDC_CONS_SIZE | |
| 636 | ctrl_msg LDC_CONS_CTRL_MSG | |
| 637 | payload LDC_CONS_PAYLOAD | |
| 638 | ||
| 639 | console CONSOLE_SIZE | |
| 640 | type CONS_TYPE | |
| 641 | uartbase CONS_UARTBASE | |
| 642 | status CONS_STATUS | |
| 643 | endpt CONS_ENDPT | |
| 644 | in_head CONS_INHEAD | |
| 645 | in_tail CONS_INTAIL | |
| 646 | vintr_mapreg CONS_VINTR_MAPREG | |
| 647 | in_buf CONS_INBUF | |
| 648 | ||
| 649 | hvdisk HVDISK_SIZE | |
| 650 | pa DISK_PA | |
| 651 | size DISK_SIZE | |
| 652 | ||
| 653 | snet_info SNET_INFO_SIZE | |
| 654 | pa SNET_PA | |
| 655 | ino SNET_INO | |
| 656 | ||
| 657 | ldc_endpoint LDC_ENDPOINT_SIZE | |
| 658 | is_live LDC_IS_LIVE | |
| 659 | is_private LDC_IS_PRIVATE | |
| 660 | svc_id LDC_IS_SVC_ID | |
| 661 | rx_updated LDC_RX_UPDATED | |
| 662 | txq_full LDC_TXQ_FULL | |
| 663 | tx_qbase_ra LDC_TX_QBASE_RA | |
| 664 | tx_qbase_pa LDC_TX_QBASE_PA | |
| 665 | tx_qsize LDC_TX_QSIZE | |
| 666 | tx_qhead LDC_TX_QHEAD | |
| 667 | tx_qtail LDC_TX_QTAIL | |
| 668 | tx_mapreg LDC_TX_MAPREG | |
| 669 | tx_cb LDC_TX_CB | |
| 670 | tx_cbarg LDC_TX_CBARG | |
| 671 | rx_qbase_ra LDC_RX_QBASE_RA | |
| 672 | rx_qbase_pa LDC_RX_QBASE_PA | |
| 673 | rx_qsize LDC_RX_QSIZE | |
| 674 | rx_qhead LDC_RX_QHEAD | |
| 675 | rx_qtail LDC_RX_QTAIL | |
| 676 | rx_mapreg LDC_RX_MAPREG | |
| 677 | rx_vintr_cookie LDC_RX_VINTR_COOKIE | |
| 678 | rx_cb LDC_RX_CB | |
| 679 | rx_cbarg LDC_RX_CBARG | |
| 680 | target_type LDC_TARGET_TYPE | |
| 681 | target_guest LDC_TARGET_GUEST | |
| 682 | target_channel LDC_TARGET_CHANNEL | |
| 683 | map_table_ra LDC_MAP_TABLE_RA | |
| 684 | map_table_pa LDC_MAP_TABLE_PA | |
| 685 | map_table_nentries LDC_MAP_TABLE_NENTRIES | |
| 686 | map_table_sz LDC_MAP_TABLE_SZ | |
| 687 | ||
| 688 | version VERSION_SIZE | |
| 689 | version_num VERSION_NUM | |
| 690 | verptr VERSION_PTR | |
| 691 | ||
| 692 | \#define VERSION_MAJOR (VERSION_NUM+MAJOR_OFF) | |
| 693 | \#define VERSION_MINOR (VERSION_NUM+MINOR_OFF) | |
| 694 | ||
| 695 | ldc_mapreg LDC_MAPREG_SIZE | |
| 696 | state LDC_MAPREG_STATE | |
| 697 | valid LDC_MAPREG_VALID | |
| 698 | ino LDC_MAPREG_INO | |
| 699 | pcpup LDC_MAPREG_CPUP | |
| 700 | cookie LDC_MAPREG_COOKIE | |
| 701 | endpoint LDC_MAPREG_ENDPOINT | |
| 702 | ||
| 703 | guest_watchdog | |
| 704 | ticks WATCHDOG_TICKS | |
| 705 | ||
| 706 | ldc_ino2endpoint LDC_I2E_SIZE | |
| 707 | endpointp LDC_I2E_ENDPOINT | |
| 708 | mapregp LDC_I2E_MAPREG | |
| 709 | ||
| 710 | sp_ldc_endpoint SP_LDC_ENDPOINT_SIZE | |
| 711 | is_live SP_LDC_IS_LIVE | |
| 712 | target_type SP_LDC_TARGET_TYPE | |
| 713 | tx_qd_pa SP_LDC_TX_QD_PA | |
| 714 | rx_qd_pa SP_LDC_RX_QD_PA | |
| 715 | target_guest SP_LDC_TARGET_GUEST | |
| 716 | target_channel SP_LDC_TARGET_CHANNEL | |
| 717 | tx_lock SP_LDC_TX_LOCK | |
| 718 | rx_lock SP_LDC_RX_LOCK | |
| 719 | tx_scr_txhead SP_LDC_TX_SCR_TXHEAD | |
| 720 | tx_scr_txtail SP_LDC_TX_SCR_TXTAIL | |
| 721 | tx_scr_txsize SP_LDC_TX_SCR_TXSIZE | |
| 722 | tx_scr_tx_qpa SP_LDC_TX_SCR_TX_QPA | |
| 723 | tx_scr_rxhead SP_LDC_TX_SCR_RXHEAD | |
| 724 | tx_scr_rxtail SP_LDC_TX_SCR_RXTAIL | |
| 725 | tx_scr_rxsize SP_LDC_TX_SCR_RXSIZE | |
| 726 | tx_scr_rx_qpa SP_LDC_TX_SCR_RX_QPA | |
| 727 | tx_scr_target SP_LDC_TX_SCR_TARGET | |
| 728 | rx_scr_txhead SP_LDC_RX_SCR_TXHEAD | |
| 729 | rx_scr_txtail SP_LDC_RX_SCR_TXTAIL | |
| 730 | rx_scr_txsize SP_LDC_RX_SCR_TXSIZE | |
| 731 | rx_scr_tx_qpa SP_LDC_RX_SCR_TX_QPA | |
| 732 | rx_scr_rxhead SP_LDC_RX_SCR_RXHEAD | |
| 733 | rx_scr_rxtail SP_LDC_RX_SCR_RXTAIL | |
| 734 | rx_scr_rxsize SP_LDC_RX_SCR_RXSIZE | |
| 735 | rx_scr_rx_qpa SP_LDC_RX_SCR_RX_QPA | |
| 736 | rx_scr_target SP_LDC_RX_SCR_TARGET | |
| 737 | rx_scr_pkt SP_LDC_RX_SCR_PKT | |
| 738 | ||
| 739 | ||
| 740 | sram_ldc_qentry SRAM_LDC_QENTRY_SIZE | |
| 741 | pkt_data SRAM_LDC_PKT_DATA | |
| 742 | ||
| 743 | sram_ldc_qd SRAM_LDC_QD_SIZE | |
| 744 | ldc_queue SRAM_LDC_QUEUE | |
| 745 | head SRAM_LDC_HEAD | |
| 746 | tail SRAM_LDC_TAIL | |
| 747 | state SRAM_LDC_STATE | |
| 748 | state_updated SRAM_LDC_STATE_UPDATED | |
| 749 | state_notify SRAM_LDC_STATE_NOTIFY | |
| 750 | padding SRAM_LDC_PADDING | |
| 751 | ||
| 752 | ldc_mapin LDC_MAPIN_SIZE | |
| 753 | local_endpoint LDC_MI_LOCAL_ENDPOINT | |
| 754 | pg_size LDC_MI_PG_SIZE | |
| 755 | perms LDC_MI_PERMS | |
| 756 | map_table_idx LDC_MI_MAP_TABLE_IDX | |
| 757 | pa LDC_MI_PA | |
| 758 | va LDC_MI_VA | |
| 759 | va_ctx LDC_MI_VA_CTX | |
| 760 | io_va LDC_MI_IO_VA | |
| 761 | mmu_map LDC_MI_MMU_MAP | |
| 762 | ||
| 763 | guest_console_queues GUEST_CONS_QUEUES_SIZE | |
| 764 | cons_rxq GUEST_CONS_RXQ | |
| 765 | cons_txq GUEST_CONS_TXQ | |
| 766 | ||
| 767 | ||
| 768 | \#define LDC_MI_NEXT_IDX 0 /* clobber 1st word when free */ | |
| 769 | \#define MIE_VA_MMU_SHIFT 0 | |
| 770 | \#define MIE_RA_MMU_SHIFT 8 | |
| 771 | \#define MIE_IO_MMU_SHIFT 16 | |
| 772 | \ offsets for a big-endian architecture | |
| 773 | \#define LDC_MI_VA_MMU_MAP (LDC_MI_MMU_MAP + 7) | |
| 774 | \#define LDC_MI_RA_MMU_MAP (LDC_MI_MMU_MAP + 6) | |
| 775 | \#define LDC_MI_IO_MMU_MAP (LDC_MI_MMU_MAP + 5) | |
| 776 | ||
| 777 | ra2pa_segment RA2PA_SEGMENT_SIZE | |
| 778 | base RA2PA_SEGMENT_BASE | |
| 779 | limit RA2PA_SEGMENT_LIMIT | |
| 780 | offset RA2PA_SEGMENT_OFFSET | |
| 781 | flags RA2PA_SEGMENT_FLAGS | |
| 782 | ||
| 783 | guest GUEST_SIZE | |
| 784 | guestid GUEST_GID | |
| 785 | ra2pa_segment GUEST_RA2PA_SEGMENT | |
| 786 | configp GUEST_CONFIGP | |
| 787 | state GUEST_STATE | |
| 788 | state_lock GUEST_STATE_LOCK | |
| 789 | soft_state GUEST_SOFT_STATE | |
| 790 | soft_state_str GUEST_SOFT_STATE_STR | |
| 791 | soft_state_lock GUEST_SOFT_STATE_LOCK | |
| 792 | real_base GUEST_REAL_BASE | |
| 793 | console GUEST_CONSOLE | |
| 794 | tod_offset GUEST_TOD_OFFSET | |
| 795 | ttrace_freeze GUEST_TTRACE_FRZ | |
| 796 | cpup GUEST_CPUP | |
| 797 | vcpus GUEST_VCPUS | |
| 798 | cpuset GUEST_CPUSET | |
| 799 | perm_mappings_lock GUEST_PERM_MAPPINGS_LOCK | |
| 800 | perm_mappings_count GUEST_PERM_MAPPINGS_COUNT | |
| 801 | perm_mappings GUEST_PERM_MAPPINGS GUEST_PERM_MAPPINGS_INCR | |
| 802 | api_groups GUEST_API_GROUPS | |
| 803 | hcall_table GUEST_HCALL_TABLE | |
| 804 | dev2inst GUEST_DEV2INST | |
| 805 | vino2inst GUEST_VINO2INST | |
| 806 | vdev_state GUEST_VDEV_STATE | |
| 807 | md_pa GUEST_MD_PA | |
| 808 | md_size GUEST_MD_SIZE | |
| 809 | maus GUEST_MAUS GUEST_MAUS_INCR | |
| 810 | dumpbuf_pa GUEST_DUMPBUF_PA | |
| 811 | dumpbuf_ra GUEST_DUMPBUF_RA | |
| 812 | dumpbuf_size GUEST_DUMPBUF_SIZE | |
| 813 | entry GUEST_ENTRY | |
| 814 | rom_base GUEST_ROM_BASE | |
| 815 | rom_size GUEST_ROM_SIZE | |
| 816 | perfreg_accessible GUEST_PERFREG_ACCESSIBLE | |
| 817 | diagpriv GUEST_DIAGPRIV | |
| 818 | reset_reason GUEST_RESET_REASON | |
| 819 | disk GUEST_DISK | |
| 820 | snet GUEST_SNET | |
| 821 | watchdog GUEST_WATCHDOG | |
| 822 | ldc_mapin_free_idx GUEST_LDC_MAPIN_FREE_IDX | |
| 823 | ldc_mapin_basera GUEST_LDC_MAPIN_BASERA | |
| 824 | ldc_max_channel_idx GUEST_LDC_MAX_CHANNEL_IDX | |
| 825 | ldc_mapin_size GUEST_LDC_MAPIN_SIZE | |
| 826 | ldc_endpoint GUEST_LDC_ENDPOINT | |
| 827 | ldc_mapin GUEST_LDC_MAPIN | |
| 828 | ldc_ino2endpoint GUEST_LDC_I2E | |
| 829 | start_stick GUEST_START_STICK | |
| 830 | util GUEST_UTIL | |
| 831 | async_busy GUEST_ASYNC_BUSY | |
| 832 | async_lock GUEST_ASYNC_LOCK | |
| 833 | async_buf GUEST_ASYNC_BUF | |
| 834 | ||
| 835 | guest_util GUEST_UTIL_SIZE | |
| 836 | stick_last GUTIL_STICK_LAST | |
| 837 | stopped_cycles GUTIL_STOPPED_CYCLES | |
| 838 | ||
| 839 | hvctl_res_status HVCTL_RES_STATUS_SIZE | |
| 840 | res HVCTL_RES_STATUS_RES | |
| 841 | resid HVCTL_RES_STATUS_RESID | |
| 842 | infoid HVCTL_RES_STATUS_INFOID | |
| 843 | code HVCTL_RES_STATUS_CODE | |
| 844 | data HVCTL_RES_STATUS_DATA | |
| 845 | ||
| 846 | rs_guest_soft_state RS_GUEST_SOFT_STATE_SIZE | |
| 847 | soft_state RS_GUEST_SOFT_STATE | |
| 848 | soft_state_str RS_GUEST_SOFT_STATE_STR | |
| 849 | ||
| 850 | devopsvec DEVOPSVEC_SIZE | |
| 851 | devino2vino DEVOPSVEC_DEVINO2VINO | |
| 852 | mondo_receive DEVOPSVEC_MONDO_RECEIVE | |
| 853 | getvalid DEVOPSVEC_GETVALID | |
| 854 | setvalid DEVOPSVEC_SETVALID | |
| 855 | settarget DEVOPSVEC_SETTARGET | |
| 856 | gettarget DEVOPSVEC_GETTARGET | |
| 857 | getstate DEVOPSVEC_GETSTATE | |
| 858 | setstate DEVOPSVEC_SETSTATE | |
| 859 | map DEVOPSVEC_MAP | |
| 860 | map_v2 DEVOPSVEC_MAP_V2 | |
| 861 | getmap DEVOPSVEC_GETMAP | |
| 862 | getmap_v2 DEVOPSVEC_GETMAP_V2 | |
| 863 | unmap DEVOPSVEC_UNMAP | |
| 864 | getbypass DEVOPSVEC_GETBYPASS | |
| 865 | configget DEVOPSVEC_CONFIGGET | |
| 866 | configput DEVOPSVEC_CONFIGPUT | |
| 867 | peek DEVOPSVEC_IOPEEK | |
| 868 | poke DEVOPSVEC_IOPOKE | |
| 869 | dmasync DEVOPSVEC_DMASYNC | |
| 870 | msiq_conf DEVOPSVEC_MSIQ_CONF | |
| 871 | msiq_info DEVOPSVEC_MSIQ_INFO | |
| 872 | msiq_getvalid DEVOPSVEC_MSIQ_GETVALID | |
| 873 | msiq_setvalid DEVOPSVEC_MSIQ_SETVALID | |
| 874 | msiq_getstate DEVOPSVEC_MSIQ_GETSTATE | |
| 875 | msiq_setstate DEVOPSVEC_MSIQ_SETSTATE | |
| 876 | msiq_gethead DEVOPSVEC_MSIQ_GETHEAD | |
| 877 | msiq_sethead DEVOPSVEC_MSIQ_SETHEAD | |
| 878 | msiq_gettail DEVOPSVEC_MSIQ_GETTAIL | |
| 879 | msi_getvalid DEVOPSVEC_MSI_GETVALID | |
| 880 | msi_setvalid DEVOPSVEC_MSI_SETVALID | |
| 881 | msi_getstate DEVOPSVEC_MSI_GETSTATE | |
| 882 | msi_setstate DEVOPSVEC_MSI_SETSTATE | |
| 883 | msi_getmsiq DEVOPSVEC_MSI_GETMSIQ | |
| 884 | msi_setmsiq DEVOPSVEC_MSI_SETMSIQ | |
| 885 | msi_msg_getmsiq DEVOPSVEC_MSI_MSG_GETMSIQ | |
| 886 | msi_msg_setmsiq DEVOPSVEC_MSI_MSG_SETMSIQ | |
| 887 | msi_msg_getvalid DEVOPSVEC_MSI_MSG_GETVALID | |
| 888 | msi_msg_setvalid DEVOPSVEC_MSI_MSG_SETVALID | |
| 889 | getperfreg DEVOPSVEC_GETPERFREG | |
| 890 | setperfreg DEVOPSVEC_SETPERFREG | |
| 891 | vgetcookie DEVOPSVEC_VGETCOOKIE | |
| 892 | vsetcookie DEVOPSVEC_VSETCOOKIE | |
| 893 | vgetvalid DEVOPSVEC_VGETVALID | |
| 894 | vsetvalid DEVOPSVEC_VSETVALID | |
| 895 | vgettarget DEVOPSVEC_VGETTARGET | |
| 896 | vsettarget DEVOPSVEC_VSETTARGET | |
| 897 | vgetstate DEVOPSVEC_VGETSTATE | |
| 898 | vsetstate DEVOPSVEC_VSETSTATE | |
| 899 | ||
| 900 | vino2inst VINO2INST_SIZE | |
| 901 | vino VINO2INST_VINO | |
| 902 | ||
| 903 | fire_cookie FIRE_COOKIE_SIZE | |
| 904 | handle FIRE_COOKIE_HANDLE | |
| 905 | jbus FIRE_COOKIE_JBUS | |
| 906 | pcie FIRE_COOKIE_PCIE | |
| 907 | cfg FIRE_COOKIE_CFG | |
| 908 | perfregs FIRE_COOKIE_PERFREGS | |
| 909 | mmu FIRE_COOKIE_MMU | |
| 910 | iotsb FIRE_COOKIE_IOTSB | |
| 911 | intclr FIRE_COOKIE_INTCLR | |
| 912 | intmap FIRE_COOKIE_INTMAP | |
| 913 | intmap_other FIRE_COOKIE_INTMAP_OTHER | |
| 914 | virtual_intmap FIRE_COOKIE_VIRTUAL_INTMAP | |
| 915 | err_lock FIRE_COOKIE_ERR_LOCK | |
| 916 | err_lock_counter FIRE_COOKIE_ERR_LOCK_COUNTER | |
| 917 | tlu_oe_status FIRE_COOKIE_OE_STATUS | |
| 918 | jbi_sig_enable FIRE_COOKIE_JBI_SIG_ENABLE | |
| 919 | inomax FIRE_COOKIE_INOMAX | |
| 920 | vino FIRE_COOKIE_VINO | |
| 921 | eqctlset FIRE_COOKIE_EQCTLSET | |
| 922 | eqctlclr FIRE_COOKIE_EQCTLCLR | |
| 923 | eqstate FIRE_COOKIE_EQSTATE | |
| 924 | eqtail FIRE_COOKIE_EQTAIL | |
| 925 | eqhead FIRE_COOKIE_EQHEAD | |
| 926 | msimap FIRE_COOKIE_MSIMAP | |
| 927 | msiclr FIRE_COOKIE_MSICLR | |
| 928 | msgmap FIRE_COOKIE_MSGMAP | |
| 929 | msieqbase FIRE_COOKIE_MSIEQBASE | |
| 930 | msieqs FIRE_COOKIE_MSIEQS | |
| 931 | msicookie FIRE_COOKIE_MSICOOKIE | |
| 932 | errcookie FIRE_COOKIE_ERRCOOKIE | |
| 933 | jbc_erpt FIRE_COOKIE_JBC_ERPT | |
| 934 | pcie_erpt FIRE_COOKIE_PCIE_ERPT | |
| 935 | extracfgrdaddrpa FIRE_COOKIE_EXTRACFGRDADDRPA | |
| 936 | blacklist FIRE_COOKIE_BLACKLIST | |
| 937 | ||
| 938 | fire_msieq FIRE_MSIEQ_SIZE | |
| 939 | eqmask FIRE_MSIEQ_EQMASK | |
| 940 | base FIRE_MSIEQ_BASE | |
| 941 | guest FIRE_MSIEQ_GUEST | |
| 942 | word0 FIRE_MSIEQ_WORD0 | |
| 943 | word1 FIRE_MSIEQ_WORD1 | |
| 944 | ||
| 945 | fire_msi_cookie FIRE_MSI_COOKIE_SIZE | |
| 946 | fire FIRE_MSI_COOKIE_FIRE | |
| 947 | eq FIRE_MSI_COOKIE_EQ | |
| 948 | ||
| 949 | fire_err_cookie FIRE_ERR_COOKIE_SIZE | |
| 950 | fire FIRE_ERR_COOKIE_FIRE | |
| 951 | state FIRE_ERR_COOKIE_STATE | |
| 952 | ||
| 953 | \#define FIRE_A_BASE0 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_BASE0) | |
| 954 | \#define FIRE_A_SIZE0 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_SIZE0) | |
| 955 | \#define FIRE_A_OFFSET0 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_OFFSET0) | |
| 956 | \#define FIRE_B_BASE0 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_BASE0) | |
| 957 | \#define FIRE_B_SIZE0 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_SIZE0) | |
| 958 | \#define FIRE_B_OFFSET0 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_OFFSET0) | |
| 959 | \#define FIRE_A_BASE1 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_BASE1) | |
| 960 | \#define FIRE_A_SIZE1 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_SIZE1) | |
| 961 | \#define FIRE_A_OFFSET1 (GUEST_FIRE+(0*FIRE_SIZE)+FIRE_OFFSET1) | |
| 962 | \#define FIRE_B_BASE1 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_BASE1) | |
| 963 | \#define FIRE_B_SIZE1 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_SIZE1) | |
| 964 | \#define FIRE_B_OFFSET1 (GUEST_FIRE+(1*FIRE_SIZE)+FIRE_OFFSET1) | |
| 965 | ||
| 966 | vdev_state VDEV_STATE_SIZE | |
| 967 | handle VDEV_STATE_HANDLE | |
| 968 | mapreg VDEV_STATE_MAPREG | |
| 969 | inomax VDEV_STATE_INOMAX | |
| 970 | vinobase VDEV_STATE_VINOBASE | |
| 971 | ||
| 972 | svc_link | |
| 973 | size SVC_LINK_SIZE | |
| 974 | pa SVC_LINK_PA | |
| 975 | next SVC_LINK_NEXT | |
| 976 | ||
| 977 | svc_callback | |
| 978 | rx SVC_CALLBACK_RX | |
| 979 | tx SVC_CALLBACK_TX | |
| 980 | cookie SVC_CALLBACK_COOKIE | |
| 981 | ||
| 982 | svc_ctrl SVC_CTRL_SIZE | |
| 983 | xid SVC_CTRL_XID | |
| 984 | sid SVC_CTRL_SID | |
| 985 | ino SVC_CTRL_INO | |
| 986 | mtu SVC_CTRL_MTU | |
| 987 | config SVC_CTRL_CONFIG | |
| 988 | state SVC_CTRL_STATE | |
| 989 | intr_cookie SVC_CTRL_INTR_COOKIE | |
| 990 | lock SVC_CTRL_LOCK | |
| 991 | dcount SVC_CTRL_COUNT | |
| 992 | dstate SVC_CTRL_DSTATE | |
| 993 | callback SVC_CTRL_CALLBACK | |
| 994 | link SVC_CTRL_LINK | |
| 995 | recv SVC_CTRL_RECV | |
| 996 | send SVC_CTRL_SEND | |
| 997 | ||
| 998 | hv_svc_data HV_SVC_DATA_SIZE | |
| 999 | rxbase HV_SVC_DATA_RXBASE | |
| 1000 | txbase HV_SVC_DATA_TXBASE | |
| 1001 | rxchannel HV_SVC_DATA_RXCHANNEL | |
| 1002 | txchannel HV_SVC_DATA_TXCHANNEL | |
| 1003 | scr HV_SVC_DATA_SCR | |
| 1004 | num_svcs HV_SVC_DATA_NUM_SVCS | |
| 1005 | sendbusy HV_SVC_DATA_SENDBUSY | |
| 1006 | sendh HV_SVC_DATA_SENDH | |
| 1007 | sendt HV_SVC_DATA_SENDT | |
| 1008 | senddh HV_SVC_DATA_SENDDH | |
| 1009 | senddt HV_SVC_DATA_SENDDT | |
| 1010 | lock HV_SVC_DATA_LOCK | |
| 1011 | svcs HV_SVC_DATA_SVC | |
| 1012 | ||
| 1013 | svc_pkt SVC_PKT_SIZE | |
| 1014 | xid SVC_PKT_XID | |
| 1015 | sid SVC_PKT_SID | |
| 1016 | sum SVC_PKT_SUM | |
| 1017 | ||
| 1018 | vdev_mapreg MAPREG_SIZE MAPREG_SHIFT | |
| 1019 | state MAPREG_STATE | |
| 1020 | valid MAPREG_VALID | |
| 1021 | pcpu MAPREG_PCPU | |
| 1022 | vcpu MAPREG_VCPU | |
| 1023 | ino MAPREG_INO | |
| 1024 | data0 MAPREG_DATA0 | |
| 1025 | devcookie MAPREG_DEVCOOKIE | |
| 1026 | getstate MAPREG_GETSTATE | |
| 1027 | setstate MAPREG_SETSTATE | |
| 1028 | ||
| 1029 | md_header DTHDR_SIZE | |
| 1030 | transport_version DTHDR_VER | |
| 1031 | node_blk_sz DTHDR_NODESZ | |
| 1032 | name_blk_sz DTHDR_NAMES | |
| 1033 | data_blk_sz DTHDR_DATA | |
| 1034 | ||
| 1035 | md_element DTNODE_SIZE | |
| 1036 | tag DTNODE_TAG | |
| 1037 | d DTNODE_DATA | |
| 1038 | ||
| 1039 | trapglobals TRAPGLOBALS_SIZE TRAPGLOBALS_SHIFT | |
| 1040 | ||
| 1041 | trapstate TRAPSTATE_SIZE | |
| 1042 | htstate TRAPSTATE_HTSTATE | |
| 1043 | tstate TRAPSTATE_TSTATE | |
| 1044 | tt TRAPSTATE_TT | |
| 1045 | tpc TRAPSTATE_TPC | |
| 1046 | tnpc TRAPSTATE_TNPC | |
| 1047 | ||
| 1048 | dbgerror_payload DBGERROR_PAYLOAD_SIZE | |
| 1049 | data DBGERROR_DATA | |
| 1050 | ||
| 1051 | dbgerror DBGERROR_SIZE | |
| 1052 | error_svch DBGERROR_ERROR_SVCH | |
| 1053 | payload DBGERROR_PAYLOAD | |
| 1054 | ||
| 1055 | devinst DEVINST_SIZE DEVINST_SIZE_SHIFT | |
| 1056 | cookie DEVINST_COOKIE | |
| 1057 | ops DEVINST_OPS | |
| 1058 | ||
| 1059 | erpt_svc_pkt ERPT_SVC_PKT_SIZE | |
| 1060 | addr ERPT_PKT_ADDR | |
| 1061 | size ERPT_PKT_SIZE | |
| 1062 | ||
| 1063 | way WAY_SIZE | |
| 1064 | tag_ecc WAY_TAG_ECC | |
| 1065 | data_ecc WAY_DATA_ECC | |
| 1066 | ||
| 1067 | l2 L2_SIZE | |
| 1068 | vdbits L2_VDBITS | |
| 1069 | uabits L2_UABITS | |
| 1070 | ways L2_WAYS | |
| 1071 | dram_contents L2_DRAM_CONTENTS | |
| 1072 | ||
| 1073 | \#define DRAM_CONTENTS(n) (L2_DRAM_CONTENTS + (n * L2_DRAM_CONTENTS_INCR)) | |
| 1074 | ||
| 1075 | tlb TLB_SIZE | |
| 1076 | tag TLB_TAG | |
| 1077 | data TLB_DATA | |
| 1078 | ||
| 1079 | icache_way ICACHE_WAY_SIZE | |
| 1080 | tag ICACHE_TAG | |
| 1081 | diag_data ICACHE_DIAG_DATA | |
| 1082 | ||
| 1083 | icache ICACHE_SIZE | |
| 1084 | lsu_diag_reg ICACHE_LSU_DIAG_REG | |
| 1085 | icache_way ICACHE_WAY | |
| 1086 | ||
| 1087 | dcache_way DCACHE_WAY_SIZE | |
| 1088 | tag DCACHE_TAG | |
| 1089 | data DCACHE_DATA | |
| 1090 | ||
| 1091 | dcache DCACHE_SIZE | |
| 1092 | lsu_diag_reg DCACHE_LSU_DIAG_REG | |
| 1093 | dcache_way DCACHE_WAY | |
| 1094 | ||
| 1095 | dram DRAM_SIZE | |
| 1096 | l2 DRAM_L2_INFO | |
| 1097 | disposition DRAM_DISPOSITION | |
| 1098 | ||
| 1099 | js JS_SIZE | |
| 1100 | jbi_err_config JS_JBI_ERR_CONFIG | |
| 1101 | jbi_err_ovf JS_JBI_ERR_OVF | |
| 1102 | jbi_log_enb JS_JBI_LOG_ENB | |
| 1103 | jbi_sig_enb JS_JBI_SIG_ENB | |
| 1104 | jbi_log_addr JS_JBI_LOG_ADDR | |
| 1105 | jbi_log_data0 JS_JBI_LOG_DATA0 | |
| 1106 | jbi_log_data1 JS_JBI_LOG_DATA1 | |
| 1107 | jbi_log_ctrl JS_JBI_LOG_CTRL | |
| 1108 | jbi_log_par JS_JBI_LOG_PAR | |
| 1109 | jbi_log_nack JS_JBI_LOG_NACK | |
| 1110 | jbi_log_arb JS_JBI_LOG_ARB | |
| 1111 | jbi_l2_timeout JS_JBI_L2_TIMEOUT | |
| 1112 | jbi_arb_timeout JS_JBI_ARB_TIMEOUT | |
| 1113 | jbi_trans_timeout JS_JBI_TRANS_TIMEOUT | |
| 1114 | jbi_memsize JS_JBI_MEMSIZE | |
| 1115 | jbi_err_inject JS_JBI_ERR_INJECT | |
| 1116 | ssi_timeout JS_SSI_TIMEOUT | |
| 1117 | ssi_log JS_SSI_LOG | |
| 1118 | ||
| 1119 | diag_buf DIAG_BUF_SIZE | |
| 1120 | l2_info DIAG_BUF_L2_INFO | |
| 1121 | dtlb DIAG_BUF_DTLB | |
| 1122 | itlb DIAG_BUF_ITLB | |
| 1123 | icache DIAG_BUF_ICACHE | |
| 1124 | dcache DIAG_BUF_DCACHE | |
| 1125 | dram_info DIAG_BUF_DRAM_INFO | |
| 1126 | js_info DIAG_BUF_JS_INFO | |
| 1127 | reg_info DIAG_BUF_REG_INFO | |
| 1128 | ||
| 1129 | mau_queue MAU_QUEUE_SIZE | |
| 1130 | mq_lock MQ_LOCK | |
| 1131 | mq_state MQ_STATE | |
| 1132 | mq_busy MQ_BUSY | |
| 1133 | mq_base MQ_BASE | |
| 1134 | mq_base_ra MQ_BASE_RA | |
| 1135 | mq_end MQ_END | |
| 1136 | mq_head MQ_HEAD | |
| 1137 | mq_head_marker MQ_HEAD_MARKER | |
| 1138 | mq_tail MQ_TAIL | |
| 1139 | mq_nentries MQ_NENTRIES | |
| 1140 | mq_cpu_pid MQ_CPU_PID | |
| 1141 | ||
| 1142 | ncs_hvdesc NCS_HVDESC_SIZE NCS_HVDESC_SHIFT | |
| 1143 | nhd_state NHD_STATE | |
| 1144 | nhd_type NHD_TYPE | |
| 1145 | nhd_regs NHD_REGS | |
| 1146 | nhd_errstatus NHD_ERRSTATUS | |
| 1147 | ||
| 1148 | ma_regs MA_REGS_SIZE | |
| 1149 | mr_ctl MR_CTL | |
| 1150 | mr_mpa MR_MPA | |
| 1151 | mr_ma MR_MA | |
| 1152 | mr_np MR_NP | |
| 1153 | ||
| 1154 | ncs_qconf_arg NCS_QCONF_ARG_SIZE | |
| 1155 | nq_mid NQ_MID | |
| 1156 | nq_base NQ_BASE | |
| 1157 | nq_end NQ_END | |
| 1158 | nq_nentries NQ_NENTRIES | |
| 1159 | ||
| 1160 | ncs_qtail_update_arg NCS_QTAIL_UPDATE_ARG_SIZE | |
| 1161 | nu_mid NU_MID | |
| 1162 | nu_tail NU_TAIL | |
| 1163 | nu_syncflag NU_SYNCFLAG | |
| 1164 | ||
| 1165 | crypto_intr CRYPTO_INTR_SIZE | |
| 1166 | ci_cookie CI_COOKIE | |
| 1167 | ci_active CI_ACTIVE | |
| 1168 | ci_data CI_DATA | |
| 1169 | ||
| 1170 | svccn_packet SVCCN_PKT_SIZE | |
| 1171 | type SVCCN_PKT_TYPE | |
| 1172 | len SVCCN_PKT_LEN | |
| 1173 | data SVCCN_PKT_DATA | |
| 1174 | ||
| 1175 | vbsc_ctrl_pkt VBSC_CTRL_PKT_SIZE | |
| 1176 | cmd VBSC_PKT_CMD | |
| 1177 | arg0 VBSC_PKT_ARG0 | |
| 1178 | arg1 VBSC_PKT_ARG1 | |
| 1179 | arg2 VBSC_PKT_ARG2 | |
| 1180 | ||
| 1181 | callback CB_SIZE | |
| 1182 | tick CB_TICK | |
| 1183 | handler CB_HANDLER | |
| 1184 | arg0 CB_ARG0 | |
| 1185 | arg1 CB_ARG1 | |
| 1186 | ||
| 1187 | cyclic CY_SIZE | |
| 1188 | t0 CY_T0 | |
| 1189 | cb CY_CB | |
| 1190 | tick CY_TICK | |
| 1191 | handler CY_HANDLER | |
| 1192 | arg0 CY_ARG0 | |
| 1193 | arg1 CY_ARG1 | |
| 1194 | ||
| 1195 | \#define STRAND_CY_T0 (STRAND_CYCLIC + CY_T0) | |
| 1196 | \#define STRAND_CY_CB (STRAND_CYCLIC + CY_CB) | |
| 1197 | \#define STRAND_CY_TICK (STRAND_CYCLIC + CY_TICK) | |
| 1198 | \#define STRAND_CY_HANDLER (STRAND_CYCLIC + CY_HANDLER) | |
| 1199 | \#define STRAND_CY_ARG0 (STRAND_CYCLIC + CY_ARG0) | |
| 1200 | \#define STRAND_CY_ARG1 (STRAND_CYCLIC + CY_ARG1) | |
| 1201 | \#define STRAND_CY_CB_TICK (STRAND_CYCLIC + CY_CB + CB_TICK) | |
| 1202 | \#define STRAND_CY_CB_HANDLER (STRAND_CYCLIC + CY_CB + CB_HANDLER) | |
| 1203 | \#define STRAND_CY_CB_ARG0 (STRAND_CYCLIC + CY_CB + CB_ARG0) | |
| 1204 | \#define STRAND_CY_CB_ARG1 (STRAND_CYCLIC + CY_CB + CB_ARG1) | |
| 1205 | \#define CB_LAST ((N_CB - 1) * CB_SIZE) | |
| 1206 | \#define STRAND_CY_CB_LAST_TICK (STRAND_CY_CB_TICK + CB_LAST) | |
| 1207 | ||
| 1208 | \ Enumerations | |
| 1209 | ||
| 1210 | hvctl_res_t | |
| 1211 | ||
| 1212 | hvctl_guest_info_t |