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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / src / traptable.s
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: traptable.s
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49 .ident "@(#)traptable.s 1.43 07/09/14 SMI"
50
51/*
52 * Niagara hypervisor trap table
53 */
54
55#include <sys/htypes.h>
56#include <sys/asm_linkage.h>
57#include <sys/stack.h>
58#include <hypervisor.h>
59#include <hprivregs.h>
60#include <asi.h>
61#include <mmu.h>
62#include <sun4v/traps.h>
63#include <sun4v/mmu.h>
64
65#include <traps.h>
66#include <traptable.h>
67#include <offsets.h>
68#include <util.h>
69#include <guest.h>
70#include <traptrace.h>
71#include <debug.h>
72#include <abort.h>
73#include <util.h>
74
75/*
76 * The basic hypervisor trap table
77 *
78 * We use the linker to place this at the beginning of the hypervisor
79 * binary which gets loaded at an appropriate alignment by Reset/Config.
80 */
81
82 ENTRY(htraptable)
83 /*
84 * hardware traps
85 */
86 TRAP(tt0_000, NOT) /* reserved */
87 TRAP(tt0_001, POR) /* power-on reset */
88 TRAP(tt0_002, GOTO(watchdog)) /* watchdog reset */
89 TRAP(tt0_003, GOTO(xir)) /* externally initiated reset */
90 TRAP(tt0_004, NOT) /* software initiated reset */
91 TRAP(tt0_005, NOT) /* red mode exception */
92 TRAP(tt0_006, NOT) /* reserved */
93 TRAP(tt0_007, NOT) /* reserved */
94 TRAP(tt0_008, GOTO(immu_err)) /* instruction access exception */
95 TRAP(tt0_009, NOT) /* instruction access mmu miss */
96 TRAP(tt0_00a, UE_ERR) /* instruction access error */
97 TRAP(tt0_00b, NOT) /* reserved */
98 TRAP(tt0_00c, NOT) /* reserved */
99 TRAP(tt0_00d, NOT) /* reserved */
100 TRAP(tt0_00e, NOT) /* reserved */
101 TRAP(tt0_00f, NOT) /* reserved */
102 TRAP(tt0_010, REVECTOR(TT_ILLINST)) /* illegal instruction */
103 TRAP(tt0_011, REVECTOR(TT_PRIVOP)) /* privileged opcode */
104 TRAP(tt0_012, REVECTOR(TT_UNIMP_LDD)) /* unimplemented LDD */
105 TRAP(tt0_013, REVECTOR(TT_UNIMP_STD)) /* unimplemented STD */
106 TRAP(tt0_014, NOT) /* reserved */
107 TRAP(tt0_015, NOT) /* reserved */
108 TRAP(tt0_016, NOT) /* reserved */
109 TRAP(tt0_017, NOT) /* reserved */
110 TRAP(tt0_018, NOT) /* reserved */
111 TRAP(tt0_019, NOT) /* reserved */
112 TRAP(tt0_01a, NOT) /* reserved */
113 TRAP(tt0_01b, NOT) /* reserved */
114 TRAP(tt0_01c, NOT) /* reserved */
115 TRAP(tt0_01d, NOT) /* reserved */
116 TRAP(tt0_01e, NOT) /* reserved */
117 TRAP(tt0_01f, NOT) /* reserved */
118 TRAP(tt0_020, NOT) /* fp disabled */
119 TRAP(tt0_021, NOT) /* fp exception ieee 754 */
120 TRAP(tt0_022, NOT) /* fp exception other */
121 TRAP(tt0_023, NOT) /* tag overflow */
122 BIGTRAP(tt0_024, CLEAN_WINDOW) /* clean window */
123 TRAP(tt0_028, NOT) /* division by zero */
124 TRAP(tt0_029, UE_ERR) /* internal processor error */
125 TRAP(tt0_02a, NOT) /* reserved */
126 TRAP(tt0_02b, NOT) /* reserved */
127 TRAP(tt0_02c, NOT) /* reserved */
128 TRAP(tt0_02d, NOT) /* reserved */
129 TRAP(tt0_02e, NOT) /* reserved */
130 TRAP(tt0_02f, NOT) /* reserved */
131 TRAP(tt0_030, GOTO(dmmu_err)) /* data access exception */
132 TRAP(tt0_031, NOT) /* data access mmu miss */
133 TRAP(tt0_032, UE_ERR) /* data access error */
134 TRAP(tt0_033, UE_ERR) /* data access protection */
135 TRAP(tt0_034, GOTO(dmmu_err)) /* mem address not aligned */
136 TRAP(tt0_035, GOTO(dmmu_err)) /* lddf mem address not aligned */
137 TRAP(tt0_036, GOTO(dmmu_err)) /* stdf mem address not aligned */
138 TRAP(tt0_037, GOTO(dmmu_err)) /* privileged action */
139 TRAP(tt0_038, GOTO(dmmu_err)) /* ldqf mem address not aligned */
140 TRAP(tt0_039, GOTO(dmmu_err)) /* stqf mem address not aligned */
141 TRAP(tt0_03a, NOT) /* reserved */
142 TRAP(tt0_03b, NOT) /* reserved */
143 TRAP(tt0_03c, NOT) /* reserved */
144 TRAP(tt0_03d, NOT) /* reserved */
145 TRAP(tt0_03e, RIMMU_MISS) /* HV: real immu miss */
146 TRAP(tt0_03f, RDMMU_MISS) /* HV: real dmmu miss */
147 TRAP(tt0_040, NOT) /* async data error */
148 TRAP(tt0_041, NOT) /* interrupt level 1 */
149 TRAP(tt0_042, NOT) /* interrupt level 2 */
150 TRAP(tt0_043, NOT) /* interrupt level 3 */
151 TRAP(tt0_044, NOT) /* interrupt level 4 */
152 TRAP(tt0_045, NOT) /* interrupt level 5 */
153 TRAP(tt0_046, NOT) /* interrupt level 6 */
154 TRAP(tt0_047, NOT) /* interrupt level 7 */
155 TRAP(tt0_048, NOT) /* interrupt level 8 */
156 TRAP(tt0_049, NOT) /* interrupt level 9 */
157 TRAP(tt0_04a, NOT) /* interrupt level a */
158 TRAP(tt0_04b, NOT) /* interrupt level b */
159 TRAP(tt0_04c, NOT) /* interrupt level c */
160 TRAP(tt0_04d, NOT) /* interrupt level d */
161 TRAP(tt0_04e, NOT) /* interrupt level e */
162 TRAP(tt0_04f, NOT) /* interrupt level f */
163 TRAP(tt0_050, NOT) /* reserved */
164 TRAP(tt0_051, NOT) /* reserved */
165 TRAP(tt0_052, NOT) /* reserved */
166 TRAP(tt0_053, NOT) /* reserved */
167 TRAP(tt0_054, NOT) /* reserved */
168 TRAP(tt0_055, NOT) /* reserved */
169 TRAP(tt0_056, NOT) /* reserved */
170 TRAP(tt0_057, NOT) /* reserved */
171 TRAP(tt0_058, NOT) /* reserved */
172 TRAP(tt0_059, NOT) /* reserved */
173 TRAP(tt0_05a, NOT) /* reserved */
174 TRAP(tt0_05b, NOT) /* reserved */
175 TRAP(tt0_05c, NOT) /* reserved */
176 TRAP(tt0_05d, NOT) /* reserved */
177 TRAP(tt0_05e, HSTICK_INTR) /* HV: hstick match */
178 TRAP(tt0_05f, NOT) /* reserved */
179 TRAP(tt0_060, VECINTR) /* interrupt vector */
180 TRAP(tt0_061, NOT) /* RA watchpoint */
181 TRAP(tt0_062, NOT) /* VA watchpoint */
182 TRAP(tt0_063, CE_ERR) /* corrected ECC error XXX */
183 BIGTRAP(tt0_064, IMMU_MISS) /* fast instruction access MMU miss */
184 BIGTRAP(tt0_068, DMMU_MISS) /* fast data access MMU miss */
185 BIGTRAP(tt0_06C, DMMU_PROT) /* fast data access protection */
186 TRAP(tt0_070, NOT) /* reserved */
187 TRAP(tt0_071, NOT) /* reserved */
188 TRAP(tt0_072, NOT) /* reserved */
189 TRAP(tt0_073, NOT) /* reserved */
190 TRAP(tt0_074, MAUINTR) /* modular arithmetic unit */
191 TRAP(tt0_075, NOT) /* reserved */
192 TRAP(tt0_076, NOT) /* reserved */
193 TRAP(tt0_077, NOT) /* reserved */
194 TRAP(tt0_078, DIS_UE_ERR) /* data error (disrupting) */
195 TRAP(tt0_079, NOT) /* reserved */
196 TRAP(tt0_07a, NOT) /* reserved */
197 TRAP(tt0_07b, NOT) /* reserved */
198 TRAP(tt0_07c, NOT) /* HV: cpu mondo */
199 TRAP(tt0_07d, NOT) /* HV: dev mondo */
200 TRAP(tt0_07e, NOT) /* HV: resumable error */
201 TRAP(tt0_07f, NOT) /* HV: non-resumable error */
202 BIGTRAP(tt0_080, SPILL_WINDOW) /* spill 0 normal */
203 BIGTRAP(tt0_084, SPILL_WINDOW) /* spill 1 normal */
204 BIGTRAP(tt0_088, SPILL_WINDOW) /* spill 2 normal */
205 BIGTRAP(tt0_08c, SPILL_WINDOW) /* spill 3 normal */
206 BIGTRAP(tt0_090, SPILL_WINDOW) /* spill 4 normal */
207 BIGTRAP(tt0_094, SPILL_WINDOW) /* spill 5 normal */
208 BIGTRAP(tt0_098, SPILL_WINDOW) /* spill 6 normal */
209 BIGTRAP(tt0_09c, SPILL_WINDOW) /* spill 7 normal */
210 BIGTRAP(tt0_0a0, SPILL_WINDOW) /* spill 0 other */
211 BIGTRAP(tt0_0a4, SPILL_WINDOW) /* spill 1 other */
212 BIGTRAP(tt0_0a8, SPILL_WINDOW) /* spill 2 other */
213 BIGTRAP(tt0_0ac, SPILL_WINDOW) /* spill 3 other */
214 BIGTRAP(tt0_0b0, SPILL_WINDOW) /* spill 4 other */
215 BIGTRAP(tt0_0b4, SPILL_WINDOW) /* spill 5 other */
216 BIGTRAP(tt0_0b8, SPILL_WINDOW) /* spill 6 other */
217 BIGTRAP(tt0_0bc, SPILL_WINDOW) /* spill 7 other */
218 BIGTRAP(tt0_0c0, FILL_WINDOW) /* fill 0 normal */
219 BIGTRAP(tt0_0c4, FILL_WINDOW) /* fill 1 normal */
220 BIGTRAP(tt0_0c8, FILL_WINDOW) /* fill 2 normal */
221 BIGTRAP(tt0_0cc, FILL_WINDOW) /* fill 3 normal */
222 BIGTRAP(tt0_0d0, FILL_WINDOW) /* fill 4 normal */
223 BIGTRAP(tt0_0d4, FILL_WINDOW) /* fill 5 normal */
224 BIGTRAP(tt0_0d8, FILL_WINDOW) /* fill 6 normal */
225 BIGTRAP(tt0_0dc, FILL_WINDOW) /* fill 7 normal */
226 BIGTRAP(tt0_0e0, FILL_WINDOW) /* fill 0 other */
227 BIGTRAP(tt0_0e4, FILL_WINDOW) /* fill 1 other */
228 BIGTRAP(tt0_0e8, FILL_WINDOW) /* fill 2 other */
229 BIGTRAP(tt0_0ec, FILL_WINDOW) /* fill 3 other */
230 BIGTRAP(tt0_0f0, FILL_WINDOW) /* fill 4 other */
231 BIGTRAP(tt0_0f4, FILL_WINDOW) /* fill 5 other */
232 BIGTRAP(tt0_0f8, FILL_WINDOW) /* fill 6 other */
233 BIGTRAP(tt0_0fc, FILL_WINDOW) /* fill 7 other */
234 /*
235 * Software traps
236 */
237 TRAP(tt0_100, NOT) /* software trap */
238 TRAP(tt0_101, NOT) /* software trap */
239 TRAP(tt0_102, NOT) /* software trap */
240 TRAP(tt0_103, NOT) /* software trap */
241 TRAP(tt0_104, NOT) /* software trap */
242 TRAP(tt0_105, NOT) /* software trap */
243 TRAP(tt0_106, NOT) /* software trap */
244 TRAP(tt0_107, NOT) /* software trap */
245 TRAP(tt0_108, NOT) /* software trap */
246 TRAP(tt0_109, NOT) /* software trap */
247 TRAP(tt0_10a, NOT) /* software trap */
248 TRAP(tt0_10b, NOT) /* software trap */
249 TRAP(tt0_10c, NOT) /* software trap */
250 TRAP(tt0_10d, NOT) /* software trap */
251 TRAP(tt0_10e, NOT) /* software trap */
252 TRAP(tt0_10f, NOT) /* software trap */
253 TRAP(tt0_110, NOT) /* software trap */
254 TRAP(tt0_111, NOT) /* software trap */
255 TRAP(tt0_112, NOT) /* software trap */
256#ifdef DEBUG
257 TRAP(tt0_113, GOTO(hprint)) /* print string */
258 TRAP(tt0_114, GOTO(hprintx)) /* print hex 64-bit */
259#else
260 TRAP(tt0_113, NOT) /* software trap */
261 TRAP(tt0_114, NOT) /* software trap */
262#endif
263 TRAP(tt0_115, NOT) /* software trap */
264 TRAP(tt0_116, NOT) /* software trap */
265 TRAP(tt0_117, NOT) /* software trap */
266 TRAP(tt0_118, NOT) /* software trap */
267 TRAP(tt0_119, NOT) /* software trap */
268 TRAP(tt0_11a, NOT) /* software trap */
269 TRAP(tt0_11b, NOT) /* software trap */
270 TRAP(tt0_11c, NOT) /* software trap */
271 TRAP(tt0_11d, NOT) /* software trap */
272 TRAP(tt0_11e, NOT) /* software trap */
273 TRAP(tt0_11f, NOT) /* software trap */
274 TRAP(tt0_120, NOT) /* software trap */
275 TRAP(tt0_121, NOT) /* software trap */
276 TRAP(tt0_122, NOT) /* software trap */
277 TRAP(tt0_123, NOT) /* software trap */
278 TRAP(tt0_124, NOT) /* software trap */
279 TRAP(tt0_125, NOT) /* software trap */
280 TRAP(tt0_126, NOT) /* software trap */
281 TRAP(tt0_127, NOT) /* software trap */
282 TRAP(tt0_128, NOT) /* software trap */
283 TRAP(tt0_129, NOT) /* software trap */
284 TRAP(tt0_12a, NOT) /* software trap */
285 TRAP(tt0_12b, NOT) /* software trap */
286 TRAP(tt0_12c, NOT) /* software trap */
287 TRAP(tt0_12d, NOT) /* software trap */
288 TRAP(tt0_12e, NOT) /* software trap */
289 TRAP(tt0_12f, NOT) /* software trap */
290 TRAP(tt0_130, NOT) /* software trap */
291 TRAP(tt0_131, NOT) /* software trap */
292 TRAP(tt0_132, NOT) /* software trap */
293 TRAP(tt0_133, NOT) /* software trap */
294 TRAP(tt0_134, NOT) /* software trap */
295 TRAP(tt0_135, NOT) /* software trap */
296 TRAP(tt0_136, NOT) /* software trap */
297 TRAP(tt0_137, NOT) /* software trap */
298 TRAP(tt0_138, NOT) /* software trap */
299 TRAP(tt0_139, NOT) /* software trap */
300 TRAP(tt0_13a, NOT) /* software trap */
301 TRAP(tt0_13b, NOT) /* software trap */
302 TRAP(tt0_13c, NOT) /* software trap */
303 TRAP(tt0_13d, NOT) /* software trap */
304 TRAP(tt0_13e, NOT) /* software trap */
305 TRAP(tt0_13f, NOT) /* software trap */
306 TRAP(tt0_140, NOT) /* software trap */
307 TRAP(tt0_141, NOT) /* software trap */
308 TRAP(tt0_142, NOT) /* software trap */
309 TRAP(tt0_143, NOT) /* software trap */
310 TRAP(tt0_144, NOT) /* software trap */
311 TRAP(tt0_145, NOT) /* software trap */
312 TRAP(tt0_146, NOT) /* software trap */
313 TRAP(tt0_147, NOT) /* software trap */
314 TRAP(tt0_148, NOT) /* software trap */
315 TRAP(tt0_149, NOT) /* software trap */
316 TRAP(tt0_14a, NOT) /* software trap */
317 TRAP(tt0_14b, NOT) /* software trap */
318 TRAP(tt0_14c, NOT) /* software trap */
319 TRAP(tt0_14d, NOT) /* software trap */
320 TRAP(tt0_14e, NOT) /* software trap */
321 TRAP(tt0_14f, NOT) /* software trap */
322 TRAP(tt0_150, NOT) /* software trap */
323 TRAP(tt0_151, NOT) /* software trap */
324 TRAP(tt0_152, NOT) /* software trap */
325 TRAP(tt0_153, NOT) /* software trap */
326 TRAP(tt0_154, NOT) /* software trap */
327 TRAP(tt0_155, NOT) /* software trap */
328 TRAP(tt0_156, NOT) /* software trap */
329 TRAP(tt0_157, NOT) /* software trap */
330 TRAP(tt0_158, NOT) /* software trap */
331 TRAP(tt0_159, NOT) /* software trap */
332 TRAP(tt0_15a, NOT) /* software trap */
333 TRAP(tt0_15b, NOT) /* software trap */
334 TRAP(tt0_15c, NOT) /* software trap */
335 TRAP(tt0_15d, NOT) /* software trap */
336 TRAP(tt0_15e, NOT) /* software trap */
337 TRAP(tt0_15f, NOT) /* software trap */
338 TRAP(tt0_160, NOT) /* software trap */
339 TRAP(tt0_161, NOT) /* software trap */
340 TRAP(tt0_162, NOT) /* software trap */
341 TRAP(tt0_163, NOT) /* software trap */
342 TRAP(tt0_164, NOT) /* software trap */
343 TRAP(tt0_165, NOT) /* software trap */
344 TRAP(tt0_166, NOT) /* software trap */
345 TRAP(tt0_167, NOT) /* software trap */
346 TRAP(tt0_168, NOT) /* software trap */
347 TRAP(tt0_169, NOT) /* software trap */
348 TRAP(tt0_16a, NOT) /* software trap */
349 TRAP(tt0_16b, NOT) /* software trap */
350 TRAP(tt0_16c, NOT) /* software trap */
351 TRAP(tt0_16d, NOT) /* software trap */
352 TRAP(tt0_16e, NOT) /* software trap */
353 TRAP(tt0_16f, NOT) /* software trap */
354 TRAP(tt0_170, NOT) /* software trap */
355 TRAP(tt0_171, NOT) /* software trap */
356 TRAP(tt0_172, NOT) /* software trap */
357 TRAP(tt0_173, NOT) /* software trap */
358 TRAP(tt0_174, NOT) /* software trap */
359 TRAP(tt0_175, NOT) /* software trap */
360 TRAP(tt0_176, NOT) /* software trap */
361 TRAP(tt0_177, NOT) /* software trap */
362 TRAP(tt0_178, NOT) /* software trap */
363 TRAP(tt0_179, NOT) /* software trap */
364 TRAP(tt0_17a, NOT) /* software trap */
365 TRAP(tt0_17b, NOT) /* software trap */
366 TRAP(tt0_17c, NOT) /* software trap */
367 TRAP(tt0_17d, NOT) /* software trap */
368 TRAP(tt0_17e, NOT) /* software trap */
369 TRAP(tt0_17f, NOT) /* software trap */
370 TRAP(tt0_180, GOTO(hcall)) /* hypervisor software trap */
371 TRAP(tt0_181, HCALL_BAD) /* hypervisor software trap */
372 TRAP(tt0_182, HCALL_BAD) /* hypervisor software trap */
373 TRAP_NOALIGN(tt0_183, HCALL(MMU_MAP_ADDR_IDX)) /* hyperfast trap */
374 TRAP_NOALIGN(tt0_184, HCALL(MMU_UNMAP_ADDR_IDX)) /* hyperfast trap */
375 TRAP_NOALIGN(tt0_185, HCALL(TTRACE_ADDENTRY_IDX)) /* hyperfast trap */
376 TRAP(tt0_186, HCALL_BAD) /* hypervisor software trap */
377 TRAP(tt0_187, HCALL_BAD) /* hypervisor software trap */
378 TRAP(tt0_188, HCALL_BAD) /* hypervisor software trap */
379 TRAP(tt0_189, HCALL_BAD) /* hypervisor software trap */
380 TRAP(tt0_18a, HCALL_BAD) /* hypervisor software trap */
381 TRAP(tt0_18b, HCALL_BAD) /* hypervisor software trap */
382 TRAP(tt0_18c, HCALL_BAD) /* hypervisor software trap */
383 TRAP(tt0_18d, HCALL_BAD) /* hypervisor software trap */
384 TRAP(tt0_18e, HCALL_BAD) /* hypervisor software trap */
385 TRAP(tt0_18f, HCALL_BAD) /* hypervisor software trap */
386 TRAP(tt0_190, HCALL_BAD) /* hypervisor software trap */
387 TRAP(tt0_191, HCALL_BAD) /* hypervisor software trap */
388 TRAP(tt0_192, HCALL_BAD) /* hypervisor software trap */
389 TRAP(tt0_193, HCALL_BAD) /* hypervisor software trap */
390 TRAP(tt0_194, HCALL_BAD) /* hypervisor software trap */
391 TRAP(tt0_195, HCALL_BAD) /* hypervisor software trap */
392 TRAP(tt0_196, HCALL_BAD) /* hypervisor software trap */
393 TRAP(tt0_197, HCALL_BAD) /* hypervisor software trap */
394 TRAP(tt0_198, HCALL_BAD) /* hypervisor software trap */
395 TRAP(tt0_199, HCALL_BAD) /* hypervisor software trap */
396 TRAP(tt0_19a, HCALL_BAD) /* hypervisor software trap */
397 TRAP(tt0_19b, HCALL_BAD) /* hypervisor software trap */
398 TRAP(tt0_19c, HCALL_BAD) /* hypervisor software trap */
399 TRAP(tt0_19d, HCALL_BAD) /* hypervisor software trap */
400 TRAP(tt0_19e, HCALL_BAD) /* hypervisor software trap */
401 TRAP(tt0_19f, HCALL_BAD) /* hypervisor software trap */
402 TRAP(tt0_1a0, HCALL_BAD) /* hypervisor software trap */
403 TRAP(tt0_1a1, HCALL_BAD) /* hypervisor software trap */
404 TRAP(tt0_1a2, HCALL_BAD) /* hypervisor software trap */
405 TRAP(tt0_1a3, HCALL_BAD) /* hypervisor software trap */
406 TRAP(tt0_1a4, HCALL_BAD) /* hypervisor software trap */
407 TRAP(tt0_1a5, HCALL_BAD) /* hypervisor software trap */
408 TRAP(tt0_1a6, HCALL_BAD) /* hypervisor software trap */
409 TRAP(tt0_1a7, HCALL_BAD) /* hypervisor software trap */
410 TRAP(tt0_1a8, HCALL_BAD) /* hypervisor software trap */
411 TRAP(tt0_1a9, HCALL_BAD) /* hypervisor software trap */
412 TRAP(tt0_1aa, HCALL_BAD) /* hypervisor software trap */
413 TRAP(tt0_1ab, HCALL_BAD) /* hypervisor software trap */
414 TRAP(tt0_1ac, HCALL_BAD) /* hypervisor software trap */
415 TRAP(tt0_1ad, HCALL_BAD) /* hypervisor software trap */
416 TRAP(tt0_1ae, HCALL_BAD) /* hypervisor software trap */
417 TRAP(tt0_1af, HCALL_BAD) /* hypervisor software trap */
418 TRAP(tt0_1b0, HCALL_BAD) /* hypervisor software trap */
419 TRAP(tt0_1b1, HCALL_BAD) /* hypervisor software trap */
420 TRAP(tt0_1b2, HCALL_BAD) /* hypervisor software trap */
421 TRAP(tt0_1b3, HCALL_BAD) /* hypervisor software trap */
422 TRAP(tt0_1b4, HCALL_BAD) /* hypervisor software trap */
423 TRAP(tt0_1b5, HCALL_BAD) /* hypervisor software trap */
424 TRAP(tt0_1b6, HCALL_BAD) /* hypervisor software trap */
425 TRAP(tt0_1b7, HCALL_BAD) /* hypervisor software trap */
426 TRAP(tt0_1b8, HCALL_BAD) /* hypervisor software trap */
427 TRAP(tt0_1b9, HCALL_BAD) /* hypervisor software trap */
428 TRAP(tt0_1ba, HCALL_BAD) /* hypervisor software trap */
429 TRAP(tt0_1bb, HCALL_BAD) /* hypervisor software trap */
430 TRAP(tt0_1bc, HCALL_BAD) /* hypervisor software trap */
431 TRAP(tt0_1bd, HCALL_BAD) /* hypervisor software trap */
432 TRAP(tt0_1be, HCALL_BAD) /* hypervisor software trap */
433 TRAP(tt0_1bf, HCALL_BAD) /* hypervisor software trap */
434 TRAP(tt0_1c0, HCALL_BAD) /* hypervisor software trap */
435 TRAP(tt0_1c1, HCALL_BAD) /* hypervisor software trap */
436 TRAP(tt0_1c2, HCALL_BAD) /* hypervisor software trap */
437 TRAP(tt0_1c3, HCALL_BAD) /* hypervisor software trap */
438 TRAP(tt0_1c4, HCALL_BAD) /* hypervisor software trap */
439 TRAP(tt0_1c5, HCALL_BAD) /* hypervisor software trap */
440 TRAP(tt0_1c6, HCALL_BAD) /* hypervisor software trap */
441 TRAP(tt0_1c7, HCALL_BAD) /* hypervisor software trap */
442 TRAP(tt0_1c8, HCALL_BAD) /* hypervisor software trap */
443 TRAP(tt0_1c9, HCALL_BAD) /* hypervisor software trap */
444 TRAP(tt0_1ca, HCALL_BAD) /* hypervisor software trap */
445 TRAP(tt0_1cb, HCALL_BAD) /* hypervisor software trap */
446 TRAP(tt0_1cc, HCALL_BAD) /* hypervisor software trap */
447 TRAP(tt0_1cd, HCALL_BAD) /* hypervisor software trap */
448 TRAP(tt0_1ce, HCALL_BAD) /* hypervisor software trap */
449 TRAP(tt0_1cf, HCALL_BAD) /* hypervisor software trap */
450 TRAP(tt0_1d0, HCALL_BAD) /* hypervisor software trap */
451 TRAP(tt0_1d1, HCALL_BAD) /* hypervisor software trap */
452 TRAP(tt0_1d2, HCALL_BAD) /* hypervisor software trap */
453 TRAP(tt0_1d3, HCALL_BAD) /* hypervisor software trap */
454 TRAP(tt0_1d4, HCALL_BAD) /* hypervisor software trap */
455 TRAP(tt0_1d5, HCALL_BAD) /* hypervisor software trap */
456 TRAP(tt0_1d6, HCALL_BAD) /* hypervisor software trap */
457 TRAP(tt0_1d7, HCALL_BAD) /* hypervisor software trap */
458 TRAP(tt0_1d8, HCALL_BAD) /* hypervisor software trap */
459 TRAP(tt0_1d9, HCALL_BAD) /* hypervisor software trap */
460 TRAP(tt0_1da, HCALL_BAD) /* hypervisor software trap */
461 TRAP(tt0_1db, HCALL_BAD) /* hypervisor software trap */
462 TRAP(tt0_1dc, HCALL_BAD) /* hypervisor software trap */
463 TRAP(tt0_1dd, HCALL_BAD) /* hypervisor software trap */
464 TRAP(tt0_1de, HCALL_BAD) /* hypervisor software trap */
465 TRAP(tt0_1df, HCALL_BAD) /* hypervisor software trap */
466 TRAP(tt0_1e0, HCALL_BAD) /* hypervisor software trap */
467 TRAP(tt0_1e1, HCALL_BAD) /* hypervisor software trap */
468 TRAP(tt0_1e2, HCALL_BAD) /* hypervisor software trap */
469 TRAP(tt0_1e3, HCALL_BAD) /* hypervisor software trap */
470 TRAP(tt0_1e4, HCALL_BAD) /* hypervisor software trap */
471 TRAP(tt0_1e5, HCALL_BAD) /* hypervisor software trap */
472 TRAP(tt0_1e6, HCALL_BAD) /* hypervisor software trap */
473 TRAP(tt0_1e7, HCALL_BAD) /* hypervisor software trap */
474 TRAP(tt0_1e8, HCALL_BAD) /* hypervisor software trap */
475 TRAP(tt0_1e9, HCALL_BAD) /* hypervisor software trap */
476 TRAP(tt0_1ea, HCALL_BAD) /* hypervisor software trap */
477 TRAP(tt0_1eb, HCALL_BAD) /* hypervisor software trap */
478 TRAP(tt0_1ec, HCALL_BAD) /* hypervisor software trap */
479 TRAP(tt0_1ed, HCALL_BAD) /* hypervisor software trap */
480 TRAP(tt0_1ee, HCALL_BAD) /* hypervisor software trap */
481 TRAP(tt0_1ef, HCALL_BAD) /* hypervisor software trap */
482 TRAP(tt0_1f0, HCALL_BAD) /* hypervisor software trap */
483 TRAP(tt0_1f1, HCALL_BAD) /* hypervisor software trap */
484 TRAP(tt0_1f2, HCALL_BAD) /* hypervisor software trap */
485 TRAP(tt0_1f3, HCALL_BAD) /* hypervisor software trap */
486 TRAP(tt0_1f4, HCALL_BAD) /* hypervisor software trap */
487 TRAP(tt0_1f5, HCALL_BAD) /* hypervisor software trap */
488 TRAP(tt0_1f6, HCALL_BAD) /* hypervisor software trap */
489 TRAP(tt0_1f7, HCALL_BAD) /* hypervisor software trap */
490 TRAP(tt0_1f8, HCALL_BAD) /* hypervisor software trap */
491 TRAP(tt0_1f9, HCALL_BAD) /* hypervisor software trap */
492 TRAP(tt0_1fa, HCALL_BAD) /* hypervisor software trap */
493 TRAP(tt0_1fb, HCALL_BAD) /* hypervisor software trap */
494 TRAP(tt0_1fc, HCALL_BAD) /* hypervisor software trap */
495 TRAP(tt0_1fd, HCALL_BAD) /* hypervisor software trap */
496 TRAP(tt0_1fe, HCALL_BAD) /* hypervisor software trap */
497 TRAP(tt0_1ff, GOTO(hcall_core)) /* hypervisor software trap */
498ehtraptable:
499 SET_SIZE(htraptable)
500
501/*
502 * Sparc V9 TBA registers require that bits 14 through 0 must be zero.
503 * Ensure the trap tracing table is aligned on a TRAPTABLE_SIZE boundry.
504 * For additional information, refer to:
505 * "The SPARC Architecture Manual", Version 9,
506 * Section 5.2.8 "Trap Base Address (TBA)"
507 *
508 * There should be nothing in the .text segment between ehtraptable
509 * and htraptracetable.
510 */
511 ENTRY(htraptracetable)
512 TTRACE_TRAP_TABLE
513ehtraptracetable:
514 SET_SIZE(htraptracetable)
515
516/*
517 * revector - revector a trap to the guest as if the guest received
518 * it directly
519 *
520 * %g1 - new trap type for guest
521 */
522 ENTRY_NP(revector)
523 rdhpr %htstate, %g2
524 btst HTSTATE_HPRIV, %g2
525 bnz,pn %xcc, badtrap
526 .empty
527
528 rdpr %pstate, %g2
529 or %g2, PSTATE_PRIV, %g2
530 wrpr %g2, %pstate
531
532 rdpr %tba, %g2
533 wrpr %g1, %tt
534 sllx %g1, 5, %g1
535 add %g2, %g1, %g1
536 !! %g1 tba offset to branch to in tt0
537
538 rdpr %tl, %g3
539 cmp %g3, MAXPTL
540 bgu,pn %xcc, watchdog_guest
541 sub %g3, 1, %g2 ! %g3 is either 1 or 2
542 sllx %g2, 14, %g2
543 !! %g2 tt1 offset for trap vector for traps at tl>0
544
545 mov HPSTATE_GUEST, %g3
546 jmp %g1 + %g2
547 wrhpr %g3, %hpstate ! keep ENB bit
548 SET_SIZE(revector)
549
550 ENTRY_NP(watchdog_guest)
551#ifdef DEBUG /* { */
552 LEGION_GOT_HERE
553 STRAND_STRUCT(%g1)
554
555 ! Save some locals so we can use them while moving around
556 ! the trap levels
557 stx %l0, [%g1 + STRAND_SCR0]
558 stx %l1, [%g1 + STRAND_SCR1]
559 stx %l2, [%g1 + STRAND_SCR2]
560 stx %l3, [%g1 + STRAND_SCR3]
561 mov %g1, %l0
562
563 ! Save current %tl and %gl
564 rdpr %tl, %l2
565 set STRAND_FAIL_TL, %l1
566 stx %l2, [%l0 + %l1]
567 rdpr %gl, %l2
568 set STRAND_FAIL_GL, %l1
569 stx %l2, [%l0 + %l1]
570
571 ! for each %tl 1..%tl
572 set STRAND_FAIL_TRAPSTATE, %l1
573 add %l0, %l1, %l1
574 rdpr %tl, %l2
575 sub %l2, 1, %l3 ! tl - 1
576 mulx %l3, TRAPSTATE_SIZE, %l3
577 add %l1, %l3, %l1 ! %l1 pointer to current trapstate
5781: wrpr %l2, %tl ! %l2 current tl
579 rdhpr %htstate, %l3
580 stx %l3, [%l1 + TRAPSTATE_HTSTATE]
581 rdpr %tstate, %l3
582 stx %l3, [%l1 + TRAPSTATE_TSTATE]
583 rdpr %tt, %l3
584 stx %l3, [%l1 + TRAPSTATE_TT]
585 rdpr %tpc, %l3
586 stx %l3, [%l1 + TRAPSTATE_TPC]
587 rdpr %tnpc, %l3
588 stx %l3, [%l1 + TRAPSTATE_TNPC]
589 deccc %l2
590 bnz,pt %xcc, 1b
591 dec TRAPSTATE_SIZE, %l1
592
593 ! for each %gl 0..%gl-1
594 set STRAND_FAIL_TRAPGLOBALS, %l1
595 add %l0, %l1, %l1
596 rdpr %gl, %l2
597 dec %l2 ! gl - 1
598 mulx %l2, TRAPGLOBALS_SIZE, %l3
599 add %l1, %l3, %l1 ! %l1 pointer to current trapglobals
6001: wrpr %l2, %gl ! %l2 current gl
601 stx %g0, [%l1 + 0x00]
602 stx %g1, [%l1 + 0x08]
603 stx %g2, [%l1 + 0x10]
604 stx %g3, [%l1 + 0x18]
605 stx %g4, [%l1 + 0x20]
606 stx %g5, [%l1 + 0x28]
607 stx %g6, [%l1 + 0x30]
608 stx %g7, [%l1 + 0x38]
609 deccc %l2
610 bge,pt %xcc, 1b
611 dec TRAPGLOBALS_SIZE, %l1
612
613 ! Restore state
614 set STRAND_FAIL_TL, %l1
615 ldx [%l0 + %l1], %l2
616 wrpr %l2, %tl
617 set STRAND_FAIL_GL, %l1
618 ldx [%l0 + %l1], %l2
619 wrpr %l2, %gl
620
621 !! %l0 = strand struct
622
623 DEBUG_SPINLOCK_ENTER(%g1, %g2, %g3)
624
625 HV_PRINT_NOTRAP("WATCHDOG: strand: ")
626 ldub [%l0 + STRAND_ID], %g1
627 HV_PRINTX_NOTRAP(%g1)
628 HV_PRINT_NOTRAP(" vcpu: ")
629 VCPU_STRUCT(%l1)
630 ldub [%l1 + CPU_VID], %g1 /* FIXME : VCPU_ID */
631 HV_PRINTX_NOTRAP(%g1)
632
633 HV_PRINT_NOTRAP(" tl: ")
634 rdpr %tl, %g1
635 HV_PRINTX_NOTRAP(%g1)
636
637 HV_PRINT_NOTRAP(" tt: ")
638 rdpr %tt, %g1
639 HV_PRINTX_NOTRAP(%g1)
640
641 HV_PRINT_NOTRAP(" gl: ")
642 rdpr %gl, %g1
643 HV_PRINTX_NOTRAP(%g1)
644 HV_PRINT_NOTRAP("\r\n")
645
646 HV_PRINT_NOTRAP(" trap state:\r\n");
647 set STRAND_FAIL_TRAPSTATE, %l1
648 add %l0, %l1, %l1
649 rdpr %tl, %l2
650 mov 1, %l3
6511:
652 HV_PRINT_NOTRAP(" tl: ");
653 mov %l3, %g1
654 HV_PRINTX_NOTRAP(%g1)
655
656 HV_PRINT_NOTRAP(" tt: ");
657 ldx [%l1 + TRAPSTATE_TT], %g1
658 HV_PRINTX_NOTRAP(%g1)
659
660 HV_PRINT_NOTRAP(" htstate: ");
661 ldx [%l1 + TRAPSTATE_HTSTATE], %g1
662 HV_PRINTX_NOTRAP(%g1)
663
664 HV_PRINT_NOTRAP(" tstate: ");
665 ldx [%l1 + TRAPSTATE_TSTATE], %g1
666 HV_PRINTX_NOTRAP(%g1)
667
668 HV_PRINT_NOTRAP("\r\n tpc: ");
669 ldx [%l1 + TRAPSTATE_TPC], %g1
670 HV_PRINTX_NOTRAP(%g1)
671
672 HV_PRINT_NOTRAP(" tnpc: ");
673 ldx [%l1 + TRAPSTATE_TNPC], %g1
674 HV_PRINTX_NOTRAP(%g1)
675 HV_PRINT_NOTRAP("\r\n");
676 inc %l3
677 cmp %l3, %l2
678 bleu,pt %xcc, 1b
679 inc TRAPSTATE_SIZE, %l1
680
681 HV_PRINT_NOTRAP(" trap globals:\r\n");
682 set STRAND_FAIL_TRAPGLOBALS, %l1
683 add %l0, %l1, %l1
684 rdpr %gl, %l2
685 mov 0, %l3
6861:
687 HV_PRINT_NOTRAP(" gl: ");
688 HV_PRINTX_NOTRAP(%l3)
689
690 HV_PRINT_NOTRAP("\r\n");
691 HV_PRINT_NOTRAP(" %g0-%g3: ");
692 ldx [%l1 + 0x00], %g1
693 HV_PRINTX_NOTRAP(%g1)
694 HV_PRINT_NOTRAP(" ");
695 ldx [%l1 + 0x08], %g1
696 HV_PRINTX_NOTRAP(%g1)
697 HV_PRINT_NOTRAP(" ");
698 ldx [%l1 + 0x10], %g1
699 HV_PRINTX_NOTRAP(%g1)
700 HV_PRINT_NOTRAP(" ");
701 ldx [%l1 + 0x18], %g1
702 HV_PRINTX_NOTRAP(%g1)
703 HV_PRINT_NOTRAP("\r\n");
704 HV_PRINT_NOTRAP(" %g4-%g7: ");
705 ldx [%l1 + 0x20], %g1
706 HV_PRINTX_NOTRAP(%g1)
707 HV_PRINT_NOTRAP(" ");
708 ldx [%l1 + 0x28], %g1
709 HV_PRINTX_NOTRAP(%g1)
710 HV_PRINT_NOTRAP(" ");
711 ldx [%l1 + 0x30], %g1
712 HV_PRINTX_NOTRAP(%g1)
713 HV_PRINT_NOTRAP(" ");
714 ldx [%l1 + 0x38], %g1
715 HV_PRINTX_NOTRAP(%g1)
716 HV_PRINT_NOTRAP("\r\n");
717 inc %l3
718 cmp %l3, %l2
719 blu,pt %xcc, 1b
720 inc TRAPGLOBALS_SIZE, %l1
721
722 HV_PRINT_NOTRAP("\r\n current window:\r\n");
723 HV_PRINT_NOTRAP(" %o0-%o3: ");
724 mov %o0, %g1
725 HV_PRINTX_NOTRAP(%g1)
726 HV_PRINT_NOTRAP(" ");
727 mov %o1, %g1
728 HV_PRINTX_NOTRAP(%g1)
729 HV_PRINT_NOTRAP(" ");
730 mov %o2, %g1
731 HV_PRINTX_NOTRAP(%g1)
732 HV_PRINT_NOTRAP(" ");
733 mov %o3, %g1
734 HV_PRINTX_NOTRAP(%g1)
735 HV_PRINT_NOTRAP("\r\n");
736 HV_PRINT_NOTRAP(" %o4-%o7: ");
737 mov %o4, %g1
738 HV_PRINTX_NOTRAP(%g1)
739 HV_PRINT_NOTRAP(" ");
740 mov %o5, %g1
741 HV_PRINTX_NOTRAP(%g1)
742 HV_PRINT_NOTRAP(" ");
743 mov %o6, %g1
744 HV_PRINTX_NOTRAP(%g1)
745 HV_PRINT_NOTRAP(" ");
746 mov %o7, %g1
747 HV_PRINTX_NOTRAP(%g1)
748 HV_PRINT_NOTRAP("\r\n");
749
750 HV_PRINT_NOTRAP("rtba: ")
751 VCPU_STRUCT(%g1)
752 ldx [%g1 + CPU_RTBA], %g1
753 HV_PRINTX_NOTRAP(%g1)
754 HV_PRINT_NOTRAP("\r\n");
755
756 DEBUG_SPINLOCK_EXIT(%g1)
757
758#ifdef T1_FPGA
759 HV_PRINT_NOTRAP("Entering infinite loop in the Hypervisor. \r\n")
760watchdog_inf_loop:
761 brz,pt %g0, watchdog_inf_loop
762 nop
763#endif
764
765 ! Restore saved locals
766 ldx [%l0 + STRAND_SCR3], %l3
767 ldx [%l0 + STRAND_SCR2], %l2
768 ldx [%l0 + STRAND_SCR1], %l1
769 ldx [%l0 + STRAND_SCR0], %l0
770#endif /* } DEBUG */
771 ! Disable MMU
772 ldxa [%g0]ASI_LSUCR, %g1
773 set (LSUCR_DM | LSUCR_IM), %g2
774 andn %g1, %g2, %g1 ! disable MMU
775 stxa %g1, [%g0]ASI_LSUCR
776
777 ! Get real-mode trap table base address
778 VCPU_STRUCT(%g3)
779 ldx [%g3 + CPU_RTBA], %g3
780 add %g3, (TT_GUEST_WATCHDOG << TT_OFFSET_SHIFT), %g3
781 rdpr %tt, %g5
782 wrpr %g0, MAXPTL, %tl
783 wrpr %g5, %tt
784 mov %g3, %o0 ! XXX clobbering %o0
785 wrpr %g0, MAXPGL, %gl
786 mov HPSTATE_GUEST, %g1 ! XXX clobbering %g1
787 jmp %o0
788 wrhpr %g1, %hpstate ! set ENB bit
789 SET_SIZE(watchdog_guest)
790
791
792 ! ttrace_generic
793 ! General purpose trap trace routine.
794 !
795 ! Records state. (See traptrace.h for details.)
796 ! Variable Fields:
797 ! All fields are zeroed.
798 !
799 ! Expects: %g7 to contain PC of trap table entry
800 !
801 ENTRY_NP(ttrace_generic)
802 TTRACE_PTR(%g1, %g2, 1f, 1f)
803 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
804 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
805 stx %g0, [%g2 + TTRACE_ENTRY_F1]
806 stx %g0, [%g2 + TTRACE_ENTRY_F2]
807 stx %g0, [%g2 + TTRACE_ENTRY_F3]
808 stx %g0, [%g2 + TTRACE_ENTRY_F4]
809 TTRACE_NEXT(%g2, %g3, %g4, %g5)
8101: TTRACE_EXIT(%g7, %g1)
811 SET_SIZE(ttrace_generic)
812
813 ! ttrace_immu
814 ! Traces instruction access exceptions.
815 !
816 ! Records state. (See traptrace.h for details.)
817 ! Variable Fields:
818 ! F1 = IMMU SFSR
819 !
820 ! Expects: %g7 to contain PC of trap table entry
821 !
822 ENTRY_NP(ttrace_immu)
823 TTRACE_PTR(%g1, %g2, 1f, 1f)
824 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
825 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
826 mov MMU_SFSR, %g4
827 ldxa [%g4]ASI_IMMU, %g4
828 stx %g4, [%g2 + TTRACE_ENTRY_F1]
829 stx %g0, [%g2 + TTRACE_ENTRY_F2]
830 stx %g0, [%g2 + TTRACE_ENTRY_F3]
831 stx %g0, [%g2 + TTRACE_ENTRY_F4]
832 TTRACE_NEXT(%g2, %g3, %g4, %g5)
8331: TTRACE_EXIT(%g7, %g1)
834 SET_SIZE(ttrace_immu)
835
836 ! ttrace_dmmu
837 ! Traces data mmu exceptions.
838 !
839 ! Records state. (See traptrace.h for details.)
840 ! Variable Fields:
841 ! F1 = DMMU SFSR
842 ! F2 = DMMU SFAR
843 !
844 ! Expects: %g7 to contain PC of trap table entry
845 !
846 ENTRY_NP(ttrace_dmmu)
847 TTRACE_PTR(%g1, %g2, 1f, 1f)
848 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
849 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
850 mov MMU_SFSR, %g4
851 ldxa [%g4]ASI_DMMU, %g4
852 stx %g4, [%g2 + TTRACE_ENTRY_F1]
853 mov MMU_SFAR, %g4
854 ldxa [%g4]ASI_DMMU, %g4
855 stx %g4, [%g2 + TTRACE_ENTRY_F2]
856 stx %g0, [%g2 + TTRACE_ENTRY_F3]
857 stx %g0, [%g2 + TTRACE_ENTRY_F4]
858 TTRACE_NEXT(%g2, %g3, %g4, %g5)
8591: TTRACE_EXIT(%g7, %g1)
860 SET_SIZE(ttrace_dmmu)
861
862 ! ttrace_hcall
863 ! Traces hypervisor call traps.
864 !
865 ! Records state. (See traptrace.h for details.)
866 ! Variable Fields:
867 ! TAG = %o5, Hypervisor Call Number
868 ! F1 = %o0, Argument 0
869 ! F2 = %o1, Argument 1
870 ! F3 = %o2, Argument 2
871 ! F4 = %o3, Argument 3
872 !
873 ! Expects: %g7 to contain PC of trap table entry
874 !
875 ENTRY_NP(ttrace_hcall)
876 TTRACE_PTR(%g1, %g2, 1f, 1f)
877 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
878 sth %o5, [%g2 + TTRACE_ENTRY_TAG]
879 stx %o0, [%g2 + TTRACE_ENTRY_F1]
880 stx %o1, [%g2 + TTRACE_ENTRY_F2]
881 stx %o2, [%g2 + TTRACE_ENTRY_F3]
882 stx %o3, [%g2 + TTRACE_ENTRY_F4]
883 TTRACE_NEXT(%g2, %g3, %g4, %g5)
8841: TTRACE_EXIT(%g7, %g1)
885 SET_SIZE(ttrace_hcall)
886
887 ! ttrace_mmu_map
888 ! Traces mmu map traps.
889 !
890 ! Records state. (See traptrace.h for details.)
891 ! Variable Fields:
892 ! F1 = vaddr
893 ! F2 = ctx
894 ! F3 = TTE
895 ! F4 = flags
896 !
897 ! Expects: %g7 to contain PC of trap table entry
898 !
899 ENTRY_NP(ttrace_mmu_map)
900 TTRACE_PTR(%g1, %g2, 1f, 1f)
901 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
902 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
903 stx %o0, [%g2 + TTRACE_ENTRY_F1]
904 stx %o1, [%g2 + TTRACE_ENTRY_F2]
905 stx %o2, [%g2 + TTRACE_ENTRY_F3]
906 stx %o3, [%g2 + TTRACE_ENTRY_F4]
907 TTRACE_NEXT(%g2, %g3, %g4, %g5)
9081: TTRACE_EXIT(%g7, %g1)
909 SET_SIZE(ttrace_mmu_map)
910
911 ! ttrace_mmu_unmap
912 ! Traces MMU Unmap traps.
913 !
914 ! Records state. (See traptrace.h for details.)
915 ! Variable Fields:
916 ! F1 = vaddr
917 ! F2 = ctx
918 ! F3 = flags
919 !
920 ! Expects: %g7 to contain PC of trap table entry
921 !
922 ENTRY_NP(ttrace_mmu_unmap)
923 TTRACE_PTR(%g1, %g2, 1f, 1f)
924 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
925 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
926 stx %o0, [%g2 + TTRACE_ENTRY_F1]
927 stx %o1, [%g2 + TTRACE_ENTRY_F2]
928 stx %o2, [%g2 + TTRACE_ENTRY_F3]
929 stx %g0, [%g2 + TTRACE_ENTRY_F4]
930 TTRACE_NEXT(%g2, %g3, %g4, %g5)
9311: TTRACE_EXIT(%g7, %g1)
932 SET_SIZE(ttrace_mmu_unmap)
933
934 ! ttrace_ce
935 ! Trace CE error traps
936 !
937 ! Records state. (See traptrace.h for details.)
938 ! Variable Fields:
939 ! F1 = ce esr
940 ! F2 = ce asr
941 !
942 ! Expects: %g7 to contain PC of trap table entry
943 !
944 ENTRY_NP(ttrace_ce)
945 TTRACE_PTR(%g1, %g2, 1f, 1f)
946 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
947 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
948 ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4
949 ldxa [%g0]ASI_SPARC_ERR_ADDR, %g5
950 stx %g4, [%g2 + TTRACE_ENTRY_F1]
951 stx %g5, [%g2 + TTRACE_ENTRY_F2]
952 stx %g0, [%g2 + TTRACE_ENTRY_F3]
953 stx %g0, [%g2 + TTRACE_ENTRY_F4]
954 TTRACE_NEXT(%g2, %g3, %g4, %g5)
9551: TTRACE_EXIT(%g7, %g1)
956 SET_SIZE(ttrace_ce)
957
958 ! ttrace_ue
959 ! Trace UE error traps
960 !
961 ! Records state. (See traptrace.h for details.)
962 ! Variable Fields:
963 ! F1 = ue esr
964 ! F2 = ue asr
965 !
966 ! Expects: %g7 to contain PC of trap table entry
967 !
968 ENTRY_NP(ttrace_ue)
969 TTRACE_PTR(%g1, %g2, 1f, 1f)
970 TTRACE_STATE(%g2, TTRACE_TYPE_HV, %g3, %g4)
971 sth %g0, [%g2 + TTRACE_ENTRY_TAG]
972 ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4
973 ldxa [%g0]ASI_SPARC_ERR_ADDR, %g5
974 stx %g4, [%g2 + TTRACE_ENTRY_F1]
975 stx %g5, [%g2 + TTRACE_ENTRY_F2]
976 stx %g0, [%g2 + TTRACE_ENTRY_F3]
977 stx %g0, [%g2 + TTRACE_ENTRY_F4]
978 TTRACE_NEXT(%g2, %g3, %g4, %g5)
9791: TTRACE_EXIT(%g7, %g1)
980 SET_SIZE(ttrace_ue)
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.