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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / src / vpci_errs.s
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: vpci_errs.s
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
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33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49 .ident "@(#)vpci_errs.s 1.23 07/05/03 SMI"
50
51#include <sys/asm_linkage.h>
52#include <sys/htypes.h>
53#include <hypervisor.h>
54#include <sparcv9/asi.h>
55#include <sun4v/asi.h>
56#include <asi.h>
57#include <mmu.h>
58
59#include <guest.h>
60#include <strand.h>
61#include <offsets.h>
62#include <errs_common.h>
63#include <debug.h>
64#include <vpci_errs.h>
65#include <util.h>
66#include <abort.h>
67#include <vdev_intr.h>
68#include <fire.h>
69
70
71#define r_fire_cookie %g1
72#define r_fire_e_rpt %g2
73#define r_fire_leaf_address %g4
74
75#define r_tmp1 %g5
76#define r_tmp2 %g7
77
78#if defined(CONFIG_FIRE)
79
80 !! %g1 = Fire Cookie
81 !! %g2 = Mondo DATA0
82 !! %g3 = IGN
83 !! %g4 = INO
84 ENTRY_NP(error_mondo_62)
85 PRINT("HV:mondo 62\r\n")
86 mov %g2, %g7 ! save DATA0 for err handle setup
87
88 !!
89 !! Generate a unique error handle
90 !! enters with:
91 !! %g1 loaded with fire cookie
92 !! %g2 data0, overwritten with r_fire_e_rpt
93 !! %g3 IGN
94 !! %g4 INO
95 !! %g5 scratch
96 !! %g6 scratch
97 !! %g7 data0
98 !!
99 !! returns with:
100 !! %g1 r_fire_cookie
101 !! %g2 pointing to r_fire_e_rpt
102 !!
103 GEN_ERR_HNDL_SETUP_ERPTS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
104 ldx [r_fire_cookie + FIRE_COOKIE_PCIE], %g4
105 ! use alias r_fire_leaf_address for %g4 now
106 !!
107 !! %g1 Fire cookie
108 !! %g2 fire error rpt
109 !! %g3 - temporary
110 !! %g4 r_fire_leaf_address
111 !! %g5 - temporary, last register loaded
112 !!
113 ! which core interruped?
114 set FIRE_DLC_IMU_ICS_MULTI_CORE_ERROR_STATUS_REG, r_tmp2
115 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
116 and r_tmp1, DMC_BIT, r_tmp2
117 brnz,a r_tmp2, dmc_core_processing
118 stx r_tmp2, [r_fire_e_rpt + PCIERPT_MULTI_CORE_ERR_STATUS]
119 and r_tmp1, PEC_BIT, r_tmp2
120 brnz,a r_tmp2, pec_core_processing
121 stx r_tmp2, [r_fire_e_rpt + PCIERPT_MULTI_CORE_ERR_STATUS]
122 ! should not get here
123 PRINT("HV:mondo 62 fall through to retry\r\n")
124 ba,a clear_pcie_err_fire_interrupt
125 .empty
126
127dmc_core_processing:
128 PRINT("HV:PEC\r\n")
129 set FIRE_DLC_IMU_ICS_DMC_INTERRUPT_STATUS_REG, r_tmp2
130 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
131 and r_tmp1, MMU_BIT, r_tmp2
132 brnz,a r_tmp2, mmu_block_processing
133 stx r_tmp2, [r_fire_e_rpt + PCIERPT_DMC_CORE_AND_BLOCK_ERR_STATUS]
134 and r_tmp1, IMU_BIT, r_tmp2
135 brnz,a r_tmp2, imu_block_processing
136 stx r_tmp2, [r_fire_e_rpt + PCIERPT_DMC_CORE_AND_BLOCK_ERR_STATUS]
137 ! should not get here
138 PRINT("HV:PEC fallthrough to retry\r\n")
139 ba,a clear_pcie_err_fire_interrupt
140 .empty
141
142
143imu_block_processing:
144 PRINT("HV:imu_block_processing\r\n")
145 set FIRE_DLC_IMU_ICS_IMU_ENABLED_ERROR_STATUS_REG, r_tmp2
146 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
147 !r_tmp1 is not changed for this block
148
149.imu_eq_not_en_group_p:
150 PRINT("HV:.imu_eq_not_en_group_p\r\n")
151 btst IMU_EQ_NOT_EN_GROUP_P, r_tmp1
152 bz %xcc, .imu_eq_over_group_p
153 and r_tmp1, IMU_EQ_NOT_EN_GROUP_P, r_tmp2
154 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
155 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
156 r_tmp2)
157 LOG_IMU_SCS_ERROR_LOG_REGS(r_fire_e_rpt, r_fire_leaf_address, \
158 r_tmp1, r_tmp2)
159 LOG_IMU_EQ_NOT_EN_GROUP_EPKT_P(r_fire_e_rpt, \
160 r_fire_leaf_address, r_tmp1, r_tmp2)
161 CLEAR_IMU_EQ_NOT_EN_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
162 r_tmp1, r_tmp2)
163 ba,a pcie_err_mondo_ereport
164 .empty
165
166.imu_eq_over_group_p:
167 PRINT("HV:imu_eq_over_group_p\r\n")
168 btst IMU_EQ_OVER_GROUP_P, r_tmp1
169 bz %xcc, .imu_msi_mes_group_p
170 and r_tmp1, IMU_EQ_OVER_GROUP_P, r_tmp2
171 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
172 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
173 r_tmp2)
174 LOG_IMU_EQS_ERROR_LOG_REGS(r_fire_e_rpt, r_fire_leaf_address, \
175 r_tmp1, r_tmp2)
176 LOG_IMU_EQ_OVER_GROUP_EPKT_P_S(r_fire_e_rpt, \
177 r_fire_leaf_address, r_tmp1, r_tmp2)
178 CLEAR_IMU_EQ_OVER_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
179 r_tmp1, r_tmp2)
180 ba,a pcie_err_mondo_ereport
181 .empty
182
183.imu_msi_mes_group_p:
184 PRINT("HV:imu_msi_mes_group_p\r\n")
185 btst IMU_MSI_MES_GROUP_P, r_tmp1
186 bz %xcc, .imu_eq_not_en_group_s
187 and r_tmp1, IMU_MSI_MES_GROUP_P, r_tmp2
188 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
189 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
190 r_tmp2)
191 LOG_IMU_RDS_ERROR_LOG_REG(r_fire_e_rpt, r_fire_leaf_address, \
192 r_tmp1, r_tmp2)
193 LOG_IMU_MSI_MES_GROUP_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, \
194 r_tmp1, r_tmp2)
195 CLEAR_IMU_MSI_MES_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
196 r_tmp1, r_tmp2)
197 ba,a pcie_err_mondo_ereport
198 .empty
199
200.imu_eq_not_en_group_s:
201 PRINT("HV:imu_eq_not_en_group_s\r\n")
202 set IMU_EQ_NOT_EN_GROUP_P, r_tmp2
203 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
204 btst r_tmp2, r_tmp1
205 bz %xcc, .imu_eq_over_group_s
206 and r_tmp2, r_tmp1, r_tmp2
207 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
208 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
209 r_tmp2)
210 LOG_IMU_EQ_NOT_EN_GROUP_EPKT_S(r_fire_e_rpt, \
211 r_fire_leaf_address, r_tmp1, r_tmp2)
212 CLEAR_IMU_EQ_NOT_EN_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
213 r_tmp1, r_tmp2)
214 ba,a pcie_err_mondo_ereport
215 .empty
216
217.imu_eq_over_group_s:
218 PRINT("HV:imu_eq_over_group_s\r\n")
219 set IMU_EQ_OVER_GROUP_P, r_tmp2
220 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
221 btst r_tmp2, r_tmp1
222 bz %xcc, .imu_msi_mes_group_s
223 and r_tmp2, r_tmp1, r_tmp2
224 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
225 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
226 LOG_IMU_EQ_OVER_GROUP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address,\
227 r_tmp1, r_tmp2)
228 CLEAR_IMU_EQ_OVER_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
229 r_tmp1, r_tmp2)
230 ba,a pcie_err_mondo_ereport
231 .empty
232
233.imu_msi_mes_group_s:
234 PRINT("HV:imu_msi_mes_group_s\r\n")
235 set IMU_MSI_MES_GROUP_P, r_tmp2
236 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
237 btst r_tmp2, r_tmp1
238 bz,pn %xcc, .imu_block_processing_nothing_to_do
239 and r_tmp2, r_tmp1, r_tmp2
240 stx r_tmp2, [r_fire_e_rpt + PCIERPT_IMU_ENABLED_ERR_STATUS]
241 LOG_DMC_IMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
242 CLEAR_IMU_MSI_MES_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
243 r_tmp1, r_tmp2)
244 ba,a clear_pcie_err_fire_interrupt
245 .empty
246
247.imu_block_processing_nothing_to_do:
248 PRINT("HV:imu_block_processing_nothing_to_do\r\n")
249 ! we should not get here
250 ba,a clear_pcie_err_fire_interrupt
251 .empty
252
253mmu_block_processing:
254 PRINT("HV:mmu_block_processing\r\n")
255 set FIRE_DLC_MMU_EN_ERR, r_tmp2
256 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
257
258.mmu_err_group_p:
259 PRINT("HV:mmu_err_group_p\r\n")
260 PRINT("HV:FIRE_DLC_MMU_EN_ERR:0x")
261 PRINTX(r_tmp1)
262 PRINT("\r\n")
263#ifdef DEBUG
264 /* PRINT() destroys %g7, which is r_tmp2, so need to reload the reg */
265 set FIRE_DLC_MMU_EN_ERR, r_tmp2
266 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
267#endif
268 set MMU_ERR_GROUP_P, r_tmp2
269 btst r_tmp2, r_tmp1
270 bz %xcc, .mmu_err_group_s
271 and r_tmp1, r_tmp2, r_tmp2
272 stx r_tmp2, [r_fire_e_rpt + PCIERPT_MMU_INTR_STATUS]
273 LOG_DMC_MMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
274 LOG_MMU_TRANS_FAULT_REGS(r_fire_e_rpt, r_fire_leaf_address, \
275 r_tmp1, r_tmp2)
276 LOG_MMU_ERR_GROUP_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, \
277 r_tmp1, r_tmp2)
278 CLEAR_MMU_ERR_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
279 r_tmp1, r_tmp2)
280 ba,a pcie_err_mondo_ereport
281 .empty
282
283.mmu_err_group_s:
284 PRINT("HV:mmu_err_group_s\r\n")
285 set MMU_ERR_GROUP_P, r_tmp2
286 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
287 btst r_tmp2, r_tmp1
288 bz,pn %xcc, .mmu_block_processing_nothing_to_do
289 and r_tmp2, r_tmp1, r_tmp2
290 stx r_tmp2, [r_fire_e_rpt + PCIERPT_MMU_INTR_STATUS]
291 LOG_DMC_MMU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
292 r_tmp2)
293 CLEAR_MMU_ERR_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
294 r_tmp1, r_tmp2)
295 ba,a clear_pcie_err_fire_interrupt
296 .empty
297
298.mmu_block_processing_nothing_to_do:
299 PRINT("HV:mmu_block_processing_nothing_to_do\r\n")
300 ! we should not get here
301 ba,a clear_pcie_err_fire_interrupt
302 .empty
303
304! read the PEC Core and Block Error Status Register (0x651808, 0x751808).
305! This register describes which one or more than one of the 4 possible block(s)
306! in the PEC Core has an error which needs to be processed.
307! bit 0 set in this register the Mondo was caused by the a PEC OE register.
308! bit 1 set in this register means the Mondo was caused by the PEC CE Register.
309! bit 2 set in this register means the Mondo was caused by the PEC UE Register.
310! bit 3 was set in this register the Mondo was caused by the ILU block.
311pec_core_processing:
312 PRINT("HV:pec_core_processing\r\n")
313 set FIRE_DLC_ILU_CIB_PEC_EN_ERR, r_tmp2
314 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
315 and r_tmp1, PEC_ILU_BIT, r_tmp2
316 brnz,a r_tmp2, .pec_ilu_processing
317 stx r_tmp2, [r_fire_e_rpt + PCIERPT_PEC_CORE_AND_BLOCK_INTR_STATUS]
318 and r_tmp1, PEC_UE_BIT, r_tmp2
319 brnz,a r_tmp2, .pec_ue_processing
320 stx r_tmp2, [r_fire_e_rpt + PCIERPT_PEC_CORE_AND_BLOCK_INTR_STATUS]
321 and r_tmp1, PEC_CE_BIT, r_tmp2
322 brnz,a r_tmp2, .pec_ce_processing
323 stx r_tmp2, [r_fire_e_rpt + PCIERPT_PEC_CORE_AND_BLOCK_INTR_STATUS]
324 and r_tmp1, PEC_OE_BIT, r_tmp2
325 brnz,a,pt r_tmp2, .pec_oe_processing
326 stx r_tmp2, [r_fire_e_rpt + PCIERPT_PEC_CORE_AND_BLOCK_INTR_STATUS]
327 ba,a clear_pcie_err_fire_interrupt
328 .empty
329
330.pec_ilu_processing:
331.ilu_interrupt_status_p:
332 PRINT("HV:ilu_interrupt_status_p\r\n")
333 set FIRE_DLC_ILU_CIB_ILU_EN_ERR, r_tmp2
334 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
335 btst ILU_GROUP_P, r_tmp1
336 bz %xcc, .ilu_interrupt_status_s
337 and r_tmp1, ILU_GROUP_P, r_tmp2
338 stx r_tmp2, [r_fire_e_rpt + PCIERPT_ILU_INTR_STATUS]
339 LOG_ILU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
340 LOG_ILU_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
341 CLEAR_ILU_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
342
343 ba,a pcie_err_mondo_ereport
344 .empty
345
346
347.ilu_interrupt_status_s:
348 PRINT("HV:ilu_interrupt_status_s\r\n")
349 set ILU_GROUP_P, r_tmp2
350 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
351 btst r_tmp2, r_tmp1
352 bz,pn %xcc, .ilu_nothing_todo
353 and r_tmp2, r_tmp1, r_tmp2
354 stx r_tmp2, [r_fire_e_rpt + PCIERPT_ILU_INTR_STATUS]
355 LOG_ILU_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
356 CLEAR_ILU_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
357 ba,a clear_pcie_err_fire_interrupt
358 .empty
359
360.ilu_nothing_todo:
361 PRINT("HV:ilu_nothing_todo\r\n")
362 ba,a clear_pcie_err_fire_interrupt
363 .empty
364
365! spec doesn't mention bits 15 and 13
366! bit 15 CA_P (Completer Abort Primary Error) does not capture any info
367! As for the completer abort, this is a resultant of many of the MMU errors
368! and not an error itself.
369! bit 13 FCP_P (Flow Control Protocol Primary error) does not capture any info
370! bits 17, 14 (rof, cto)
371! TLU Transmit Uncorrectable Error Header1 Log Register (0x691038, 0x791038 )
372! TLU Transmit Uncorrectable Error Header2 Log Register (0x691040, 0x791040 )
373!
374!
375! clear with TLU Uncorrectable Error Status Clear Register (0x691018, 0x791018)
376! no logging registers for bit 0 and 4
377.pec_ue_processing:
378.tlu_uce_recv_group_p:
379 PRINT("HV:tlu_uce_recv_group_p\r\n")
380 set FIRE_PLC_TLU_CTB_TLR_UE_EN_ERR, r_tmp2
381 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
382 set TLU_UE_RECV_GROUP_P, r_tmp2
383 and r_tmp2, r_tmp1, r_tmp2
384 brz r_tmp2, .tlu_uce_trans_group_p
385 nop
386 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
387 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
388 LOG_TLU_UE_RCV_HDR_REGS(r_fire_e_rpt, r_fire_leaf_address, \
389 r_tmp1, r_tmp2)
390 LOG_TLU_UE_RECV_GROUP_EPKT_P(r_fire_e_rpt, r_fire_leaf_address,\
391 r_tmp1, r_tmp2)
392 CLEAR_TLU_UE_RECV_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
393 r_tmp1, r_tmp2)
394 ba,a pcie_err_mondo_ereport
395 .empty
396
397
398.tlu_uce_trans_group_p:
399 PRINT("HV:tlu_uce_trans_group_p\r\n")
400 set TLU_UE_TRANS_GROUP_P, r_tmp2
401 and r_tmp2, r_tmp1, r_tmp2
402 brz r_tmp2, .tlu_uce_tlu_dlp_p
403 nop
404 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
405 PRINT("r_tmp1 0x")
406 PRINTX(r_tmp1)
407 PRINT("\r\n")
408 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
409 LOG_TLU_UE_TRANS_HDR_REGS(r_fire_e_rpt, r_fire_leaf_address, \
410 r_tmp1, r_tmp2)
411 LOG_TLU_UE_TRANS_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, \
412 r_tmp1, r_tmp2)
413 CLEAR_TLU_UE_TRANS_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
414 r_tmp1, r_tmp2)
415 ba,a pcie_err_mondo_ereport
416 .empty
417
418.tlu_uce_tlu_dlp_p:
419/*
420 * Special case error, no data, plus dup in another reg
421 */
422 PRINT("HV:tlu_uce_tlu_dlp_p\r\n")
423 set TLU_DLP_P, r_tmp2
424 and r_tmp2, r_tmp1, r_tmp2
425 brz r_tmp2, .tlu_uce_tlu_fcp_p
426 nop
427 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
428 PRINT("HV:r_tmp1 0x")
429 PRINTX(r_tmp1)
430 PRINT("\r\n")
431 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
432 LOG_TLU_UE_DLP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
433 r_tmp1, r_tmp2)
434 CLEAR_TLU_UE_DLP_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
435 r_tmp1, r_tmp2)
436 ba,a pcie_err_mondo_ereport
437 .empty
438
439.tlu_uce_tlu_fcp_p:
440 PRINT("HV:tlu_uce_tlu_fcp_p\r\n")
441 set TLU_FCP_P, r_tmp2
442 and r_tmp2, r_tmp1, r_tmp2
443 brz r_tmp2, .tlu_uce_tlu_ca_p
444 nop
445 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
446 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
447 LOG_TLU_UE_FCP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
448 r_tmp1, r_tmp2)
449 CLEAR_TLU_UE_FCP_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
450 r_tmp2)
451 ba,a pcie_err_mondo_ereport
452 .empty
453
454
455.tlu_uce_tlu_ca_p:
456 PRINT("HV:tlu_uce_tlu_fcp_p\r\n")
457 set TLU_CA_P, r_tmp2
458 and r_tmp2, r_tmp1, r_tmp2
459 brz r_tmp2, .tlu_uce_tlu_dlp_s
460 nop
461 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
462 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
463 LOG_TLU_UE_CA_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
464 r_tmp1, r_tmp2)
465 CLEAR_TLU_UE_CA_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
466 r_tmp2)
467 ba,a pcie_err_mondo_ereport
468 .empty
469
470.tlu_uce_tlu_dlp_s:
471/*
472 * Special case error, no data, plus dup in another reg
473 */
474 PRINT("HV:tlu_uce_tlu_dlp_s\r\n")
475 set TLU_DLP_P, r_tmp2
476 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
477 and r_tmp2, r_tmp1, r_tmp2
478 brz r_tmp2, .tlu_uce_tlu_te_p
479 nop
480 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
481 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
482 LOG_TLU_UE_DLP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
483 r_tmp1, r_tmp2)
484 CLEAR_TLU_UE_DLP_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
485 r_tmp1, r_tmp2)
486 ba,a pcie_err_mondo_ereport
487 .empty
488
489.tlu_uce_tlu_te_p:
490/*
491 * Special case error, no data, plus dup in another reg
492 */
493 PRINT("HV:tlu_uce_tlu_te_p\r\n")
494 set TLU_TE_P, r_tmp2
495 and r_tmp2, r_tmp1, r_tmp2
496 brz r_tmp2, .tlu_uce_tlu_te_s
497 nop
498 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
499 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
500 LOG_TLU_UE_TE_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
501 r_tmp1, r_tmp2)
502 CLEAR_TLU_UE_TE_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
503 r_tmp1, r_tmp2)
504 ba,a pcie_err_mondo_ereport
505 .empty
506
507.tlu_uce_tlu_te_s:
508/*
509 * Special case error, no data, plus dup in another reg
510 */
511 PRINT("HV:tlu_uce_tlu_te_s\r\n")
512 set TLU_TE_P, r_tmp2
513 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
514 and r_tmp2, r_tmp1, r_tmp2
515 brz r_tmp2, .tlu_uce_recv_group_s
516 nop
517 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
518 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
519 LOG_TLU_UE_TE_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
520 r_tmp1, r_tmp2)
521 CLEAR_TLU_UE_TE_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
522 r_tmp1, r_tmp2)
523 ba,a pcie_err_mondo_ereport
524 .empty
525
526.tlu_uce_recv_group_s:
527 PRINT("HV:tlu_uce_recv_group_s\r\n")
528 set TLU_UE_RECV_GROUP_P, r_tmp2
529 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
530 and r_tmp2, r_tmp1, r_tmp2
531 brz r_tmp2, .tlu_uce_trans_group_s
532 nop
533 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
534 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
535 LOG_TLU_UE_TRANS_HDR_REGS(r_fire_e_rpt, r_fire_leaf_address, \
536 r_tmp1, r_tmp2)
537 CLEAR_TLU_UE_RECV_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
538 r_tmp1, r_tmp2)
539 ba,a clear_pcie_err_fire_interrupt
540 .empty
541
542.tlu_uce_trans_group_s:
543 PRINT("HV:tlu_uce_trans_group_s\r\n")
544 set TLU_UE_TRANS_GROUP_P, r_tmp2
545 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
546 and r_tmp2, r_tmp1, r_tmp2
547 brz,pn r_tmp2, .tlu_uce_tlu_fcp_s
548 nop
549 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
550 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
551 r_tmp2)
552 LOG_TLU_UE_TRANS_EPKT_S(r_fire_e_rpt, r_fire_leaf_address, \
553 r_tmp1, r_tmp2)
554 CLEAR_TLU_UE_TRANS_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
555 r_tmp1, r_tmp2)
556 ba,a pcie_err_mondo_ereport
557 .empty
558
559.tlu_uce_tlu_fcp_s:
560 set TLU_FCP_P, r_tmp2
561 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
562 and r_tmp2, r_tmp1, r_tmp2
563 brz r_tmp2, .tlu_uce_tlu_ca_s
564 nop
565 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
566 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
567 LOG_TLU_UE_FCP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
568 r_tmp1, r_tmp2)
569 CLEAR_TLU_UE_FCP_S(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
570 r_tmp2)
571 ba,a pcie_err_mondo_ereport
572 .empty
573
574.tlu_uce_tlu_ca_s:
575 PRINT("HV:tlu_uce_tlu_ca_s\r\n")
576 set TLU_CA_P, r_tmp2
577 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
578 and r_tmp2, r_tmp1, r_tmp2
579 brz r_tmp2, .tlu_uce_nothingtodo
580 nop
581 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_UE_STATUS]
582 LOG_TLU_UE_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
583 LOG_TLU_UE_CA_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
584 r_tmp1, r_tmp2)
585 CLEAR_TLU_UE_CA_S(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
586 r_tmp2)
587 ba,a pcie_err_mondo_ereport
588 .empty
589
590.tlu_uce_nothingtodo:
591 PRINT("HV:tlu_uce_nothingtodo\r\n")
592 PRINT("HV:r_tmp1 0x")
593 PRINTX(r_tmp1)
594 PRINT("\r\n")
595 ba,a clear_pcie_err_fire_interrupt
596 .empty
597
598.pec_ce_processing:
599.pec_ce_primary:
600 PRINT("HV:pec_ce_processing\r\n")
601! to clear dup regs , read page 392 of the november fire spec
602 set FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR, r_tmp2
603 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
604 PRINT("HV:FIRE_PLC_TLU_CTB_TLR_CE_EN_ERRR = 0x")
605 PRINTX(r_tmp1)
606 PRINT("\r\n")
607 set TLU_CE_GROUP_P, r_tmp2
608 and r_tmp2, r_tmp1, r_tmp2
609 brz r_tmp2, .pec_ce_secondary
610 nop
611 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_CE_INTR_STATUS]
612 LOG_TLU_CE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
613 r_tmp2)
614 LOG_TLU_CE_GROUP_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, \
615 r_tmp1, r_tmp2)
616 CLEAR_TLU_CE_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
617 r_tmp2)
618 ba,a pcie_err_mondo_ereport
619 .empty
620
621.pec_ce_secondary:
622 PRINT("HV:pec_ce_secondary\r\n")
623 set TLU_CE_GROUP_P, r_tmp2
624 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
625 and r_tmp2, r_tmp1, r_tmp2
626 brz,pn r_tmp2, .pec_ce_nothingtodo
627 nop
628 stx r_tmp2, [r_fire_e_rpt + PCIERPT_TLU_CE_INTR_STATUS]
629 LOG_TLU_CE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
630 r_tmp2)
631 LOG_TLU_CE_GROUP_EPKT_S(r_fire_e_rpt, r_fire_leaf_address, \
632 r_tmp1, r_tmp2)
633 CLEAR_TLU_CE_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, \
634 r_tmp2)
635 ba,a pcie_err_mondo_ereport
636 .empty
637
638.pec_ce_nothingtodo:
639#ifdef DEBUG
640 PRINT("HV:pec_ce_nothingtodo\r\n")
641 set FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR, r_tmp2
642 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
643 PRINT("HV:FIRE_PLC_TLU_CTB_TLR_CE_EN_ERR:0x")
644 PRINTX(r_tmp1)
645 PRINT("\r\n")
646#endif
647 ba,a clear_pcie_err_fire_interrupt
648 .empty
649
650.pec_oe_processing:
651 PRINT("HV:pec_oe_processing\r\n")
652.tlu_receive_other_event_p:
653 PRINT("HV:tlu_receive_other_event_p\r\n")
654 /*
655 * Also logs trans regs
656 */
657 set FIRE_PLC_TLU_CTB_TLR_OE_EN_ERR, r_tmp2
658 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
659 PRINT("HV:contents = 0x")
660 PRINTX(r_tmp1)
661 PRINT("\r\n")
662 set TLU_OE_RECEIVE_GROUP_P, r_tmp2
663 btst r_tmp2, r_tmp1
664 bz %xcc, .tlu_oe_link_interrupt_group_p
665 nop
666 /*
667 * Special, this set of errors also records some in the transmit
668 * regs
669 */
670 set TLU_OE_TRANS_GROUP_P, r_tmp2
671 btst r_tmp2, r_tmp1
672 .pushlocals
673 bz %xcc, 1f
674 nop
675 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
676 r_tmp2)
677 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
678 r_tmp1, r_tmp2, TLU_OE_RECEIVE_GROUP_P)
679 LOG_TLU_OE_TRANS_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
680 r_tmp1, r_tmp2)
681 ba,a 2f
682 .empty
6831:
684 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
685 r_tmp2)
686 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
687 r_tmp1, r_tmp2, TLU_OE_RECEIVE_GROUP_P)
6882:
689 LOG_TLU_OE_RECV_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
690 r_tmp1, r_tmp2)
691 CLEAR_TLU_OE_RECV_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
692 r_tmp1, r_tmp2)
693 ba,a clear_pcie_err_fire_interrupt
694 .empty
695 .poplocals
696
697.tlu_receive_other_event_s:
698 PRINT("HV:tlu_receive_other_event_s\r\n")
699 set TLU_OE_RECEIVE_GROUP_P, r_tmp2
700 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
701 btst r_tmp2, r_tmp1
702 bz %xcc, .tlu_oe_dup_lli_s
703 nop
704 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
705 r_tmp2)
706 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
707 r_tmp1, r_tmp2, TLU_OE_RECEIVE_GROUP_P)
708 CLEAR_TLU_OE_RECV_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
709 r_tmp1, r_tmp2)
710 ba,a clear_pcie_err_fire_interrupt
711 .empty
712
713.tlu_oe_dup_lli_s:
714 PRINT("HV:tlu_oe_dup_lli_s\r\n")
715 /*
716 * these errors express themselves with possible duplicate bits
717 * in the LPU Link Layer Interrupt reg (0x6e2210, 0x7e2210)
718 */
719 set TLU_OE_DUP_LLI_P, r_tmp2
720 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
721 btst r_tmp2, r_tmp1
722 bz,pn %xcc, .pec_oe_processing_nothingtodo
723 nop
724 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
725 r_tmp2)
726 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
727 r_tmp1, r_tmp2, TLU_OE_DUP_LLI_P)
728 /*
729 * bits 9 through 4 are the dup bits, yet we do not send any
730 * info to the guest, so just clear them all. fma has received all
731 * the info
732 */
733 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(r_fire_e_rpt, \
734 r_fire_leaf_address, r_tmp1, r_tmp2)
735 CLEAR_TLU_OE_DUP_LLI_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
736 r_tmp1, r_tmp2)
737 ba,a clear_pcie_err_fire_interrupt
738 .empty
739
740.tlu_oe_link_interrupt_group_p:
741 PRINT("HV:.tlu_oe_link_interrupt_group_p\r\n")
742 PRINT("HV:r_tmp1 = 0x")
743 PRINTX(r_tmp1)
744 PRINT("\r\n")
745 set TLU_OE_LINK_INTERRUPT_GROUP_P, r_tmp2
746 btst r_tmp2, r_tmp1
747 bz %xcc, .tlu_trans_other_event_p
748 nop
749 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
750 r_tmp2)
751 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
752 r_tmp1, r_tmp2, TLU_OE_LINK_INTERRUPT_GROUP_P)
753
754 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_STATUS, r_tmp2
755 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
756 PRINT("HV:FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_INTERRUPT_STATUS\r\n")
757 PRINTX(r_tmp1)
758 PRINT("\r\n")
759 and r_tmp1, LPU_INT_STAT_INT_PERF_CNTR_2_OVFLW, r_tmp2
760 brnz,pn r_tmp2, .lpu_int_stat_int_perf_cntr_2_ovflw
761 nop
762 and r_tmp1, LPU_INT_STAT_INT_PERF_CNTR_1_OVFLW, r_tmp2
763 brnz,pn r_tmp2, .lpu_int_stat_int_perf_cntr_1_ovflw
764 nop
765 and r_tmp1, LPU_INT_STAT_INT_LINK_LAYER, r_tmp2
766 brnz,pn r_tmp2, .lpu_int_stat_int_link_layer
767 nop
768 and r_tmp1, LPU_INT_STAT_INT_PHY_ERROR, r_tmp2
769 brnz,pn r_tmp2, .lpu_int_stat_int_phy_error
770 nop
771 and r_tmp1, LPU_INT_STAT_INT_LTSSM, r_tmp2
772 brnz,pn r_tmp2, .lpu_int_stat_int_ltssm
773 nop
774 and r_tmp1, LPU_INT_STAT_INT_PHY_TX, r_tmp2
775 brnz,pn r_tmp2, .lpu_int_stat_int_phy_tx
776 nop
777 and r_tmp1, LPU_INT_STAT_INT_PHY_RX, r_tmp2
778 brnz,pn r_tmp2, .lpu_int_stat_int_phy_rx
779 nop
780 and r_tmp1, LPU_INT_STAT_INT_PHY_GB, r_tmp2
781 brnz,pt r_tmp2, .lpu_int_stat_int_phy_gb
782 nop
783
784.nothing_to_do_tlu_oe_link_interrupt_group_p:
785 PRINT("HV:.nothing_to_do_tlu_oe_link_interrupt_group_p\r\n")
786 ba,a .all_done_tlu_oe_link_interrupt_group_p
787 .empty
788
789.lpu_int_stat_int_perf_cntr_2_ovflw:
790 PRINT("HV:.lpu_int_stat_int_perf_cntr_2_ovflw\r\n")
791 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
792 LPU_INT_STAT_INT_PERF_CNTR_2_OVFLW, r_tmp1, r_tmp2)
793 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR2(r_fire_e_rpt, \
794 r_fire_leaf_address, r_tmp1, r_tmp2)
795 CLEAR_PERF_CNTR_2_OVFLW(r_fire_e_rpt, r_fire_leaf_address, \
796 r_tmp1, r_tmp2)
797 ba,a .all_done_tlu_oe_link_interrupt_group_p
798 .empty
799
800.lpu_int_stat_int_perf_cntr_1_ovflw:
801 PRINT("HV:.lpu_int_stat_int_perf_cntr_1_ovflw\r\n")
802 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
803 LPU_INT_STAT_INT_PERF_CNTR_1_OVFLW, r_tmp1, r_tmp2)
804 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LINK_PERF_CNTR1(r_fire_e_rpt, \
805 r_fire_leaf_address, r_tmp1, r_tmp2)
806 CLEAR_PERF_CNTR_1_OVFLW(r_fire_e_rpt, r_fire_leaf_address, \
807 r_tmp1, r_tmp2)
808 ba,a .all_done_tlu_oe_link_interrupt_group_p
809 .empty
810
811.lpu_int_stat_int_link_layer:
812 PRINT("HV:.lpu_int_stat_int_link_layer\r\n")
813 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
814 LPU_INT_STAT_INT_LINK_LAYER, r_tmp1, r_tmp2)
815 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(r_fire_e_rpt, \
816 r_fire_leaf_address, r_tmp1, r_tmp2)
817 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(r_fire_e_rpt, \
818 r_fire_leaf_address, r_tmp1, r_tmp2)
819 ba,a .all_done_tlu_oe_link_interrupt_group_p
820 .empty
821
822.lpu_int_stat_int_phy_error:
823 PRINT("HV:.lpu_int_stat_int_phy_error\r\n")
824 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
825 LPU_INT_STAT_INT_PHY_ERROR, r_tmp1, r_tmp2)
826 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT(r_fire_e_rpt, \
827 r_fire_leaf_address, r_tmp1, r_tmp2)
828 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_PHY_ERR_INT(r_fire_e_rpt, \
829 r_fire_leaf_address, r_tmp1, r_tmp2)
830 ba,a .all_done_tlu_oe_link_interrupt_group_p
831 .empty
832
833.lpu_int_stat_int_ltssm:
834 PRINT("HV:.lpu_int_stat_int_ltssm\r\n")
835 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
836 LPU_INT_STAT_INT_LTSSM, r_tmp1, r_tmp2)
837 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM(r_fire_e_rpt, \
838 r_fire_leaf_address, r_tmp1, r_tmp2)
839 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LTSSM(r_fire_e_rpt, \
840 r_fire_leaf_address, r_tmp1, r_tmp2)
841 ba,a .all_done_tlu_oe_link_interrupt_group_p
842 .empty
843
844.lpu_int_stat_int_phy_tx:
845 PRINT("HV:.lpu_int_stat_int_phy_tx\r\n")
846 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
847 LPU_INT_STAT_INT_PHY_TX, r_tmp1, r_tmp2)
848#ifdef DEBUG
849 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT, r_tmp2
850 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
851 PRINT("HV:LPU_INT_STAT_INT_PHY_TX\r\n")
852 PRINTX(r_tmp1)
853 PRINT("\r\n")
854#endif
855
856 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT(r_fire_e_rpt, \
857 r_fire_leaf_address, r_tmp1, r_tmp2)
858 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_TX_PHY_INT(r_fire_e_rpt, \
859 r_fire_leaf_address, r_tmp1, r_tmp2)
860 ba,a .all_done_tlu_oe_link_interrupt_group_p
861 .empty
862
863.lpu_int_stat_int_phy_rx:
864 PRINT("HV:.lpu_int_stat_int_phy_rx\r\n")
865 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
866 LPU_INT_STAT_INT_PHY_RX, r_tmp1, r_tmp2)
867 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT(r_fire_e_rpt, \
868 r_fire_leaf_address, r_tmp1, r_tmp2)
869 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_RX_PHY_INT(r_fire_e_rpt, \
870 r_fire_leaf_address, r_tmp1, r_tmp2)
871 ba,a .all_done_tlu_oe_link_interrupt_group_p
872 .empty
873
874.lpu_int_stat_int_phy_gb:
875 PRINT("HV:.lpu_int_stat_int_phy_gb\r\n")
876 LOG_PCIERPT_LPU_INTR_STATUS(r_fire_e_rpt, r_fire_leaf_address, \
877 LPU_INT_STAT_INT_PHY_GB, r_tmp1, r_tmp2)
878#ifdef DEBUG
879 set FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_GL_INT, r_tmp2
880 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
881 PRINT("HV:LPU_GB_STAT_INT_PHY_TX\r\n")
882 PRINTX(r_tmp1)
883 PRINT("\r\n")
884#endif
885 LOG_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT(r_fire_e_rpt, \
886 r_fire_leaf_address, r_tmp1, r_tmp2)
887 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_GB_PHY_INT(r_fire_e_rpt, \
888 r_fire_leaf_address, r_tmp1, r_tmp2)
889
890.all_done_tlu_oe_link_interrupt_group_p:
891 PRINT("HV:all_done_tlu_oe_link_interrupt_group_p\r\n")
892 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, r_tmp2
893 set TLU_OE_LINK_INTERRUPT_GROUP_P, r_tmp1
894 stx r_tmp1, [r_fire_leaf_address + r_tmp2]
895
896#ifdef DEBUG
897 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, r_tmp2
898 ldx [r_fire_leaf_address + r_tmp2], r_tmp1
899 PRINT("HV:FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS 0x")
900 PRINTX(r_tmp1)
901 PRINT("\r\n")
902#endif
903 ba,a clear_pcie_err_fire_interrupt
904 .empty
905
906.tlu_trans_other_event_p:
907 PRINT("HV:tlu_trans_other_event_p\r\n")
908 /*
909 * Bits 22:21, 17, 16, and 15
910 * this test must happen after the recieve other event test
911 * as both the transmit and recieve groups have overlap and
912 * post info to both trans and receive regs. Since we tested
913 * the overlap in the receive we won't need to test it here
914 * in theory the only bit we should see is the one that only
915 * posts to the trans reg
916 */
917 set TLU_OE_TRANS_GROUP_P, r_tmp2
918 btst r_tmp2, r_tmp1
919 bz %xcc, .tlu_oe_no_dup_group_p
920 nop
921 set TLU_OE_TRANS_SVVS_RPT_MSK, r_tmp2
922 btst r_tmp2, r_tmp1
923 .pushlocals
924 bz %xcc, 1f
925 nop
926 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
927 r_tmp2)
928 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
929 r_tmp1, r_tmp2, TLU_OE_TRANS_GROUP_P)
930 LOG_TLU_OE_TRANS_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
931 r_tmp1, r_tmp2)
932 LOG_TLU_OE_TRANS_GROUP_EPKT_P(r_fire_e_rpt, r_fire_leaf_address,\
933 r_tmp1, r_tmp2)
934 CLEAR_TLU_OE_TRANS_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
935 r_tmp1, r_tmp2)
936 ba,a pcie_err_mondo_ereport
937 .empty
9381:
939 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
940 r_tmp2)
941 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
942 r_tmp1, r_tmp2, TLU_OE_TRANS_GROUP_P)
943 LOG_TLU_OE_TRANS_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
944 r_tmp1, r_tmp2)
945 CLEAR_TLU_OE_TRANS_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
946 r_tmp1, r_tmp2)
947 ba,a clear_pcie_err_fire_interrupt
948 .empty
949 .poplocals
950
951.tlu_oe_no_dup_group_p:
952 PRINT("HV:tlu_oe_no_dup_group_p\r\n")
953 set TLU_OE_NO_DUP_GROUP_P, r_tmp2
954 btst r_tmp2, r_tmp1
955 bz,pn %xcc, .tlu_oe_dup_lli_p
956 nop
957 set TLU_OE_NO_DUP_SVVS_RPT_MSK, r_tmp2
958 btst r_tmp2, r_tmp1
959 .pushlocals
960 bz %xcc, 1f
961 nop
962 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
963 r_tmp2)
964 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
965 r_tmp1, r_tmp2, TLU_OE_NO_DUP_GROUP_P)
966 LOG_TLU_OE_NO_DUP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
967 r_tmp1, r_tmp2)
968 CLEAR_TLU_OE_NO_DUP_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
969 r_tmp1, r_tmp2)
970 ba,a pcie_err_mondo_ereport
971 .empty
9721:
973 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
974 r_tmp2)
975 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
976 r_tmp1, r_tmp2, TLU_OE_NO_DUP_GROUP_P)
977 CLEAR_TLU_OE_NO_DUP_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
978 r_tmp1, r_tmp2)
979 ba,a clear_pcie_err_fire_interrupt
980 .empty
981 .poplocals
982
983.tlu_oe_dup_lli_p:
984 PRINT("HV:tlu_oe_dup_lli_p\r\n")
985 /*
986 * these errors express themselves with possible duplicate bits
987 * in the LPU Link Layer Interrupt reg (0x6e2210, 0x7e2210)
988 */
989 set TLU_OE_DUP_LLI_P, r_tmp2
990 btst r_tmp2, r_tmp1
991 bz,pn %xcc, .tlu_oe_no_dup_group_s
992 nop
993 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
994 r_tmp2)
995 LOG_TLU_OE_INTR_STATUS_P(r_fire_e_rpt, r_fire_leaf_address, \
996 r_tmp1, r_tmp2, TLU_OE_DUP_LLI_P)
997 LOG_ILU_EPKT_P(r_fire_e_rpt, r_fire_leaf_address, r_tmp1, r_tmp2)
998 /*
999 * bits 9 through 4 are the dup bits, yet we do not send any
1000 * info to the guest, so just clear them all. fma has recieved all
1001 * the info
1002 */
1003 CLEAR_FIRE_PLC_TLU_CTB_LPR_PCIE_LPU_LL_ERR_INT(r_fire_e_rpt, \
1004 r_fire_leaf_address, r_tmp1, r_tmp2)
1005 CLEAR_TLU_OE_DUP_LLI_GROUP_P(r_fire_e_rpt, r_fire_leaf_address, \
1006 r_tmp1, r_tmp2)
1007 ba,a pcie_err_mondo_ereport
1008 .empty
1009
1010
1011.tlu_oe_no_dup_group_s:
1012 PRINT("HV:tlu_oe_no_dup_group_s\r\n")
1013 set TLU_OE_NO_DUP_GROUP_P, r_tmp2
1014 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1015 btst r_tmp2, r_tmp1
1016 bz,pn %xcc, .tlu_trans_other_event_s
1017 nop
1018 set TLU_OE_NO_DUP_SVVS_RPT_MSK, r_tmp2
1019 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1020 btst r_tmp2, r_tmp1
1021 .pushlocals
1022 bz %xcc, 1f
1023 nop
1024 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
1025 r_tmp1, r_tmp2)
1026 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
1027 r_tmp1, r_tmp2, TLU_OE_NO_DUP_GROUP_P)
1028 LOG_TLU_OE_NO_DUP_EPKT_P_S(r_fire_e_rpt, r_fire_leaf_address, \
1029 r_tmp1, r_tmp2)
1030 CLEAR_TLU_OE_NO_DUP_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
1031 r_tmp1, r_tmp2)
1032 ba,a pcie_err_mondo_ereport
1033 .empty
10341:
1035 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
1036 r_tmp1, r_tmp2)
1037 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
1038 r_tmp1, r_tmp2, TLU_OE_NO_DUP_GROUP_P)
1039 CLEAR_TLU_OE_NO_DUP_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
1040 r_tmp1, r_tmp2)
1041 ba,a clear_pcie_err_fire_interrupt
1042 .empty
1043 .poplocals
1044
1045.tlu_trans_other_event_s:
1046 PRINT("HV:tlu_trans_other_event_s\r\n")
1047 set TLU_OE_TRANS_GROUP_P, r_tmp2
1048 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1049 btst r_tmp2, r_tmp1
1050 bz,pn %xcc, .tlu_oe_link_interrupt_group_s
1051 nop
1052 set TLU_OE_TRANS_SVVS_RPT_MSK, r_tmp2
1053 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1054 btst r_tmp2, r_tmp1
1055 .pushlocals
1056 bz %xcc, 1f
1057 nop
1058 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
1059 r_tmp2)
1060 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
1061 r_tmp2, TLU_OE_TRANS_GROUP_P)
1062 LOG_TLU_OE_TRANS_GROUP_EPKT_S(r_fire_e_rpt, r_fire_leaf_address,\
1063 r_tmp1, r_tmp2)
1064 CLEAR_TLU_OE_TRANS_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
1065 r_tmp1, r_tmp2)
1066 ba,a pcie_err_mondo_ereport
1067 .empty
1068
10691:
1070 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, \
1071 r_tmp1, r_tmp2)
1072 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
1073 r_tmp1, r_tmp2, TLU_OE_TRANS_GROUP_P)
1074 CLEAR_TLU_OE_TRANS_GROUP_S(r_fire_e_rpt, r_fire_leaf_address, \
1075 r_tmp1, r_tmp2)
1076 ba,a clear_pcie_err_fire_interrupt
1077 .empty
1078 .poplocals
1079
1080.tlu_oe_link_interrupt_group_s:
1081 PRINT("HV:tlu_oe_link_interrupt_group_s\r\n")
1082 set TLU_OE_LINK_INTERRUPT_GROUP_P, r_tmp2
1083 sllx r_tmp2, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp2
1084 btst r_tmp2, r_tmp1
1085 bz %xcc, .tlu_receive_other_event_s
1086 nop
1087 LOG_TLU_OE_GROUP_REGS(r_fire_e_rpt, r_fire_leaf_address, r_tmp1,\
1088 r_tmp2)
1089 LOG_TLU_OE_INTR_STATUS_S(r_fire_e_rpt, r_fire_leaf_address, \
1090 r_tmp1, r_tmp2, TLU_OE_LINK_INTERRUPT_GROUP_P)
1091
1092 set FIRE_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS, r_tmp2
1093 set TLU_OE_LINK_INTERRUPT_GROUP_P, r_tmp1
1094 sllx r_tmp1, PRIMARY_TO_SECONDARY_SHIFT_SZ, r_tmp1
1095 stx r_tmp1, [r_fire_leaf_address + r_tmp2]
1096
1097 ba,a clear_pcie_err_fire_interrupt
1098 .empty
1099
1100
1101pcie_err_mondo_ereport:
1102 PCIE_ERR_MONDO_EREPORT(r_fire_cookie, r_fire_e_rpt, r_tmp1, r_tmp2)
1103clear_pcie_err_fire_interrupt:
1104 CLEAR_FIRE_INTERRUPT(r_fire_cookie, PCIE_ERR_INO, r_tmp1)
1105 GENERATE_FMA_REPORT; /* never returns */
1106
1107jbc_err_mondo_ereport:
1108 JBC_ERR_MONDO_EREPORT(r_fire_cookie, r_fire_e_rpt, r_tmp1, r_tmp2)
1109clear_jbc_err_fire_interrupt:
1110 CLEAR_FIRE_INTERRUPT(r_fire_cookie, JBC_ERR_INO, r_tmp1)
1111 GENERATE_FMA_REPORT; /* never returns */
1112
1113.pec_oe_processing_nothingtodo:
1114 PRINT("HV:pec_oe_processing_nothingtodo\r\n")
1115 ba,a clear_pcie_err_fire_interrupt
1116 .empty
1117
1118 SET_SIZE(error_mondo_62)
1119
1120 !! %g1 = Fire Cookie
1121 !! %g2 = Mondo DATA0
1122 !! %g3 = IGN
1123 !! %g4 = INO
1124 ENTRY_NP(error_mondo_63)
1125 PRINT("HV:mondo 63\r\n")
1126 mov %g2, %g7 ! save DATA0 for err handle setup
1127 !!
1128 !! Generate a unique error handle
1129 !! enters with:
1130 !! %g1 loaded with fire cookie
1131 !! %g2 data0, overwritten with r_fire_e_rpt
1132 !! %g3 IGN
1133 !! %g4 INO
1134 !! %g5 scratch
1135 !! %g6 scratch
1136 !! %g7 data0
1137 !!
1138 !! returns with:
1139 !! %g1 r_fire_cookie
1140 !! %g2 pointing to r_fire_e_rpt
1141 !!
1142 GEN_ERR_HNDL_SETUP_ERPTS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
1143
1144#define r_jbc_intr_status %g3
1145#define r_jbus_base_addr %g4
1146
1147 ldx [r_fire_cookie + FIRE_COOKIE_JBUS], r_jbus_base_addr
1148 set FIRE_JBC_ERROR_LOG_EN_REG, r_tmp1 /* 0x471000 */
1149 ldx [r_jbus_base_addr + r_tmp1], r_tmp2
1150 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_ERR_LOG_ENABLE]
1151
1152 /* 0x471020 */
1153 set FIRE_JBC_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS, r_tmp1
1154 ldx [r_jbus_base_addr + r_tmp1], r_tmp2
1155 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_ERROR_STATUS_SET_REG]
1156
1157 set FIRE_JBC_ERROR_INT_EN_REG, r_tmp1 /* 0x471008 */
1158 ldx [r_jbus_base_addr + r_tmp1], r_tmp2
1159 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_ENABLE]
1160
1161 set FIRE_JBC_ENABLED_ERROR_STATUS_REG, r_tmp1 /* 0x471010 */
1162 ldx [r_jbus_base_addr + r_tmp1], r_jbc_intr_status
1163 /* %g3 has the individual interrupt bits */
1164
1165 setx JBC_FATAL_GROUP, r_tmp2, r_tmp1
1166 btst r_jbc_intr_status, r_tmp1
1167 bnz %xcc, fatal_errors
1168 .empty
1169
1170 set FIRE_JBC_INTERRUPT_STATUS_REG, r_tmp1 /* 0x471808 */
1171 add r_jbus_base_addr, r_tmp1, r_tmp1
1172 ldx [r_tmp1], r_tmp2
1173
1174 set DMCINT_BIT, r_tmp1 ! Mask for dmcint type errors
1175 btst r_tmp2, r_tmp1
1176 bnz %xcc, dmcint_errors
1177 stx r_tmp1, [r_fire_e_rpt + PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS]
1178
1179 set JBCINT_BIT, r_tmp1
1180 btst r_tmp2, r_tmp1
1181 bnz %xcc, jbcint_errors
1182 stx r_tmp1, [r_fire_e_rpt + PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS]
1183
1184 set MERGE_BIT, r_tmp1
1185 btst r_tmp2, r_tmp1
1186 bnz %xcc, merge_errors
1187 stx r_tmp1, [r_fire_e_rpt + PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS]
1188
1189 set CSR_BIT, r_tmp1
1190 btst r_tmp2, r_tmp1
1191 bnz %xcc, csr_errors
1192 stx r_tmp1, [r_fire_e_rpt + PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS]
1193
1194 ! Should not get here
1195 PRINT("HV:Fall through on top level mondo 63 processing\r\n")
1196 ba,a clear_jbc_err_fire_interrupt
1197 .empty
1198
1199fatal_errors:
1200 PRINT("HV:fatal_errors:\r\n")
1201 set JBC_FATAL_LOGING_GROUP, r_tmp1
1202 btst r_tmp2, r_tmp1
1203 .pushlocals
1204 bz %xcc, 1f
1205 and r_tmp2, r_tmp1, r_tmp2
1206 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_CORE_AND_BLOCK_ERR_STATUS]
1207 LOG_JBUS_FATAL_REGS(r_fire_e_rpt, r_jbus_base_addr, r_tmp1, r_tmp2)
1208 CLEAR_JBUS_FATAL_REGS(r_fire_e_rpt, r_jbus_base_addr, r_tmp1, r_tmp2)
1209 ba,a clear_jbc_err_fire_interrupt
1210 .empty
12111:
1212 CLEAR_JBUS_FATAL_REGS(r_fire_e_rpt, r_jbus_base_addr, r_tmp1, r_tmp2)
1213 ba,a clear_jbc_err_fire_interrupt
1214 .empty
1215 .poplocals
1216
1217dmcint_errors:
1218.dmcint.odc_p:
1219 PRINT("HV:.dmcint.odc_p:\r\n")
1220 PRINT("HV:setting reg to bits DMCINT_ODC_GROUP_P:0x")
1221 setx DMCINT_ODC_GROUP_P, r_tmp2, r_tmp1
1222 PRINTX(r_tmp1)
1223 PRINT("\r\n")
1224 PRINT("HV:r_jbc_intr_status:0x")
1225 PRINTX(r_jbc_intr_status)
1226 PRINT("\r\n")
1227 btst r_jbc_intr_status, r_tmp1
1228 bz %xcc, .dmcint.idc_p
1229 and r_tmp1, r_jbc_intr_status, r_tmp2
1230 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1231 LOG_DMCINT_ODC_REGS(r_fire_e_rpt, r_jbus_base_addr, \
1232 r_tmp1, r_tmp2)
1233 CLEAR_DMCINT_ODC_P(r_fire_e_rpt, r_jbus_base_addr, \
1234 r_tmp1, r_tmp2)
1235 set DMCINT_ODC_SVVS_RPT_MSK, r_tmp1
1236 btst r_jbc_intr_status, r_tmp1
1237 .pushlocals
1238 bnz %xcc, 1f
1239 nop
1240 ba,a clear_jbc_err_fire_interrupt
1241 .empty
12421:
1243 .poplocals
1244 LOG_DMCINT_ODC_EPKT_P(r_fire_e_rpt, r_jbus_base_addr, \
1245 r_jbc_intr_status, r_tmp1, r_tmp2)
1246 ba,a jbc_err_mondo_ereport
1247 .empty
1248
1249.dmcint.idc_p:
1250 PRINT("HV:dmcint.idc_p:\r\n")
1251 set DMCINT_IDC_GROUP_P, r_tmp1
1252 btst r_jbc_intr_status, r_tmp1
1253 bz %xcc, .dmcint.idc_s
1254 and r_jbc_intr_status, DMCINT_IDC_GROUP_P, r_tmp2
1255 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1256 LOG_DMCINT_IDC_REGS(r_fire_e_rpt, r_jbus_base_addr, \
1257 r_tmp1, r_tmp2)
1258 CLEAR_DMCINT_IDC_P(r_fire_e_rpt, r_jbus_base_addr, \
1259 r_jbc_intr_status, r_tmp1, r_tmp2)
1260 /* no guest reports from this group */
1261 ba,a clear_jbc_err_fire_interrupt
1262 .empty
1263
1264.dmcint.idc_s:
1265 PRINT("HV:dmcint.idc_s:\r\n")
1266 setx DMCINT_IDC_GROUP_S, r_tmp2, r_tmp1
1267 btst r_jbc_intr_status, r_tmp1
1268 bz %xcc, .dmcint.odc_s
1269 and r_jbc_intr_status, r_tmp1, r_tmp2
1270 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1271 CLEAR_DMCINT_IDC_S(r_fire_e_rpt, r_jbus_base_addr, \
1272 r_jbc_intr_status, r_tmp1, r_tmp2)
1273 ba,a clear_jbc_err_fire_interrupt
1274 .empty
1275
1276.dmcint.odc_s:
1277 PRINT("HV:dmcint.odc_s:\r\n")
1278 setx DMCINT_ODC_GROUP_S, r_tmp2, r_tmp1
1279 btst r_jbc_intr_status, r_tmp1
1280 bz,pn %xcc, .dmcint_nothingtodo
1281 and r_jbc_intr_status, r_tmp1, r_tmp2
1282 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1283 CLEAR_DMCINT_ODC_S(r_fire_e_rpt, r_jbus_base_addr, \
1284 r_jbc_intr_status, r_tmp1, r_tmp2)
1285 ba,a clear_jbc_err_fire_interrupt
1286 .empty
1287
1288.dmcint_nothingtodo:
1289 PRINT("HV:dmcint_nothingtodo:\r\n")
1290 ba,a clear_jbc_err_fire_interrupt
1291 .empty
1292
1293jbcint_errors:
1294.jbcint_in_p:
1295 PRINT("HV:jbcint_in_p:\r\n")
1296 .pushlocals
1297 set JBUSINT_IN_GROUP_P, r_tmp1
1298 btst r_jbc_intr_status, r_tmp1
1299 bz %xcc, .jbcint_out_p
1300 and r_jbc_intr_status, r_tmp1, r_tmp2
1301 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1302 LOG_JBCINT_IN_REGS(r_fire_e_rpt, r_jbus_base_addr, \
1303 r_tmp1, r_tmp2)
1304 CLEAR_JBCINT_IN_P(r_fire_e_rpt, r_jbus_base_addr, \
1305 r_jbc_intr_status, r_tmp1, r_tmp2)
1306 PRINT("HV:r_jbc_intr_status:0x")
1307 PRINTX(r_jbc_intr_status)
1308 PRINT("\r\n")
1309 set JBUSINT_IN_SVVS_RPT_MSK, r_tmp1
1310 btst r_jbc_intr_status, r_tmp1
1311 bnz %xcc, 1f
1312 nop
1313 PRINT("HV:no guest report for jbcint_in_p\r\n")
1314 ba,a clear_jbc_err_fire_interrupt
1315 .empty
13161:
1317 LOG_JBCINT_IN_EPKT_P(r_fire_e_rpt, r_jbus_base_addr, \
1318 r_jbc_intr_status, r_tmp1, r_tmp2)
1319 ba,a jbc_err_mondo_ereport
1320 .empty
1321 .poplocals
1322
1323.jbcint_out_p:
1324 PRINT("HV:jbcint_out_p:\r\n")
1325 .pushlocals
1326 set JBUSINT_OUT_GROUP_P, r_tmp1
1327 btst r_jbc_intr_status, r_tmp1
1328 bz %xcc, .jbcint_in_s
1329 and r_jbc_intr_status, r_tmp1, r_tmp2
1330 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1331 LOG_JBCINT_OUT_REGS(r_fire_e_rpt, r_jbus_base_addr, \
1332 r_tmp1, r_tmp2)
1333 CLEAR_JBCINT_OUT_P(r_fire_e_rpt, r_jbus_base_addr, \
1334 r_jbc_intr_status, r_tmp1, r_tmp2)
1335 /* no guest report ever for this group */
1336 set JBUSINT_OUT_SVVS_RPT_MSK, r_tmp1
1337 btst r_jbc_intr_status, r_tmp1
1338 bnz %xcc, 1f
1339 nop
1340 ba,a clear_jbc_err_fire_interrupt
1341 .empty
13421:
1343 LOG_JBCINT_OUT_EPKT_P(r_fire_e_rpt, r_jbus_base_addr, \
1344 r_jbc_intr_status, r_tmp1, r_tmp2)
1345 ba,a jbc_err_mondo_ereport
1346 .empty
1347 .poplocals
1348
1349.jbcint_in_s:
1350 PRINT("HV:jbcint_in_s:\r\n")
1351 setx JBUSINT_IN_GROUP_S, r_tmp2, r_tmp1
1352 btst r_jbc_intr_status, r_tmp1
1353 bz %xcc, .jbcint_out_s
1354 and r_jbc_intr_status, r_tmp1, r_tmp2
1355 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1356 CLEAR_JBCINT_IN_S(r_fire_e_rpt, r_jbus_base_addr, \
1357 r_jbc_intr_status, r_tmp1, r_tmp2)
1358 ba,a clear_jbc_err_fire_interrupt
1359 .empty
1360
1361.jbcint_out_s:
1362 PRINT("HV:jbcint_out_s:\r\n")
1363 setx JBUSINT_OUT_GROUP_S, r_tmp2, r_tmp1
1364 btst r_jbc_intr_status, r_tmp1
1365 bz,pn %xcc, .jbcint_nothingtodo
1366 and r_jbc_intr_status, r_tmp1, r_tmp2
1367 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1368 CLEAR_JBCINT_OUT_S(r_fire_e_rpt, r_jbus_base_addr, \
1369 r_jbc_intr_status, r_tmp1, r_tmp2)
1370 ba,a clear_jbc_err_fire_interrupt
1371 .empty
1372
1373.jbcint_nothingtodo:
1374 PRINT("HV:jbcint_nothingtodo:\r\n")
1375 ba,a clear_jbc_err_fire_interrupt
1376 .empty
1377
1378merge_errors:
1379.merge_errors_p:
1380 PRINT("HV:merge_errors_p::\r\n")
1381 .pushlocals
1382 set MERGE_GROUP_P, r_tmp1
1383 btst r_jbc_intr_status, r_tmp1
1384 bz %xcc, .merge_errors_s
1385 and r_jbc_intr_status, r_tmp1, r_tmp2
1386 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1387 LOG_MERGE_REGS(r_fire_e_rpt, r_jbus_base_addr, r_tmp1, r_tmp2)
1388 CLEAR_MERGE_P(r_fire_e_rpt, r_jbus_base_addr, r_jbc_intr_status,\
1389 r_tmp1, r_tmp2)
1390 set MERGE_SVVS_RPT_MSK, r_tmp1
1391 btst r_jbc_intr_status, r_tmp1
1392 bnz %xcc, 1f
1393 nop
1394 ba,a clear_jbc_err_fire_interrupt
1395 .empty
13961:
1397 LOG_MERGE_ERROR_EPKT_P(r_fire_e_rpt, r_jbus_base_addr, \
1398 r_jbc_intr_status, r_tmp1, r_tmp2)
1399 ba,a jbc_err_mondo_ereport
1400 .empty
1401 .poplocals
1402
1403.merge_errors_s:
1404 PRINT("HV:merge_errors_s:\r\n")
1405 setx MERGE_GROUP_S, r_tmp2, r_tmp1
1406 btst r_jbc_intr_status, r_tmp1
1407 bz,pn %xcc, .merge_errors_nothingtodo
1408 and r_jbc_intr_status, r_tmp1, r_tmp2
1409 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1410 CLEAR_MERGE_S(r_fire_e_rpt, r_jbus_base_addr, r_jbc_intr_status,\
1411 r_tmp1, r_tmp2)
1412 ba,a clear_jbc_err_fire_interrupt
1413 .empty
1414
1415.merge_errors_nothingtodo:
1416 PRINT("HV:merge_errors_nothingtodo:\r\n")
1417 ba,a clear_jbc_err_fire_interrupt
1418 .empty
1419
1420
1421csr_errors:
1422.csr_errors_p:
1423 PRINT("HV:csr_errors_p:\r\n")
1424 .pushlocals
1425 set CSR_GROUP_P, r_tmp1
1426 btst r_jbc_intr_status, r_tmp1
1427 bz %xcc, .csr_errors_s
1428 and r_jbc_intr_status, r_tmp1, r_tmp2
1429 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1430 LOG_CSR_REGS(r_fire_e_rpt, r_jbus_base_addr, r_tmp1, r_tmp2)
1431 CLEAR_CSR_P(r_fire_e_rpt, r_jbus_base_addr, r_jbc_intr_status, \
1432 r_tmp1, r_tmp2)
1433 set CSR_SVVS_RPT_MSK, r_tmp1
1434 btst r_jbc_intr_status, r_tmp1
1435 bnz %xcc, 1f
1436 nop
1437 ba,a clear_jbc_err_fire_interrupt
1438 .empty
14391:
1440 LOG_CSR_ERRORS_P_EPKT_P(r_fire_e_rpt, r_jbus_base_addr, \
1441 r_jbc_intr_status, r_tmp1, r_tmp2)
1442 ba,a jbc_err_mondo_ereport
1443 .empty
1444 .poplocals
1445
1446.csr_errors_s:
1447 PRINT("HV:csr_errors_s:\r\n")
1448 setx CSR_GROUP_S, r_tmp2, r_tmp1
1449 btst r_jbc_intr_status, r_tmp1
1450 bz,pn %xcc, .csr_errors_nothingtodo
1451 .empty
1452 and r_jbc_intr_status, r_tmp1, r_tmp2
1453 stx r_tmp2, [r_fire_e_rpt + PCIERPT_JBC_INTR_STATUS]
1454 CLEAR_CSR_S(r_fire_e_rpt, r_jbus_base_addr, r_jbc_intr_status, \
1455 r_tmp1, r_tmp2)
1456 ba,a clear_jbc_err_fire_interrupt
1457 .empty
1458
1459.csr_errors_nothingtodo:
1460 PRINT("HV:csr_errors_nothingtodo:\r\n")
1461 ba,a clear_jbc_err_fire_interrupt
1462 .empty
1463
1464 SET_SIZE(error_mondo_63)
1465
1466
1467/*
1468 * %g2 pointing to ereport buffer, i.e. r_fire_e_rpt
1469 * so jbus is special, sometimes we need to send ereports
1470 * to both leafs since we don't really know which leaf
1471 * generated the error. We do this here, by xor'ing bit
1472 * 7 of word 0 before we send it then call generate_guest_report
1473 */
1474 ENTRY_NP(generate_guest_report_special)
1475
1476 /*
1477 * this error code is completely unintelligible ...
1478 * hopefully this register usage is OK but who can tell ???
1479 *
1480 * The PA has been inserted into the PCI error packet, now
1481 * translate to a RA
1482 */
1483 ldx [r_fire_e_rpt + PCIERPT_ERROR_PADDR], r_tmp2
1484 RADDR_IS_IO_XCCNEG(r_tmp2, r_tmp1)
1485 bneg %xcc, .generate_guest_report_special_ra2pa_done ! do nothing
1486 nop
1487
1488 GUEST_STRUCT(r_tmp1)
1489 PA2RA_CONV(r_tmp1, r_tmp2, %g6, %g3, %g4)
1490 ! %g6 RADDR
1491 stx %g6, [r_fire_e_rpt + PCIERPT_ERROR_RADDR]
1492
1493.generate_guest_report_special_ra2pa_done:
1494
1495 /*
1496 * Is other leaf on?
1497 */
1498 PRINT("HV:Is other leaf is on?\r\n")
1499 ldx [r_fire_e_rpt + PCIERPT_SYSINO], r_tmp1 ! PCIERPT_SYSINO
1500 srlx r_tmp1, FIRE_DEVINO_SHIFT, r_tmp1
1501 and r_tmp1, FIRE_LEAF_DEVID_MASK, r_tmp1 ! devid 0 or 1
1502 btog 1, r_tmp1 ! make it other dev id
1503 ldx [r_fire_cookie + FIRE_COOKIE_VIRTUAL_INTMAP], r_tmp2
1504 ldub [r_tmp2 + r_tmp1], r_tmp2
1505 brz r_tmp2, generate_guest_report ! if off don't send a ereport
1506 ! for other leaf
1507 nop
1508 PRINT("HV:other leaf is on!\r\n")
1509 CPU_PUSH(r_fire_cookie, r_tmp1, r_tmp2, %g6)
1510 CPU_PUSH(r_fire_e_rpt, r_tmp1, r_tmp2, %g6)
1511 add r_fire_e_rpt, PCIERPT_SYSINO, %g1
1512 /*
1513 * fixup mondo to report other leaf
1514 */
1515 ldx [%g1], %g3
1516 btog 0x40, %g3 ! flip bit 7
1517 stx %g3, [%g1]
1518 STRAND_PUSH(%g1, r_tmp1, r_tmp2)
1519 HVCALL(insert_device_mondo_p)
1520 STRAND_POP(%g1, r_tmp1)
1521 PRINT("HV:calling:generate_guest_report\r\n")
1522
1523 /*
1524 * fixup mondo to report current leaf
1525 */
1526 ldx [%g1], %g3
1527 btog 0x40, %g3 ! flip bit 7
1528 stx %g3, [%g1]
1529
1530 CPU_POP(r_fire_e_rpt, r_tmp1, r_tmp2, %g6)
1531 CPU_POP(r_fire_cookie, r_tmp1, r_tmp2, %g6)
1532
1533 PRINT("HV:Is this leaf on?\r\n")
1534 ldx [r_fire_e_rpt + PCIERPT_SYSINO], r_tmp1 ! PCIERPT_SYSINO
1535 srlx r_tmp1, FIRE_DEVINO_SHIFT, r_tmp1
1536 and r_tmp1, FIRE_LEAF_DEVID_MASK, r_tmp1 ! devid 0 or 1
1537 ldx [r_fire_cookie + FIRE_COOKIE_VIRTUAL_INTMAP], r_tmp2
1538 ldub [r_tmp2 + r_tmp1], r_tmp2
1539 brnz r_tmp2, generate_guest_report ! It's on send it
1540 nop
1541 /*
1542 * This one is off, but this one took the interrupt
1543 * so we must clear the interrupt ourselves
1544 */
1545 ba,a clear_jbc_err_fire_interrupt
1546 .empty
1547 SET_SIZE(generate_guest_report_special)
1548
1549/*
1550 * %g2 pointing to ereport buffer, i.e. r_fire_e_rpt
1551 */
1552 ENTRY_NP(generate_guest_report)
1553 add r_fire_e_rpt, PCIERPT_SYSINO, %g1
1554#ifdef DEBUG
1555 PRINT("HV:generate_guest_report\r\n")
1556 PRINT("\r\n")
1557 ldx [%g1 + 0x00], %g3
1558 PRINT("HV:word0:0x")
1559 PRINTX(%g3)
1560 PRINT("\r\n")
1561 ldx [%g1 + 0x08], %g3
1562 PRINT("HV:word1:0x")
1563 PRINTX(%g3)
1564 PRINT("\r\n")
1565 ldx [%g1 + 0x10], %g3
1566 PRINT("HV:word2:0x")
1567 PRINTX(%g3)
1568 PRINT("\r\n")
1569 ldx [%g1 + 0x18], %g3
1570 PRINT("HV:word3:0x")
1571 PRINTX(%g3)
1572 PRINT("\r\n")
1573 ldx [%g1 + 0x20], %g3
1574 PRINT("HV:word4:0x")
1575 PRINTX(%g3)
1576 PRINT("\r\n")
1577 ldx [%g1 + 0x28], %g3
1578 PRINT("HV:word5:0x")
1579 PRINTX(%g3)
1580 PRINT("\r\n")
1581 ldx [%g1 + 0x30], %g3
1582 PRINT("HV:word6:0x")
1583 PRINTX(%g3)
1584 PRINT("\r\n")
1585 ldx [%g1 + 0x38], %g3
1586 PRINT("HV:word7:0x")
1587 PRINTX(%g3)
1588 PRINT("\r\n")
1589 PRINT("HV:calling:insert_device_mondo_p\r\n")
1590#endif
1591 STRAND_PUSH(r_fire_e_rpt, r_tmp1, r_tmp2)
1592 HVCALL(insert_device_mondo_p)
1593 STRAND_POP(r_fire_e_rpt, r_tmp1)
1594 mov r_fire_e_rpt, %g1
1595 PRINT("HV:calling:generate_fma_report\r\n")
1596 /*
1597 * %g1 r_fire_e_rpt
1598 */
1599 ba,a generate_fma_report
1600 .empty
1601 SET_SIZE(generate_guest_report)
1602/*
1603 * %g1 pointing to fire error buffer
1604 */
1605 ENTRY_NP(generate_fma_report)
1606
1607 ! set %g2 to point to unsent flag
1608 add %g1, PCI_UNSENT_PKT, %g2
1609
1610 ! set %g1 to point to vbsc err report
1611 add %g1, PCI_ERPT_U, %g1
1612
1613 ! set %g3 to contain the size of the buf
1614 mov PCIERPT_SIZE - EPKTSIZE, %g3
1615
1616 HVCALL(send_diag_erpt)
1617
1618 PRINT("HV:all done with fire error processing, fma report sent\r\n")
1619 retry
1620 SET_SIZE(generate_fma_report)
1621
1622!!
1623!! fire_err_mondo_receive
1624!!
1625!! %g1 = Fire Cookie
1626!! %g2 = Mondo DATA0
1627!! %g3 = IGN
1628!! %g4 = INO
1629!!
1630 ENTRY_NP(fire_err_mondo_receive)
1631 /*
1632 * is it mondo 62 or 63
1633 */
1634 cmp %g4, JBC_ERR_INO ! 63
1635 beq,pt %xcc, error_mondo_63
1636 cmp %g4, PCIE_ERR_INO ! 62
1637 beq,pt %xcc, error_mondo_62
1638 nop
1639 ba insert_device_mondo_r
1640 rd %pc, %g7
1641 retry
1642 SET_SIZE(fire_err_mondo_receive)
1643
1644!!
1645!! fire_err_intr_getvalid
1646!!
1647!! %g1 Fire Cookie Pointer
1648!! arg0 Virtual INO (%o0)
1649!! --
1650!! ret0 status (%o0)
1651!! ret1 intr valid state (%o1)
1652!!
1653 ENTRY_NP(fire_err_intr_getvalid)
1654 and %o0, FIRE_DEVINO_MASK, %g2
1655 cmp %g2, JBC_ERR_INO ! is it mondo 63
1656 mov JBC_ERR_MONDO_OFFSET, %g4
1657 movne %xcc, PCIE_ERR_MONDO_OFFSET, %g4
1658 srlx %o0, FIRE_DEVINO_SHIFT, %g2
1659 and %g2, FIRE_LEAF_DEVID_MASK, %g2 ! devid 0 or 1
1660 ldx [%g1 + FIRE_COOKIE_VIRTUAL_INTMAP], %g6
1661 add %g6, %g4, %g6 ! JBC or PCIE offset
1662 ldub [%g6 + %g2], %g6
1663 mov INTR_DISABLED, %o1
1664 movrz %g6, INTR_ENABLED, %o1
1665 HCALL_RET(EOK)
1666 SET_SIZE(fire_err_intr_getvalid)
1667
1668!!
1669!! fire_err_intr_setvalid
1670!!
1671!! %g1 Fire Cookie Pointer
1672!! arg0 Virtual INO (%o0)
1673!! arg1 intr valid state (%o1) 1: Valid 0: Invalid
1674!! --
1675!! ret0 status (%o0)
1676!!
1677
1678 ENTRY_NP(fire_err_intr_setvalid)
1679 mov %o0, %g2
1680 mov %o1, %g3
1681 HVCALL(_fire_err_intr_setvalid)
1682
1683 ! _fire_err_intr_setvalid doesn't have any failure cases
1684 ! so it is safe to just return EOK
1685 HCALL_RET(EOK)
1686 SET_SIZE(fire_err_intr_setvalid)
1687
1688!!
1689!! _fire_err_intr_setvalid
1690!! %g1 Fire Cookie Pointer
1691!! %g2 device ino
1692!! %g3 Valid/Invalid
1693!!
1694 ENTRY_NP(_fire_err_intr_setvalid)
1695 and %g2, FIRE_DEVINO_MASK, %g5
1696 cmp %g5, JBC_ERR_INO ! is it mondo 63
1697 mov JBC_ERR_MONDO_OFFSET, %g4
1698 movne %xcc, PCIE_ERR_MONDO_OFFSET, %g4
1699 ldx [%g1 + FIRE_COOKIE_VIRTUAL_INTMAP], %g6
1700 srlx %g2, FIRE_DEVINO_SHIFT, %g5
1701 and %g5, FIRE_LEAF_DEVID_MASK, %g5 ! devid 0 or 1
1702 add %g6, %g4, %g6 ! virtual intmap + mondo offset
1703 stb %g3, [%g6 + %g5]
1704
1705 HVRET
1706 SET_SIZE(_fire_err_intr_setvalid)
1707
1708!!
1709!! fire_err_intr_getstate
1710!!
1711!! %g1 Fire Cookie Pointer
1712!! arg0 Virtual INO (%o0)
1713!! --
1714!! ret0 status (%o0)
1715!! ret1 (%o1) 1: Pending / 0: Idle
1716!!
1717 ENTRY_NP(fire_err_intr_getstate)
1718 ba,a fire_intr_getstate
1719 .empty
1720 SET_SIZE(fire_err_intr_getstate)
1721
1722!!
1723!! fire_err_intr_setstate
1724!!
1725!! %g1 Fire Cookie Pointer
1726!! arg0 Virtual INO (%o0)
1727!! arg1 (%o1) 1: Pending / 0: Idle
1728!! --
1729!! ret0 status (%o0)
1730!!
1731 ENTRY_NP(fire_err_intr_setstate)
1732 ba,a fire_intr_setstate
1733 .empty
1734 SET_SIZE(fire_err_intr_setstate)
1735
1736!!
1737!! fire_err_intr_gettarget
1738!!
1739!! %g1 Fire Cookie Pointer
1740!! arg0 Virtual INO (%o0)
1741!! --
1742!! ret0 status (%o0)
1743!! ret1 cpuid (%o1)
1744!!
1745 ENTRY_NP(fire_err_intr_gettarget)
1746 ba,a fire_intr_gettarget
1747 .empty
1748 SET_SIZE(fire_err_intr_gettarget)
1749
1750!!
1751!! fire_err_intr_settarget
1752!!
1753!! %g1 Fire Cookie Pointer
1754!! arg0 Virtual INO (%o0)
1755!! arg1 cpuid (%o1)
1756!! --
1757!! ret0 status (%o0)
1758!!
1759 ENTRY_NP(fire_err_intr_settarget)
1760 ba,a fire_intr_settarget
1761 .empty
1762 SET_SIZE(fire_err_intr_settarget)
1763
1764
1765!!
1766!! fire_err_intr_redistribution
1767!! %g1 - this cpu
1768!! %g2 - tgt cpu
1769!!
1770!! Generates each INO and calls the function that actually
1771!! does the work
1772!!
1773 ENTRY_NP(fire_err_intr_redistribution)
1774 CPU_PUSH(%g7, %g3, %g4, %g5)
1775
1776 mov %g2, %g1
1777 CPU_PUSH(%g1, %g3, %g4, %g5)
1778 mov FIRE_A_AID << FIRE_DEVINO_SHIFT, %g4
1779 or %g4, JBC_ERR_INO, %g3
1780 HVCALL(_fire_err_intr_redistribution)
1781
1782 CPU_POP(%g1, %g3, %g4, %g5)
1783 CPU_PUSH(%g1, %g3, %g4, %g5)
1784 mov FIRE_A_AID << FIRE_DEVINO_SHIFT, %g4
1785 or %g4, PCIE_ERR_INO, %g3
1786 HVCALL(_fire_err_intr_redistribution)
1787
1788 CPU_POP(%g1, %g3, %g4, %g5)
1789 CPU_PUSH(%g1, %g3, %g4, %g5)
1790 mov FIRE_B_AID << FIRE_DEVINO_SHIFT, %g4
1791 or %g4, JBC_ERR_INO, %g3
1792 HVCALL(_fire_err_intr_redistribution)
1793
1794 CPU_POP(%g1, %g3, %g4, %g5)
1795 CPU_PUSH(%g1, %g3, %g4, %g5)
1796 mov FIRE_B_AID << FIRE_DEVINO_SHIFT, %g4
1797 or %g4, PCIE_ERR_INO, %g3
1798 HVCALL(_fire_err_intr_redistribution)
1799 CPU_POP(%g1, %g3, %g4, %g5)
1800
1801 CPU_POP(%g7, %g3, %g4, %g5)
1802 HVRET
1803 SET_SIZE(fire_err_intr_redistribution)
1804
1805 /*
1806 * _fire_err_intr_redistribution
1807 *
1808 * %g1 - tgt cpu
1809 * %g3 - INO
1810 */
1811 ENTRY_NP(_fire_err_intr_redistribution)
1812 CPU_PUSH(%g7, %g4, %g5, %g6)
1813 CPU_PUSH(%g1, %g4, %g5, %g6) ! save tgt cpu
1814 CPU_PUSH(%g3, %g4, %g5, %g6) ! save INO
1815
1816 GUEST_STRUCT(%g4)
1817 ! get dev
1818 srlx %g3, FIRE_DEVINO_SHIFT, %g6
1819 DEVINST2INDEX(%g4, %g6, %g6, %g5, ._fire_err_intr_redistribution_fail)
1820 DEVINST2COOKIE(%g4, %g6, %g1, %g5, ._fire_err_intr_redistribution_fail)
1821
1822 and %g3, FIRE_DEVINO_MASK, %g2
1823
1824 !! %g1 = Fire Cookie
1825 !! %g2 = device ino
1826 HVCALL(_fire_intr_gettarget)
1827 !! %g3 phys cpuid for this ino
1828
1829 STRAND_STRUCT(%g2) /* FIXME: this ok ? */
1830 ldub [%g2 + STRAND_ID], %g2
1831
1832 !! %g2 this cpu (strand) id
1833 cmp %g3, %g2
1834 bne %xcc, ._fire_err_intr_redistribution_done
1835 nop
1836
1837 ! deal with virtual portion
1838 CPU_POP(%g2, %g4, %g6, %g7)
1839 mov INTR_DISABLED, %g3
1840 !! %g1 = Fire cookie
1841 !! %g2 = vino
1842 !! %g3 = Disable
1843 HVCALL(_fire_err_intr_setvalid)
1844
1845 ! set new target
1846 and %g2, FIRE_DEVINO_MASK, %g2
1847 CPU_POP(%g3, %g4, %g6, %g7)
1848 !! %g1 = Fire Cookie Ptr
1849 !! %g2 = device ino
1850 !! %g3 = Physical target CPU id
1851 HVCALL(_fire_intr_settarget)
1852
1853 ! clear state machine
1854 mov INTR_IDLE, %g3
1855 !! %g1 = Fire cookie
1856 !! %g2 = device ino
1857 !! %g3 = Idle
1858 HVCALL(_fire_intr_setstate)
1859
1860 ba,a ._fire_err_intr_redistribution_exit
1861
1862._fire_err_intr_redistribution_done:
1863 CPU_POP(%g3, %g4, %g5, %g6)
1864 CPU_POP(%g1, %g3, %g4, %g5)
1865._fire_err_intr_redistribution_exit:
1866 CPU_POP(%g7, %g3, %g4, %g5)
1867 HVRET
1868._fire_err_intr_redistribution_fail:
1869 CPU_POP(%g3, %g4, %g5, %g6)
1870 CPU_POP(%g1, %g3, %g4, %g5)
1871 ba hvabort
1872 rd %pc, %g1
1873
1874 SET_SIZE(_fire_err_intr_redistribution)
1875#endif /* CONFIG_FIRE */
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