[OpenSPARC-T2-SAM] / hypervisor / src / include / hypervisor.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: hypervisor.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _HYPERVISOR_H
#define	_HYPERVISOR_H

#pragma ident	"@(#)hypervisor.h	1.49	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif


#ifndef _HV_SAMPLE
#include <platform/hypervisor.h>
#endif

/*
 * Common Hypervisor definitions
 */

/*
 * Hypervisor software trap numbers
 */
#define	FAST_TRAP	0x80
#define	MMU_MAP_ADDR	0x83
#define	MMU_UNMAP_ADDR	0x84
#define	TTRACE_ADDENTRY	0x85
#define	CORE_TRAP	0xff


/*
 * Hypervisor function numbers for CORE_TRAP
 */
#define	API_SET_VERSION		0x00
#define	API_PUTCHAR		0x01
#define	API_EXIT		0x02
#define	API_GET_VERSION		0x03


/*
 * Hypervisor function numbers for FAST_TRAP
 */

/*
 * CPU/Memory APIs (Core API group)
 */
#define	MACH_EXIT		0x00
#define	MACH_DESC		0x01
#define	MACH_SIR		0x02
#define	MACH_SET_WATCHDOG	0x05

#define	CPU_START		0x10
#define	CPU_STOP		0x11
#define	CPU_YIELD		0x12
#define	CPU_QCONF		0x14
#define	CPU_QINFO		0x15
#define	CPU_MYID		0x16
#define	CPU_GET_STATE		0x17
#define	CPU_SET_RTBA		0x18
#define	CPU_GET_RTBA		0x19

#define	MMU_TSB_CTX0		0x20
#define	MMU_TSB_CTXNON0		0x21
#define	MMU_DEMAP_PAGE		0x22
#define	MMU_DEMAP_CTX		0x23
#define	MMU_DEMAP_ALL		0x24
#define	MMU_MAP_PERM_ADDR	0x25
#define	MMU_FAULT_AREA_CONF	0x26
#define	MMU_ENABLE		0x27
#define	MMU_UNMAP_PERM_ADDR	0x28
#define	MMU_TSB_CTX0_INFO	0x29
#define	MMU_TSB_CTXNON0_INFO	0x2a
#define	MMU_FAULT_AREA_INFO	0x2b

#define	MEM_SCRUB		0x31
#define	MEM_SYNC		0x32

#define	CPU_MONDO_SEND		0x42

#define	TOD_GET			0x50
#define	TOD_SET			0x51

#define	CONS_GETCHAR		0x60
#define	CONS_PUTCHAR		0x61
#define	CONS_READ		0x62
#define	CONS_WRITE		0x63

#define	SOFT_STATE_SET		0x70
#define	SOFT_STATE_GET		0x71

#define	TTRACE_BUF_CONF		0x90
#define	TTRACE_BUF_INFO		0x91
#define	TTRACE_ENABLE		0x92
#define	TTRACE_FREEZE		0x93
#define	DUMP_BUF_UPDATE		0x94
#define	DUMP_BUF_INFO		0x95

#define	INTR_DEVINO2SYSINO	0xa0
#define	INTR_GETENABLED		0xa1
#define	INTR_SETENABLED		0xa2
#define	INTR_GETSTATE		0xa3
#define	INTR_SETSTATE		0xa4
#define	INTR_GETTARGET		0xa5
#define	INTR_SETTARGET		0xa6

#define	VINTR_GETCOOKIE	0xa7
#define	VINTR_SETCOOKIE	0xa8
#define	VINTR_GETVALID	0xa9
#define	VINTR_SETVALID	0xaa
#define	VINTR_GETSTATE	0xab
#define	VINTR_SETSTATE	0xac
#define	VINTR_GETTARGET	0xad
#define	VINTR_SETTARGET	0xae

/*
 * vPCI APIs (PCIe API group)
 */
#define	VPCI_IOMMU_MAP		0xb0
#define	VPCI_IOMMU_UNMAP	0xb1
#define	VPCI_IOMMU_GETMAP	0xb2
#define	VPCI_IOMMU_GETBYPASS	0xb3
#define	VPCI_CONFIG_GET		0xb4
#define	VPCI_CONFIG_PUT		0xb5
#define	VPCI_IO_PEEK		0xb6
#define	VPCI_IO_POKE		0xb7
#define	VPCI_DMA_SYNC		0xb8


#define	MSIQ_CONF		0xc0
#define	MSIQ_INFO		0xc1
#define	MSIQ_GETVALID		0xc2
#define	MSIQ_SETVALID		0xc3
#define	MSIQ_GETSTATE		0xc4
#define	MSIQ_SETSTATE		0xc5
#define	MSIQ_GETHEAD		0xc6
#define	MSIQ_SETHEAD		0xc7
#define	MSIQ_GETTAIL		0xc8

#define	MSI_GETVALID		0xc9
#define	MSI_SETVALID		0xca
#define	MSI_GETMSIQ		0xcb
#define	MSI_SETMSIQ		0xcc
#define	MSI_GETSTATE		0xcd
#define	MSI_SETSTATE		0xce

#define	MSI_MSG_GETMSIQ		0xd0
#define	MSI_MSG_SETMSIQ		0xd1
#define	MSI_MSG_GETVALID	0xd2
#define	MSI_MSG_SETVALID	0xd3

#define	LDC_TX_QCONF		0xe0
#define	LDC_TX_QINFO		0xe1
#define	LDC_TX_GET_STATE	0xe2
#define	LDC_TX_SET_QTAIL	0xe3
#define	LDC_RX_QCONF		0xe4
#define	LDC_RX_QINFO		0xe5
#define	LDC_RX_GET_STATE	0xe6
#define	LDC_RX_SET_QHEAD	0xe7

#define	LDC_IRQ_CPU		0xe8
#define	LDC_SET_INO		0xe9

#define	LDC_SET_MAP_TABLE	0xea
#define	LDC_GET_MAP_TABLE	0xeb
#define	LDC_COPY		0xec
#define	LDC_MAPIN		0xed
#define	LDC_UNMAP		0xee
#define	LDC_REVOKE		0xef

/*
 * Platform-specific APIs
 */

/*
 * Greatlakes platform service channels (SVC API group)
 */
#ifdef CONFIG_SVC
#define	SVC_SEND		0x80
#define	SVC_RECV		0x81
#define	SVC_GETSTATUS		0x82
#define	SVC_SETSTATUS		0x83
#define	SVC_CLRSTATUS		0x84
#endif

/* ----------------------------------- */

/*
 * Simulation-only APIs (Core API group)
 */
#ifdef CONFIG_DISK
#define	DISK_READ		0xf0
#define	DISK_WRITE		0xf1
#endif

#ifdef T1_FPGA_SNET
#define	SNET_READ		0xf2
#define	SNET_WRITE		0xf3
#endif

#ifdef DEBUG /* Not yet FWARCd */
#define	MMU_PERM_ADDR_INFO	0xfd
#endif

/*
 * Diagnostic hcalls (Diag and Test API group)
 */
#define	DIAG_RA2PA		0x200	/* diagnostic partitions only */
#define	DIAG_HEXEC		0x201	/* diagnostic partitions only */


/* ----------------------------------- */

/*
 * Hypervisor manifest constants
 */

/*
 * Version API groups
 * hcalls: API_SET_VERSION/API_GET_VERSION
 */
#define	API_GROUP_SUN4V		0x000
#define	API_GROUP_CORE		0x001
#define	API_GROUP_INTR		0x002
#define	API_GROUP_SOFTSTATE	0x003
#define	API_GROUP_PCI		0x100
#define	API_GROUP_LDC		0x101
#define	API_GROUP_SVC		0x102
#define	API_GROUP_NCS		0x103
#define	API_GROUP_RNG		0x104
#define	API_GROUP_NIAGARA	0x200
#define	API_GROUP_FIRE		0x201
#define	API_GROUP_NIAGARA2	0x202
#define	API_GROUP_NIAGARA2PIU	0x203
#define	API_GROUP_NIAGARA2NIU	0x204
#define	API_GROUP_DIAG		0x300

#define	SUN4V_VERSION_INITIAL	1

/*
 * CPU States
 */
#define	CPU_STATE_INVALID	0x0
#define	CPU_STATE_STOPPED	0x1	/* cpu not started */
#define	CPU_STATE_RUNNING	0x2	/* cpu running guest code */
#define	CPU_STATE_ERROR		0x3	/* cpu is in the error state */
#define	CPU_STATE_SUSPENDED	0x4 	/* cpu in suspend loop */
#define	CPU_STATE_UNCONFIGURED	0x5 	/* cpu unconfigured from guest */
#define	CPU_STATE_STOPPING	0x6	/* cpu transitioning to stopped state */
#define	CPU_STATE_STARTING	0x7	/* cpu transitioning to running state */
#define	CPU_STATE_LAST_PUBLIC	CPU_STATE_ERROR /* last state defined by API */


/*
 * MMU constants
 */

/* MMU map flags (MMU_MAP_ADDR/MMU_MAP_PERM_ADDR/etc) */
#define	MAP_DTLB	0x1
#define	MAP_ITLB	0x2

#define	NPERMMAPPINGS	8	/* MMU_MAP_PERM_ADDR */

#define	MMU_FAULT_AREA_SIZE	0x80 /* MMU_FAULT_AREA */
#define	MMU_FAULT_AREA_ALIGNMENT	64

/*
 * TSB description area (MMU_TSB_*)
 */
#define	TSBD_BYTES	32
#define	TSBD_SHIFT	5	/* log2(TSBD_BYTES) */
#define	TSBD_ALIGNMENT	8

#define	TSBD_IDXPGSZ_OFF 0	/* 2 bytes */
#define	TSBD_ASSOC_OFF	2	/* 2 bytes */
#define	TSBD_SIZE_OFF	4	/* 4 bytes */
#define	TSBD_CTX_INDEX	8	/* 4 bytes */
#define	TSBD_PGSZS_OFF	12	/* 4 bytes */
#define	TSBD_BASE_OFF	16	/* 8 bytes */
#define	TSBD_RSVD_OFF	24	/* 8 bytes */

#define	TSBD_CTX_IDX_SHARE	-1


/*
 * Permanent mapping table
 */
#define	PERMMAPINFO_BYTES	32 /* size of each entry in the list */
#define	PERMMAPINFO_VA		0 /* permanent mapping virtual address */
#define	PERMMAPINFO_CTX		8 /* permanent mapping context */
#define	PERMMAPINFO_TTE		16 /* permanent mapping's TTE */
#define	PERMMAPINFO_FLAGS	24 /* permanent mapping flags for this cpu */


/*
 * cpulists
 */
#define	CPULIST_ENTRYDONE	-1 /* item in list was completed */
#define	CPULIST_ENTRYSIZE	2 /* each item is 16 bits */
#define	CPULIST_ENTRYSIZE_SHIFT	1 /* cpulist index to offset */
#define	CPULIST_ALIGNMENT	CPULIST_ENTRYSIZE


/*
 * MEM_SCRUB / MEM_SYNC
 */
#define	MEMSYNC_ALIGNMENT	0x2000

/*
 * MACH_DESC
 */
#define	MACH_DESC_ALIGNMENT	0x10	/* 16-byte alignment */

/*
 * Hypervisor call status codes
 */
#define	EOK		0	/* No error */
#define	ENOCPU		1	/* Invalid CPU id */
#define	ENORADDR	2	/* Invalid real address */
#define	ENOINTR		3	/* Invalid interrupt id */
#define	EBADPGSZ	4	/* Invalid page size encoding */
#define	EBADTSB		5	/* Invalid TSB description */
#define	EINVAL		6	/* Invalid argument */
#define	EBADTRAP	7	/* Invalid function number */
#define	EBADALIGN	8	/* Invalid address alignment */
#define	EWOULDBLOCK	9	/* Call would block */
#define	ENOACCESS	10	/* No access to resource */
#define	EIO		11	/* I/O error */
#define	ECPUERROR	12	/* CPU is in error state */
#define	ENOTSUPPORTED	13	/* Function or request is not supported */
#define	ENOMAP		14	/* No mapping found */
#define	ETOOMANY	15	/* Hard resource limit exceeded */
#define	ECHANNEL	16	/* Illegal LDC channel */

/*
 * Hypervisor call return values
 */

/* CONS_GETCHAR and CONS_PUTCHAR special character values (64-bit) */
#define	CONS_BREAK	-1
#define	CONS_HUP	-2	/* CONS_GETCHAR only */

#define	MAX_CHAR	255

/*
 * Traptrace header data structure offsets
 * TTRACE_HEADER_LAST_OFF is analogous to sun4u's TRAPTR_LAST_OFFSET
 * TTRACE_HEADER_OFFSET is analogous to sun4u's TRAPTR_OFFSET
 */
#define	TTRACE_HEADER_LAST_OFF	(0 * 8) /* 64-bits, last_offset (#bytes) */
#define	TTRACE_HEADER_OFFSET	(1 * 8) /* 64-bits, next offset (#bytes) */

/*
 * Traptrace record data structure offsets
 */
#define	TTRACE_ENTRY_TYPE	((0 * 8) + 0) /* 8-bits */
#define	TTRACE_ENTRY_HPSTATE	((0 * 8) + 1) /* 8-bits */
#define	TTRACE_ENTRY_TL		((0 * 8) + 2) /* 8-bits */
#define	TTRACE_ENTRY_GL		((0 * 8) + 3) /* 8-bits */
#define	TTRACE_ENTRY_TT		((0 * 8) + 4) /* 16-bits */
#define	TTRACE_ENTRY_TAG	((0 * 8) + 6) /* 16-bits */
#define	TTRACE_ENTRY_TSTATE	(1 * 8) /* 64-bits */
#define	TTRACE_ENTRY_TICK	(2 * 8) /* 64-bits */
#define	TTRACE_ENTRY_TPC	(3 * 8) /* 64-bits */
#define	TTRACE_ENTRY_F1		(4 * 8) /* 64-bits of entry-specific data */
#define	TTRACE_ENTRY_F2		(5 * 8) /* 64-bits of entry-specific data */
#define	TTRACE_ENTRY_F3		(6 * 8) /* 64-bits of entry-specific data */
#define	TTRACE_ENTRY_F4		(7 * 8) /* 64-bits of entry-specific data */

#define	TTRACE_RECORD_SIZE	(8 * 8) /* sizeof record data struct */
#define	TTRACE_RECORD_SZ_SHIFT	6	/* log2(TTRACE_RECORD_SIZE) */

#define	TTRACE_MINIMUM_ENTRIES	2	/* Control struct plus one record. */

#define	TTRACE_ALIGNMENT	(TTRACE_RECORD_SIZE)

/*
 * Definition of TTRACE_ENTRY_TYPE
 * All values not specified are reserved.
 */
#define	TTRACE_TYPE_UNDEF	0	/* entry data undefined */
#define	TTRACE_TYPE_HV		1	/* entry recorded by HV */
#define	TTRACE_TYPE_GUEST	255	/* guest entry, via TTRACE_ADDENTRY */

/*
 * TTRACE_ENTRY_TAG values defined for hypervisor trace entries.
 * The number space of this field is specific to the record's type.
 * Tag values used by the hypervisor are distinct from those
 * defined and used by guest software.
 */
#define	TTRACE_TAG_HVCONF	0xffff	/* continuation entry recorded by HV */

#define	INSTRUCTION_SIZE	4
#define	INSTRUCTION_ALIGNMENT	INSTRUCTION_SIZE

#define	DUMPBUF_ALIGNMENT	64

#define	MONDO_DATA_SIZE		64
#define	MONDO_DATA_ALIGNMENT	MONDO_DATA_SIZE

#define	MIN_QUEUE_ENTRIES	2

/*
 * LDC flags and other arguments
 */

#define	LDC_QENTRY_SIZE_SHIFT	6
#define	LDC_QENTRY_SIZE		(1<<LDC_QENTRY_SIZE_SHIFT)

	/* Channel state */
#define	LDC_CHANNEL_DOWN	0
#define	LDC_CHANNEL_UP		1
#define	LDC_CHANNEL_RESET	2

	/* Map table constants */

#define	LDC_MTE_SHIFT	4
#define	LDC_MTE_SIZE	(1<<LDC_MTE_SHIFT)

	/* Map permissions bits */

#define	LDC_MAP_R_BIT		0
#define	LDC_MAP_W_BIT		1
#define	LDC_MAP_X_BIT		2
#define	LDC_MAP_IOR_BIT		3
#define	LDC_MAP_IOW_BIT		4
#define	LDC_MAP_COPY_IN_BIT	5
#define	LDC_MAP_COPY_OUT_BIT	6

#define	LDC_MAP_R		(1<<LDC_MAP_R_BIT)
#define	LDC_MAP_W		(1<<LDC_MAP_W_BIT)
#define	LDC_MAP_X		(1<<LDC_MAP_X_BIT)
#define	LDC_MAP_IOR		(1<<LDC_MAP_IOR_BIT)
#define	LDC_MAP_IOW		(1<<LDC_MAP_IOW_BIT)
#define	LDC_MAP_COPY_IN		(1<<LDC_MAP_COPY_IN_BIT)
#define	LDC_MAP_COPY_OUT	(1<<LDC_MAP_COPY_OUT_BIT)

#define	LDC_MAPIN_MASK	(LDC_MAP_R|LDC_MAP_W|LDC_MAP_X|LDC_MAP_IOR|LDC_MAP_IOW)


/*
 * NOTE: Implementation - copy flags are tested against permissions
 * using: (perms & 1<<(flags+LDC_MAP_COPY_IN_BIT))
 * So take care that COPY_* flags are consistent
 */

#define	LDC_COPY_IN	0x0	/* Copy data into guest from others exprtd pg */
#define	LDC_COPY_OUT	0x1	/* Copy data out of guest to others exprtd pg */

/*
 * Guest Soft State
 */
#define	SIS_NORMAL		0x1
#define	SIS_TRANSITION		0x2

#define	SOFT_STATE_ALIGNMENT	0x20	/* 32 byte alignment */
#define	SOFT_STATE_SIZE		0x20	/* 32 bytes */

#ifdef __cplusplus
}
#endif

#endif /* _HYPERVISOR_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: hypervisor.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _HYPERVISOR_H
	50	#define _HYPERVISOR_H
	51
	52	#pragma ident "@(#)hypervisor.h 1.49 07/05/03 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58
	59	#ifndef _HV_SAMPLE
	60	#include <platform/hypervisor.h>
	61	#endif
	62
	63	/*
	64	* Common Hypervisor definitions
65	*/
66
67	/*
68	* Hypervisor software trap numbers
69	*/
70	#define FAST_TRAP 0x80
71	#define MMU_MAP_ADDR 0x83
72	#define MMU_UNMAP_ADDR 0x84
73	#define TTRACE_ADDENTRY 0x85
74	#define CORE_TRAP 0xff
75
76
77	/*
78	* Hypervisor function numbers for CORE_TRAP
79	*/
80	#define API_SET_VERSION 0x00
81	#define API_PUTCHAR 0x01
82	#define API_EXIT 0x02
83	#define API_GET_VERSION 0x03
84
85
86	/*
87	* Hypervisor function numbers for FAST_TRAP
88	*/
89
90	/*
91	* CPU/Memory APIs (Core API group)
92	*/
93	#define MACH_EXIT 0x00
94	#define MACH_DESC 0x01
95	#define MACH_SIR 0x02
96	#define MACH_SET_WATCHDOG 0x05
97
98	#define CPU_START 0x10
99	#define CPU_STOP 0x11
100	#define CPU_YIELD 0x12
101	#define CPU_QCONF 0x14
102	#define CPU_QINFO 0x15
103	#define CPU_MYID 0x16
104	#define CPU_GET_STATE 0x17
105	#define CPU_SET_RTBA 0x18
106	#define CPU_GET_RTBA 0x19
107
108	#define MMU_TSB_CTX0 0x20
109	#define MMU_TSB_CTXNON0 0x21
110	#define MMU_DEMAP_PAGE 0x22
111	#define MMU_DEMAP_CTX 0x23
112	#define MMU_DEMAP_ALL 0x24
113	#define MMU_MAP_PERM_ADDR 0x25
114	#define MMU_FAULT_AREA_CONF 0x26
115	#define MMU_ENABLE 0x27
116	#define MMU_UNMAP_PERM_ADDR 0x28
117	#define MMU_TSB_CTX0_INFO 0x29
118	#define MMU_TSB_CTXNON0_INFO 0x2a
119	#define MMU_FAULT_AREA_INFO 0x2b
120
121	#define MEM_SCRUB 0x31
122	#define MEM_SYNC 0x32
123
124	#define CPU_MONDO_SEND 0x42
125
126	#define TOD_GET 0x50
127	#define TOD_SET 0x51
128
129	#define CONS_GETCHAR 0x60
130	#define CONS_PUTCHAR 0x61
131	#define CONS_READ 0x62
132	#define CONS_WRITE 0x63
133
134	#define SOFT_STATE_SET 0x70
135	#define SOFT_STATE_GET 0x71
136
137	#define TTRACE_BUF_CONF 0x90
138	#define TTRACE_BUF_INFO 0x91
139	#define TTRACE_ENABLE 0x92
140	#define TTRACE_FREEZE 0x93
141	#define DUMP_BUF_UPDATE 0x94
142	#define DUMP_BUF_INFO 0x95
143
144	#define INTR_DEVINO2SYSINO 0xa0
145	#define INTR_GETENABLED 0xa1
146	#define INTR_SETENABLED 0xa2
147	#define INTR_GETSTATE 0xa3
148	#define INTR_SETSTATE 0xa4
149	#define INTR_GETTARGET 0xa5
150	#define INTR_SETTARGET 0xa6
151
152	#define VINTR_GETCOOKIE 0xa7
153	#define VINTR_SETCOOKIE 0xa8
154	#define VINTR_GETVALID 0xa9
155	#define VINTR_SETVALID 0xaa
156	#define VINTR_GETSTATE 0xab
157	#define VINTR_SETSTATE 0xac
158	#define VINTR_GETTARGET 0xad
159	#define VINTR_SETTARGET 0xae
160
161	/*
162	* vPCI APIs (PCIe API group)
163	*/
164	#define VPCI_IOMMU_MAP 0xb0
165	#define VPCI_IOMMU_UNMAP 0xb1
166	#define VPCI_IOMMU_GETMAP 0xb2
167	#define VPCI_IOMMU_GETBYPASS 0xb3
168	#define VPCI_CONFIG_GET 0xb4
169	#define VPCI_CONFIG_PUT 0xb5
170	#define VPCI_IO_PEEK 0xb6
171	#define VPCI_IO_POKE 0xb7
172	#define VPCI_DMA_SYNC 0xb8
173
174
175	#define MSIQ_CONF 0xc0
176	#define MSIQ_INFO 0xc1
177	#define MSIQ_GETVALID 0xc2
178	#define MSIQ_SETVALID 0xc3
179	#define MSIQ_GETSTATE 0xc4
180	#define MSIQ_SETSTATE 0xc5
181	#define MSIQ_GETHEAD 0xc6
182	#define MSIQ_SETHEAD 0xc7
183	#define MSIQ_GETTAIL 0xc8
184
185	#define MSI_GETVALID 0xc9
186	#define MSI_SETVALID 0xca
187	#define MSI_GETMSIQ 0xcb
188	#define MSI_SETMSIQ 0xcc
189	#define MSI_GETSTATE 0xcd
190	#define MSI_SETSTATE 0xce
191
192	#define MSI_MSG_GETMSIQ 0xd0
193	#define MSI_MSG_SETMSIQ 0xd1
194	#define MSI_MSG_GETVALID 0xd2
195	#define MSI_MSG_SETVALID 0xd3
196
197	#define LDC_TX_QCONF 0xe0
198	#define LDC_TX_QINFO 0xe1
199	#define LDC_TX_GET_STATE 0xe2
200	#define LDC_TX_SET_QTAIL 0xe3
201	#define LDC_RX_QCONF 0xe4
202	#define LDC_RX_QINFO 0xe5
203	#define LDC_RX_GET_STATE 0xe6
204	#define LDC_RX_SET_QHEAD 0xe7
205
206	#define LDC_IRQ_CPU 0xe8
207	#define LDC_SET_INO 0xe9
208
209	#define LDC_SET_MAP_TABLE 0xea
210	#define LDC_GET_MAP_TABLE 0xeb
211	#define LDC_COPY 0xec
212	#define LDC_MAPIN 0xed
213	#define LDC_UNMAP 0xee
214	#define LDC_REVOKE 0xef
215
216	/*
217	* Platform-specific APIs
218	*/
219
220	/*
221	* Greatlakes platform service channels (SVC API group)
222	*/
223	#ifdef CONFIG_SVC
224	#define SVC_SEND 0x80
225	#define SVC_RECV 0x81
226	#define SVC_GETSTATUS 0x82
227	#define SVC_SETSTATUS 0x83
228	#define SVC_CLRSTATUS 0x84
229	#endif
230
231	/* ----------------------------------- */
232
233	/*
234	* Simulation-only APIs (Core API group)
235	*/
236	#ifdef CONFIG_DISK
237	#define DISK_READ 0xf0
238	#define DISK_WRITE 0xf1
239	#endif
240
241	#ifdef T1_FPGA_SNET
242	#define SNET_READ 0xf2
243	#define SNET_WRITE 0xf3
244	#endif
245
246	#ifdef DEBUG /* Not yet FWARCd */
247	#define MMU_PERM_ADDR_INFO 0xfd
248	#endif
249
250	/*
251	* Diagnostic hcalls (Diag and Test API group)
252	*/
253	#define DIAG_RA2PA 0x200 /* diagnostic partitions only */
254	#define DIAG_HEXEC 0x201 /* diagnostic partitions only */
255
256
257	/* ----------------------------------- */
258
259	/*
260	* Hypervisor manifest constants
261	*/
262
263	/*
264	* Version API groups
265	* hcalls: API_SET_VERSION/API_GET_VERSION
266	*/
267	#define API_GROUP_SUN4V 0x000
268	#define API_GROUP_CORE 0x001
269	#define API_GROUP_INTR 0x002
270	#define API_GROUP_SOFTSTATE 0x003
271	#define API_GROUP_PCI 0x100
272	#define API_GROUP_LDC 0x101
273	#define API_GROUP_SVC 0x102
274	#define API_GROUP_NCS 0x103
275	#define API_GROUP_RNG 0x104
276	#define API_GROUP_NIAGARA 0x200
277	#define API_GROUP_FIRE 0x201
278	#define API_GROUP_NIAGARA2 0x202
279	#define API_GROUP_NIAGARA2PIU 0x203
280	#define API_GROUP_NIAGARA2NIU 0x204
281	#define API_GROUP_DIAG 0x300
282
283	#define SUN4V_VERSION_INITIAL 1
284
285	/*
286	* CPU States
287	*/
288	#define CPU_STATE_INVALID 0x0
289	#define CPU_STATE_STOPPED 0x1 /* cpu not started */
290	#define CPU_STATE_RUNNING 0x2 /* cpu running guest code */
291	#define CPU_STATE_ERROR 0x3 /* cpu is in the error state */
292	#define CPU_STATE_SUSPENDED 0x4 /* cpu in suspend loop */
293	#define CPU_STATE_UNCONFIGURED 0x5 /* cpu unconfigured from guest */
294	#define CPU_STATE_STOPPING 0x6 /* cpu transitioning to stopped state */
295	#define CPU_STATE_STARTING 0x7 /* cpu transitioning to running state */
296	#define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last state defined by API */
297
298
299	/*
300	* MMU constants
301	*/
302
303	/* MMU map flags (MMU_MAP_ADDR/MMU_MAP_PERM_ADDR/etc) */
304	#define MAP_DTLB 0x1
305	#define MAP_ITLB 0x2
306
307	#define NPERMMAPPINGS 8 /* MMU_MAP_PERM_ADDR */
308
309	#define MMU_FAULT_AREA_SIZE 0x80 /* MMU_FAULT_AREA */
310	#define MMU_FAULT_AREA_ALIGNMENT 64
311
312	/*
313	* TSB description area (MMU_TSB_*)
314	*/
315	#define TSBD_BYTES 32
316	#define TSBD_SHIFT 5 /* log2(TSBD_BYTES) */
317	#define TSBD_ALIGNMENT 8
318
319	#define TSBD_IDXPGSZ_OFF 0 /* 2 bytes */
320	#define TSBD_ASSOC_OFF 2 /* 2 bytes */
321	#define TSBD_SIZE_OFF 4 /* 4 bytes */
322	#define TSBD_CTX_INDEX 8 /* 4 bytes */
323	#define TSBD_PGSZS_OFF 12 /* 4 bytes */
324	#define TSBD_BASE_OFF 16 /* 8 bytes */
325	#define TSBD_RSVD_OFF 24 /* 8 bytes */
326
327	#define TSBD_CTX_IDX_SHARE -1
328
329
330	/*
331	* Permanent mapping table
332	*/
333	#define PERMMAPINFO_BYTES 32 /* size of each entry in the list */
334	#define PERMMAPINFO_VA 0 /* permanent mapping virtual address */
335	#define PERMMAPINFO_CTX 8 /* permanent mapping context */
336	#define PERMMAPINFO_TTE 16 /* permanent mapping's TTE */
337	#define PERMMAPINFO_FLAGS 24 /* permanent mapping flags for this cpu */
338
339
340	/*
341	* cpulists
342	*/
343	#define CPULIST_ENTRYDONE -1 /* item in list was completed */
344	#define CPULIST_ENTRYSIZE 2 /* each item is 16 bits */
345	#define CPULIST_ENTRYSIZE_SHIFT 1 /* cpulist index to offset */
346	#define CPULIST_ALIGNMENT CPULIST_ENTRYSIZE
347
348
349	/*
350	* MEM_SCRUB / MEM_SYNC
351	*/
352	#define MEMSYNC_ALIGNMENT 0x2000
353
354	/*
355	* MACH_DESC
356	*/
357	#define MACH_DESC_ALIGNMENT 0x10 /* 16-byte alignment */
358
359	/*
360	* Hypervisor call status codes
361	*/
362	#define EOK 0 /* No error */
363	#define ENOCPU 1 /* Invalid CPU id */
364	#define ENORADDR 2 /* Invalid real address */
365	#define ENOINTR 3 /* Invalid interrupt id */
366	#define EBADPGSZ 4 /* Invalid page size encoding */
367	#define EBADTSB 5 /* Invalid TSB description */
368	#define EINVAL 6 /* Invalid argument */
369	#define EBADTRAP 7 /* Invalid function number */
370	#define EBADALIGN 8 /* Invalid address alignment */
371	#define EWOULDBLOCK 9 /* Call would block */
372	#define ENOACCESS 10 /* No access to resource */
373	#define EIO 11 /* I/O error */
374	#define ECPUERROR 12 /* CPU is in error state */
375	#define ENOTSUPPORTED 13 /* Function or request is not supported */
376	#define ENOMAP 14 /* No mapping found */
377	#define ETOOMANY 15 /* Hard resource limit exceeded */
378	#define ECHANNEL 16 /* Illegal LDC channel */
379
380	/*
381	* Hypervisor call return values
382	*/
383
384	/* CONS_GETCHAR and CONS_PUTCHAR special character values (64-bit) */
385	#define CONS_BREAK -1
386	#define CONS_HUP -2 /* CONS_GETCHAR only */
387
388	#define MAX_CHAR 255
389
390	/*
391	* Traptrace header data structure offsets
392	* TTRACE_HEADER_LAST_OFF is analogous to sun4u's TRAPTR_LAST_OFFSET
393	* TTRACE_HEADER_OFFSET is analogous to sun4u's TRAPTR_OFFSET
394	*/
395	#define TTRACE_HEADER_LAST_OFF (0 * 8) /* 64-bits, last_offset (#bytes) */
396	#define TTRACE_HEADER_OFFSET (1 * 8) /* 64-bits, next offset (#bytes) */
397
398	/*
399	* Traptrace record data structure offsets
400	*/
401	#define TTRACE_ENTRY_TYPE ((0 * 8) + 0) /* 8-bits */
402	#define TTRACE_ENTRY_HPSTATE ((0 * 8) + 1) /* 8-bits */
403	#define TTRACE_ENTRY_TL ((0 * 8) + 2) /* 8-bits */
404	#define TTRACE_ENTRY_GL ((0 * 8) + 3) /* 8-bits */
405	#define TTRACE_ENTRY_TT ((0 * 8) + 4) /* 16-bits */
406	#define TTRACE_ENTRY_TAG ((0 * 8) + 6) /* 16-bits */
407	#define TTRACE_ENTRY_TSTATE (1 * 8) /* 64-bits */
408	#define TTRACE_ENTRY_TICK (2 * 8) /* 64-bits */
409	#define TTRACE_ENTRY_TPC (3 * 8) /* 64-bits */
410	#define TTRACE_ENTRY_F1 (4 * 8) /* 64-bits of entry-specific data */
411	#define TTRACE_ENTRY_F2 (5 * 8) /* 64-bits of entry-specific data */
412	#define TTRACE_ENTRY_F3 (6 * 8) /* 64-bits of entry-specific data */
413	#define TTRACE_ENTRY_F4 (7 * 8) /* 64-bits of entry-specific data */
414
415	#define TTRACE_RECORD_SIZE (8 * 8) /* sizeof record data struct */
416	#define TTRACE_RECORD_SZ_SHIFT 6 /* log2(TTRACE_RECORD_SIZE) */
417
418	#define TTRACE_MINIMUM_ENTRIES 2 /* Control struct plus one record. */
419
420	#define TTRACE_ALIGNMENT (TTRACE_RECORD_SIZE)
421
422	/*
423	* Definition of TTRACE_ENTRY_TYPE
424	* All values not specified are reserved.
425	*/
426	#define TTRACE_TYPE_UNDEF 0 /* entry data undefined */
427	#define TTRACE_TYPE_HV 1 /* entry recorded by HV */
428	#define TTRACE_TYPE_GUEST 255 /* guest entry, via TTRACE_ADDENTRY */
429
430	/*
431	* TTRACE_ENTRY_TAG values defined for hypervisor trace entries.
432	* The number space of this field is specific to the record's type.
433	* Tag values used by the hypervisor are distinct from those
434	* defined and used by guest software.
435	*/
436	#define TTRACE_TAG_HVCONF 0xffff /* continuation entry recorded by HV */
437
438	#define INSTRUCTION_SIZE 4
439	#define INSTRUCTION_ALIGNMENT INSTRUCTION_SIZE
440
441	#define DUMPBUF_ALIGNMENT 64
442
443	#define MONDO_DATA_SIZE 64
444	#define MONDO_DATA_ALIGNMENT MONDO_DATA_SIZE
445
446	#define MIN_QUEUE_ENTRIES 2
447
448	/*
449	* LDC flags and other arguments
450	*/
451
452	#define LDC_QENTRY_SIZE_SHIFT 6
453	#define LDC_QENTRY_SIZE (1<<LDC_QENTRY_SIZE_SHIFT)
454
455	/* Channel state */
456	#define LDC_CHANNEL_DOWN 0
457	#define LDC_CHANNEL_UP 1
458	#define LDC_CHANNEL_RESET 2
459
460	/* Map table constants */
461
462	#define LDC_MTE_SHIFT 4
463	#define LDC_MTE_SIZE (1<<LDC_MTE_SHIFT)
464
465	/* Map permissions bits */
466
467	#define LDC_MAP_R_BIT 0
468	#define LDC_MAP_W_BIT 1
469	#define LDC_MAP_X_BIT 2
470	#define LDC_MAP_IOR_BIT 3
471	#define LDC_MAP_IOW_BIT 4
472	#define LDC_MAP_COPY_IN_BIT 5
473	#define LDC_MAP_COPY_OUT_BIT 6
474
475	#define LDC_MAP_R (1<<LDC_MAP_R_BIT)
476	#define LDC_MAP_W (1<<LDC_MAP_W_BIT)
477	#define LDC_MAP_X (1<<LDC_MAP_X_BIT)
478	#define LDC_MAP_IOR (1<<LDC_MAP_IOR_BIT)
479	#define LDC_MAP_IOW (1<<LDC_MAP_IOW_BIT)
480	#define LDC_MAP_COPY_IN (1<<LDC_MAP_COPY_IN_BIT)
481	#define LDC_MAP_COPY_OUT (1<<LDC_MAP_COPY_OUT_BIT)
482
483	#define LDC_MAPIN_MASK (LDC_MAP_R\|LDC_MAP_W\|LDC_MAP_X\|LDC_MAP_IOR\|LDC_MAP_IOW)
484
485
486	/*
487	* NOTE: Implementation - copy flags are tested against permissions
488	* using: (perms & 1<<(flags+LDC_MAP_COPY_IN_BIT))
489	* So take care that COPY_* flags are consistent
490	*/
491
492	#define LDC_COPY_IN 0x0 /* Copy data into guest from others exprtd pg */
493	#define LDC_COPY_OUT 0x1 /* Copy data out of guest to others exprtd pg */
494
495	/*
496	* Guest Soft State
497	*/
498	#define SIS_NORMAL 0x1
499	#define SIS_TRANSITION 0x2
500
501	#define SOFT_STATE_ALIGNMENT 0x20 /* 32 byte alignment */
502	#define SOFT_STATE_SIZE 0x20 /* 32 bytes */
503
504	#ifdef __cplusplus
505	}
506	#endif
507
508	#endif /* _HYPERVISOR_H */