projects / OpenSPARC-T2-SAM / blame
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1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * Hypervisor Software File: asi.h | |
| 5 | * | |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 7 | * | |
| 8 | * - Do no alter or remove copyright notices | |
| 9 | * | |
| 10 | * - Redistribution and use of this software in source and binary forms, with | |
| 11 | * or without modification, are permitted provided that the following | |
| 12 | * conditions are met: | |
| 13 | * | |
| 14 | * - Redistribution of source code must retain the above copyright notice, | |
| 15 | * this list of conditions and the following disclaimer. | |
| 16 | * | |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
| 18 | * this list of conditions and the following disclaimer in the | |
| 19 | * documentation and/or other materials provided with the distribution. | |
| 20 | * | |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
| 22 | * may be used to endorse or promote products derived from this software | |
| 23 | * without specific prior written permission. | |
| 24 | * | |
| 25 | * This software is provided "AS IS," without a warranty of any kind. | |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
| 37 | * | |
| 38 | * You acknowledge that this software is not designed, licensed or | |
| 39 | * intended for use in the design, construction, operation or maintenance of | |
| 40 | * any nuclear facility. | |
| 41 | * | |
| 42 | * ========== Copyright Header End ============================================ | |
| 43 | */ | |
| 44 | /* | |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
| 46 | * Use is subject to license terms. | |
| 47 | */ | |
| 48 | ||
| 49 | #ifndef _SUN4V_ASI_H | |
| 50 | #define _SUN4V_ASI_H | |
| 51 | ||
| 52 | #pragma ident "@(#)asi.h 1.6 07/07/17 SMI" | |
| 53 | ||
| 54 | #ifdef __cplusplus | |
| 55 | extern "C" { | |
| 56 | #endif | |
| 57 | ||
| 58 | ||
| 59 | /* | |
| 60 | * sun4v ASI definitions | |
| 61 | */ | |
| 62 | #define ASI_REAL 0x14 /* Real-addressed memory */ | |
| 63 | #define ASI_REAL_IO 0x15 /* Real-addressed I/O */ | |
| 64 | #define ASI_REAL_L 0x1c /* Real-addressed memory, little-endian */ | |
| 65 | #define ASI_REAL_IO_L 0x1d /* Real-addressed I/O, little-endian */ | |
| 66 | #define ASI_SCRATCHPAD 0x20 /* Scratchpad registers */ | |
| 67 | #define ASI_MMU 0x21 /* MMU registers */ | |
| 68 | #define ASI_QUEUE 0x25 /* Queue registers */ | |
| 69 | #define ASI_REAL_QLDD 0x26 /* Real-addressed quad-ldd */ | |
| 70 | #define ASI_REAL_QLDD_L 0x2e /* Real-addressed quad-ldd, little-endian */ | |
| 71 | ||
| 72 | /* | |
| 73 | * 8x8-byte block load/store | |
| 74 | */ | |
| 75 | #define ASI_BLK_P 0xf0 /* Primary address space */ | |
| 76 | #define ASI_BLK_S 0xf1 /* Secondary address space */ | |
| 77 | #define ASI_BLK_PL 0xf8 /* Primary address space, little-endian */ | |
| 78 | #define ASI_BLK_SL 0xf9 /* Secondary address space, little-endian */ | |
| 79 | ||
| 80 | /* | |
| 81 | * sun4v ASR definitions | |
| 82 | */ | |
| 83 | #define SOFTINT_SET %asr20 | |
| 84 | #define SOFTINT_CLR %asr21 | |
| 85 | #define PERFCNTRCTRL %asr16 /* performance counter control */ | |
| 86 | #define SOFTINT %asr22 /* softint register */ | |
| 87 | #define TICKCMP %asr23 /* tick-compare */ | |
| 88 | #define STICK %asr24 /* system tick register */ | |
| 89 | #define STICKCMP %asr25 /* stick-compare */ | |
| 90 | ||
| 91 | #define SOFTINT_SM_BIT (1 << 16) | |
| 92 | ||
| 93 | /* | |
| 94 | * Processor Interrupt Levels | |
| 95 | */ | |
| 96 | #define PIL_15 0xf | |
| 97 | #define PIL_14 0xe | |
| 98 | #define PIL_13 0xd | |
| 99 | #define PIL_12 0xc | |
| 100 | #define PIL_11 0xb | |
| 101 | #define PIL_10 0xa | |
| 102 | #define PIL_9 0x9 | |
| 103 | #define PIL_8 0x8 | |
| 104 | #define PIL_7 0x7 | |
| 105 | #define PIL_6 0x6 | |
| 106 | #define PIL_5 0x5 | |
| 107 | #define PIL_4 0x4 | |
| 108 | #define PIL_3 0x3 | |
| 109 | #define PIL_2 0x2 | |
| 110 | #define PIL_1 0x1 | |
| 111 | #define PIL_0 0x0 | |
| 112 | ||
| 113 | #ifdef __cplusplus | |
| 114 | } | |
| 115 | #endif | |
| 116 | ||
| 117 | #endif /* _SUN4V_ASI_H */ |