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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * Hypervisor Software File: traps.h | |
5 | * | |
6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
7 | * | |
8 | * - Do no alter or remove copyright notices | |
9 | * | |
10 | * - Redistribution and use of this software in source and binary forms, with | |
11 | * or without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistribution of source code must retain the above copyright notice, | |
15 | * this list of conditions and the following disclaimer. | |
16 | * | |
17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
18 | * this list of conditions and the following disclaimer in the | |
19 | * documentation and/or other materials provided with the distribution. | |
20 | * | |
21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
22 | * may be used to endorse or promote products derived from this software | |
23 | * without specific prior written permission. | |
24 | * | |
25 | * This software is provided "AS IS," without a warranty of any kind. | |
26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
37 | * | |
38 | * You acknowledge that this software is not designed, licensed or | |
39 | * intended for use in the design, construction, operation or maintenance of | |
40 | * any nuclear facility. | |
41 | * | |
42 | * ========== Copyright Header End ============================================ | |
43 | */ | |
44 | /* | |
45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
46 | * Use is subject to license terms. | |
47 | */ | |
48 | ||
49 | #ifndef _SUN4V_TRAPS_H | |
50 | #define _SUN4V_TRAPS_H | |
51 | ||
52 | #pragma ident "@(#)traps.h 1.10 07/05/03 SMI" | |
53 | ||
54 | #ifdef __cplusplus | |
55 | extern "C" { | |
56 | #endif | |
57 | ||
58 | #define MAXPTL 2 /* Maximum privileged trap level */ | |
59 | #define MAXPGL 2 /* Maximum privileged globals level */ | |
60 | #define TT_OFFSET_SHIFT 5 /* tt to trap table offset shift */ | |
61 | #define TRAPTABLE_ENTRY_SIZE (8 * 4) /* Eight Instructions */ | |
62 | #define REAL_TRAPTABLE_SIZE (8 * TRAPTABLE_ENTRY_SIZE) | |
63 | #define TRAPTABLE_SIZE (1 << 14) | |
64 | ||
65 | /* | |
66 | * sun4v definition of pstate | |
67 | */ | |
68 | #define PSTATE_IE 0x00000002 /* interrupt enable */ | |
69 | #define PSTATE_PRIV 0x00000004 /* privilege */ | |
70 | #define PSTATE_AM 0x00000008 /* address mask */ | |
71 | #define PSTATE_PEF 0x00000010 /* fpu enable */ | |
72 | #define PSTATE_MM_MASK 0x000000c0 /* memory model */ | |
73 | #define PSTATE_MM_SHIFT 0x00000006 | |
74 | #define PSTATE_TLE 0x00000100 /* trap little-endian */ | |
75 | #define PSTATE_CLE 0x00000200 /* current little-endian */ | |
76 | #define PSTATE_TCT 0x00001000 /* trap on control transfer */ | |
77 | ||
78 | #define PSTATE_MM_TSO 0x00 | |
79 | #define PSTATE_MM_PSO 0x40 | |
80 | #define PSTATE_MM_RMO 0x80 | |
81 | ||
82 | #define TSTATE_CWP_SHIFT 0 | |
83 | #define TSTATE_CWP_MASK 0x1f | |
84 | #define TSTATE_PSTATE_SHIFT 8 | |
85 | #define TSTATE_ASI_SHIFT 24 | |
86 | #define TSTATE_ASI_MASK 0xff | |
87 | #define TSTATE_CCR_SHIFT 32 | |
88 | #define TSTATE_GL_SHIFT 40 | |
89 | #define TSTATE_GL_MASK 0x3 | |
90 | ||
91 | #define TSTATE_PSTATE_PRIV (PSTATE_PRIV << TSTATE_PSTATE_SHIFT) | |
92 | ||
93 | #define TT_GUEST_WATCHDOG 0x2 /* guest watchdog */ | |
94 | #define TT_IAX 0x8 /* instruction access exception */ | |
95 | #define TT_IMMU_MISS 0x9 /* instruction access MMU miss */ | |
96 | #define TT_ILLINST 0x10 /* illegal instruction */ | |
97 | #define TT_PRIVOP 0x11 /* privileged opcode */ | |
98 | #define TT_UNIMP_LDD 0x12 /* unimplemented LDD */ | |
99 | #define TT_UNIMP_STD 0x13 /* unimplemented STD */ | |
100 | #define TT_FP_DISABLED 0x20 /* fp disabled */ | |
101 | #define TT_FP_IEEE754 0x21 /* fp exception IEEE 754 */ | |
102 | #define TT_FP_OTHER 0x22 /* fp exception other */ | |
103 | #define TT_TAGOVERFLOW 0x23 /* tag overflow */ | |
104 | #define TT_CLEANWIN 0x24 /* cleanwin (BIG) */ | |
105 | #define TT_DIV0 0x28 /* division by zero */ | |
106 | #define TT_DAX 0x30 /* data access exception */ | |
107 | #define TT_DMMU_MISS 0x31 /* data access MMU miss */ | |
108 | #define TT_DAP 0x33 /* data access protection */ | |
109 | #define TT_ALIGN 0x34 /* mem address not aligned */ | |
110 | #define TT_LDDF_ALIGN 0x35 /* LDDF mem address not aligned */ | |
111 | #define TT_STDF_ALIGN 0x36 /* STDF mem address not aligned */ | |
112 | #define TT_PRIVACT 0x37 /* privileged action */ | |
113 | #define TT_LDQF_ALIGN 0x38 /* LDQF mem address not aligned */ | |
114 | #define TT_STQF_ALIGN 0x39 /* STQF mem address not aligned */ | |
115 | #define TT_INTR_LEV1 0x41 /* interrupt level 1 */ | |
116 | #define TT_INTR_LEV2 0x42 /* interrupt level 2 */ | |
117 | #define TT_INTR_LEV3 0x43 /* interrupt level 3 */ | |
118 | #define TT_INTR_LEV4 0x44 /* interrupt level 4 */ | |
119 | #define TT_INTR_LEV5 0x45 /* interrupt level 5 */ | |
120 | #define TT_INTR_LEV6 0x46 /* interrupt level 6 */ | |
121 | #define TT_INTR_LEV7 0x47 /* interrupt level 7 */ | |
122 | #define TT_INTR_LEV8 0x48 /* interrupt level 8 */ | |
123 | #define TT_INTR_LEV9 0x49 /* interrupt level 9 */ | |
124 | #define TT_INTR_LEVa 0x4a /* interrupt level a */ | |
125 | #define TT_INTR_LEVb 0x4b /* interrupt level b */ | |
126 | #define TT_INTR_LEVc 0x4c /* interrupt level c */ | |
127 | #define TT_INTR_LEVd 0x4d /* interrupt level d */ | |
128 | #define TT_INTR_LEVe 0x4e /* interrupt level e */ | |
129 | #define TT_INTR_LEVf 0x4f /* interrupt level f */ | |
130 | #define TT_RA_WATCH 0x61 /* real address watchpoint */ | |
131 | #define TT_VA_WATCH 0x62 /* virtual address watchpoint */ | |
132 | #define TT_FAST_IMMU_MISS 0x64 /* fast immu miss (BIG) */ | |
133 | #define TT_FAST_DMMU_MISS 0x68 /* fast dmmu miss (BIG) */ | |
134 | #define TT_FAST_DMMU_PROT 0x6c /* fast dmmu protection (BIG) */ | |
135 | #define TT_CTI_TAKEN 0x74 /* control transfer instruction */ | |
136 | #define TT_CPU_MONDO 0x7c /* cpu mondo */ | |
137 | #define TT_DEV_MONDO 0x7d /* dev mondo */ | |
138 | #define TT_RESUMABLE_ERR 0x7e /* resumable error */ | |
139 | #define TT_NONRESUMABLE_ERR 0x7f /* non-resumable error */ | |
140 | #define TT_SPILL_0_NORMAL 0x80 /* spill 0 normal (BIG) */ | |
141 | #define TT_SPILL_1_NORMAL 0x84 /* spill 1 normal (BIG) */ | |
142 | #define TT_SPILL_2_NORMAL 0x88 /* spill 2 normal (BIG) */ | |
143 | #define TT_SPILL_3_NORMAL 0x8c /* spill 3 normal (BIG) */ | |
144 | #define TT_SPILL_4_NORMAL 0x90 /* spill 4 normal (BIG) */ | |
145 | #define TT_SPILL_5_NORMAL 0x94 /* spill 5 normal (BIG) */ | |
146 | #define TT_SPILL_6_NORMAL 0x98 /* spill 6 normal (BIG) */ | |
147 | #define TT_SPILL_7_NORMAL 0x9c /* spill 7 normal (BIG) */ | |
148 | #define TT_SPILL_0_OTHER 0xa0 /* spill 0 other (BIG) */ | |
149 | #define TT_SPILL_1_OTHER 0xa4 /* spill 1 other (BIG) */ | |
150 | #define TT_SPILL_2_OTHER 0xa8 /* spill 2 other (BIG) */ | |
151 | #define TT_SPILL_3_OTHER 0xac /* spill 3 other (BIG) */ | |
152 | #define TT_SPILL_4_OTHER 0xb0 /* spill 4 other (BIG) */ | |
153 | #define TT_SPILL_5_OTHER 0xb4 /* spill 5 other (BIG) */ | |
154 | #define TT_SPILL_6_OTHER 0xb8 /* spill 6 other (BIG) */ | |
155 | #define TT_SPILL_7_OTHER 0xbc /* spill 7 other (BIG) */ | |
156 | #define TT_FILL_0_NORMAL 0xc0 /* fill 0 normal (BIG) */ | |
157 | #define TT_FILL_1_NORMAL 0xc4 /* fill 1 normal (BIG) */ | |
158 | #define TT_FILL_2_NORMAL 0xc8 /* fill 2 normal (BIG) */ | |
159 | #define TT_FILL_3_NORMAL 0xcc /* fill 3 normal (BIG) */ | |
160 | #define TT_FILL_4_NORMAL 0xd0 /* fill 4 normal (BIG) */ | |
161 | #define TT_FILL_5_NORMAL 0xd4 /* fill 5 normal (BIG) */ | |
162 | #define TT_FILL_6_NORMAL 0xd8 /* fill 6 normal (BIG) */ | |
163 | #define TT_FILL_7_NORMAL 0xdc /* fill 7 normal (BIG) */ | |
164 | #define TT_FILL_0_OTHER 0xe0 /* fill 0 other (BIG) */ | |
165 | #define TT_FILL_1_OTHER 0xe4 /* fill 1 other (BIG) */ | |
166 | #define TT_FILL_2_OTHER 0xe8 /* fill 2 other (BIG) */ | |
167 | #define TT_FILL_3_OTHER 0xec /* fill 3 other (BIG) */ | |
168 | #define TT_FILL_4_OTHER 0xf0 /* fill 4 other (BIG) */ | |
169 | #define TT_FILL_5_OTHER 0xf4 /* fill 5 other (BIG) */ | |
170 | #define TT_FILL_6_OTHER 0xf8 /* fill 6 other (BIG) */ | |
171 | #define TT_FILL_7_OTHER 0xfc /* fill 7 other (BIG) */ | |
172 | #define TT_SWTRAP_BASE 0x100 /* trap instruction */ | |
173 | ||
174 | #ifdef __cplusplus | |
175 | } | |
176 | #endif | |
177 | ||
178 | #endif /* _SUN4V_TRAPS_H */ |