projects / OpenSPARC-T2-SAM / blame
| Commit | Line | Data |
|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * Copyright 2005 Sun Microsystems, Inc. All rights reserved. | |
| 3 | * Use is subject to license terms. | |
| 4 | */ | |
| 5 | #pragma ident "@(#)README.libpiu 1.1 05/10/05 SMI" | |
| 6 | ||
| 7 | "piu" device howto | |
| 8 | ======================================================= | |
| 9 | ||
| 10 | I. What is "piu" device? | |
| 11 | ------------------------ | |
| 12 | This device implements the PCI Express Interface Unit (PIU) to | |
| 13 | allow an PCIE based I/O subsystem (PCIE end point device) to | |
| 14 | be connected to the Niagara2 chip. | |
| 15 | ||
| 16 | ||
| 17 | II. Where is libpiu? | |
| 18 | -------------------- | |
| 19 | The source is in <ws>/devices/mem_bus/libpiu | |
| 20 | ||
| 21 | ||
| 22 | III. How is libpiu implemented? | |
| 23 | ------------------------------- | |
| 24 | It is implemented as a typical dev_type_t device module | |
| 25 | ||
| 26 | ||
| 27 | dev_type_t dev_type_piu={ | |
| 28 | "piu", | |
| 29 | piu_parse(), | |
| 30 | piu_init(), | |
| 31 | piu_dump(), | |
| 32 | generic_device_non_cacheable(), | |
| 33 | piu_cpu_access(), | |
| 34 | DEV_MAGIC | |
| 35 | }; | |
| 36 | ||
| 37 | The device specific parser interface "piu_parse" is extended so | |
| 38 | it's capable of parsing and loading an PCIE end point device. | |
| 39 | ||
| 40 | The downbound transaction (N2 core->PIU->PCIE end device) is | |
| 41 | handled by the the "piu_cpu_access" interface for | |
| 42 | ||
| 43 | * access to PCIE CSRs | |
| 44 | * read/write access to PCIE Cfg/IO, MEM32 and MEM64 space | |
| 45 | ||
| 46 | ||
| 47 | The PCIE end device is implemented by with a new device type | |
| 48 | which is derived from the dev_type_t and similar to the one | |
| 49 | used in the "fire" device module: | |
| 50 | ||
| 51 | ||
| 52 | typedef struct pcie_dev_type { | |
| 53 | char *dev_type_namep; | |
| 54 | void (*dev_init)(); | |
| 55 | void (*dev_parse)(); | |
| 56 | void (*dev_dump)(); | |
| 57 | uint16_t req_id; | |
| 58 | bool_t (*dev_cfg_read)(); | |
| 59 | bool_t (*dev_cfg_write)(); | |
| 60 | int (*bar_test)(); | |
| 61 | bool_t (*dev_mem_read)(); | |
| 62 | bool_t (*dev_mem_write)(); | |
| 63 | bool_t (*dev_io_read)(); | |
| 64 | bool_t (*dev_io_write)(); | |
| 65 | pcie_model_t *pcie_modp; | |
| 66 | pcie_access_t *pcie_accessp; | |
| 67 | struct pcie_dev_type *next; | |
| 68 | } pcie_dev_type_t; | |
| 69 | ||
| 70 | where "pcie_access_t" is defined as below to handle the | |
| 71 | upbound transaction (PCIE end device->PIU->N2 core) such | |
| 72 | as the DMA read and write: | |
| 73 | ||
| 74 | typedef struct pcie_access { | |
| 75 | bool_t *pcie_dma_read(); | |
| 76 | bool_t *pcie_dma_write(); | |
| 77 | bool_t *pcie_msi_write(); | |
| 78 | bool_t *pcie_msg_assert_intx(); | |
| 79 | bool_t *pcie_msg_deassert_intx(); | |
| 80 | } pcie_access_t; | |
| 81 | ||
| 82 | ||
| 83 | III. How do I configure the "piu" device | |
| 84 | ---------------------------------------- | |
| 85 | The config syntax for loading the "piu" device and an PCIE | |
| 86 | end point device is: | |
| 87 | ||
| 88 | device "piu" <addr1> + <size1>, <addr2> + <size2> | |
| 89 | { | |
| 90 | pcie_device "dev_name" <pcie device properties>; // optional | |
| 91 | } | |
| 92 | ||
| 93 | Example: | |
| 94 | load "bcm" device as an PCIE end point device: | |
| 95 | ||
| 96 | device "piu" 0x8800000000 + 8M, 0xC000000000 + 64G | |
| 97 | { | |
| 98 | pcie_device "bcm" 2 0 "/dev/bge"; | |
| 99 | } |