Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / devices / mem_bus / include / pcie_device.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: pcie_device.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _PCIE_DEVICE_H
29#define _PCIE_DEVICE_H
30
31#pragma ident "@(#)pcie_device.h 1.4 06/10/05 SMI"
32
33/*
34 * This file contains function prototypes and data structures
35 * for PCIE device generic support
36 */
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42/*
43 * Structure used to implement PCIE interface unit model
44 * (it's named as PIU for Niagara 2)
45 */
46typedef struct PCIE_MODEL pcie_model_t;
47
48/*
49 * Macros, structs used in PCIE device
50 */
51#define PCIE_REQ_ID(bus,dev,fun) ((bus<<8)|((MASK64(4,0)&dev)<<3)|(MASK64(2,0)&fun))
52#define PCIE_BUS_NO(req_id) ((req_id & MASK64(15,8))>>8)
53#define PCIE_DEV_NO(req_id) ((req_id & MASK64(7,3))>>3)
54#define PCIE_FUN_NO(req_id) ((req_id & MASK64(2,0)))
55
56typedef enum {
57 PCIE_IS32 = 0,
58 PCIE_IS64 = 1
59} dev_mode_t;
60
61typedef enum {
62 PCIE_CFG = 0,
63 PCIE_IO = 1,
64 PCIE_MEM32 = 2,
65 PCIE_MEM64 = 3
66} pcie_space_t;
67
68/*
69 * PCIE interface for down bound transaction
70 */
71typedef struct pcie_dwbound {
72 bool_t (*mem_access)(void *hdl, uint64_t addr, uint64_t *datap, uint32_t count, dev_access_t type,
73 pcie_space_t space_id);
74 int (*bar_test)(void *hdl, uint64_t addr, pcie_space_t space_id);
75} pcie_dwbound_t;
76
77/*
78 * PCIE access interface for upbound transaction
79 */
80typedef struct pcie_upbound {
81 bool_t (*dma_access)(pcie_model_t *pcie_model, tvaddr_t va, uint8_t *datap, int count,
82 uint16_t req_id, dev_access_t type, dev_mode_t mode);
83 bool_t (*assert_intx)(pcie_model_t *pcie_model, uint8_t pin_no, uint8_t dev_no);
84 bool_t (*deassert_intx)(pcie_model_t *pcie_model, uint8_t pin_no, uint8_t dev_no);
85} pcie_upbound_t;
86
87
88/*
89 * PCIE device instance (an instance of a pcie device type)
90 */
91typedef struct pcie_dev_inst {
92 uint16_t req_id; /* 16 bit request ID (8 bit bus_no, 5 bit dev_no, 3 bit fun_no */
93
94 pcie_dwbound_t *pcie_dp;
95 void *hdl;
96
97 pcie_upbound_t *pcie_up;
98 pcie_model_t *pcie_modp;
99
100 struct pcie_dev_inst *next;
101} pcie_dev_inst_t;
102
103
104/*
105 * PCIE device type (derived from DEV_TYPE)
106 */
107typedef struct pcie_dev_type {
108 char *dev_type_namep;
109 void (*dev_init)(struct pcie_dev_inst *);
110 void (*dev_parse)(void *);
111 void (*dev_dump)(void *);
112} pcie_dev_type_t;
113
114
115/*
116 * PCIE Mondo interrupt
117 */
118typedef struct PCIE_MONDO {
119 int thread_id;
120 uint64_t data[8];
121} pcie_mondo_t;
122
123
124#ifdef __cplusplus
125}
126#endif
127
128#endif /* _PCIE_DEVICE_H */