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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: xdcache.h | |
5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
7 | * | |
8 | * The above named program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public | |
10 | * License version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * The above named program is distributed in the hope that it will be | |
13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public | |
18 | * License along with this work; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | * | |
21 | * ========== Copyright Header End ============================================ | |
22 | */ | |
23 | /* | |
24 | * Copyright 2006 Sun Microsystems, Inc. All rights reserved. | |
25 | * Use is subject to license terms. | |
26 | */ | |
27 | ||
28 | #ifndef _XDCACHE_H_ | |
29 | #define _XDCACHE_H_ | |
30 | ||
31 | #pragma ident "@(#)xdcache.h 1.9 06/09/01 SMI" | |
32 | ||
33 | #ifdef __cplusplus | |
34 | extern "C" { | |
35 | #endif | |
36 | ||
37 | /* | |
38 | * Simulator's data access cache model | |
39 | * Overloaded to simulate datacaches, and TLB accesses etc. | |
40 | * Basically - fast tracks as many loads/stores as possible, | |
41 | * then misses to handle exceptional cases. | |
42 | */ | |
43 | ||
44 | #define XDCACHE_LINE_SIZE_BITS 13 /* 8K pages unless we want a real d-cache */ | |
45 | #define XDCACHE_LINE_SIZE (1ULL<<XDCACHE_LINE_SIZE_BITS) | |
46 | #define XDCACHE_LINE_OFFSET_MASK (XDCACHE_LINE_SIZE-1) | |
47 | #define XDCACHE_TAG_MASK (~XDCACHE_LINE_OFFSET_MASK) | |
48 | ||
49 | #define XDCACHE_NUM_LINES_BITS 8 /* log2(entries) (must be at least 4, as we need 2 bits in tag) */ | |
50 | #define XDCACHE_NUM_LINES (1<<XDCACHE_NUM_LINES_BITS) /* 64 entries */ | |
51 | ||
52 | ||
53 | /* FIXME: must deal with SPARC address masking so this goes away soon */ | |
54 | #if (XDCACHE_LINE_SIZE_BITS+XDCACHE_NUM_LINES_BITS)>=32 | |
55 | #error Total number of bits spanned by XDcache must be less than 32 for SPARC address masking to work | |
56 | #endif | |
57 | ||
58 | ||
59 | /* | |
60 | * The tag match algorithm is design to test 3 things simultaneously: | |
61 | * Tag match + alignment + access permission. | |
62 | * | |
63 | * We need 2 bits for access permission and validity checks in the tag field. | |
64 | * We also reserve 3 bits to test the correct access alignment. | |
65 | * Thus the tag field holds a maximum of 64-2-3 = 58 bits of the tag. | |
66 | * These become fewer if the cache lines are larger than 32 bytes. | |
67 | * | |
68 | * So, suppose there is a 4 byte read to address 0x3ce000. | |
69 | * | |
70 | * A matching tag would look something like 0x3ce008. | |
71 | * | |
72 | * The check looks something like: (addr | READ_PERM) ^ tag | |
73 | * If the read perm bit is not set in the tag, then tag bit field in the result is non-zero. | |
74 | * If addr is not aligned correctly, then the bottom 2 bits are non zero. | |
75 | * If the tag doesn't match then the upper bits are non-zero. | |
76 | * So to check for a match, mask the result with a mask with the upper bits set | |
77 | * (for the actual tag fields), the READ_PERM bit, and the bottom N (2) bits set for | |
78 | * checking alignment. | |
79 | * This mask is concocted appropriately for each type of load. | |
80 | * | |
81 | * Thus trivially, a suitable invalid tag is one where neither the READ_PERM nor WRITE_PERM bits | |
82 | * are set .. i.e. 0. | |
83 | */ | |
84 | ||
85 | typedef struct { | |
86 | tvaddr_t tag; | |
87 | #define XDCACHE_INVALID_TAG 0 | |
88 | #define XDCACHE_ALIGN_MASK 0x7 | |
89 | #define XDCACHE_READ_PERM 0x8 | |
90 | #define XDCACHE_WRITE_PERM 0x10 | |
91 | uint64_t offset; /* addr + offset = location of data in simulator memory */ | |
92 | } xdcache_line_t; | |
93 | ||
94 | /* | |
95 | * Try to optimize locating of xdc_line by using raw values to | |
96 | * avoid excess shifts and masking by compiler | |
97 | */ | |
98 | ||
99 | #define XDCACHE_RAW_LINE_BITS 4 /* 16 bytes sizeof(tvaddr_t) + sizeof(offset) */ | |
100 | #define XDCACHE_RAW_SHIFT (XDCACHE_LINE_SIZE_BITS - XDCACHE_RAW_LINE_BITS) | |
101 | #define XDCACHE_RAW_LINE_MASK ((XDCACHE_NUM_LINES-1) << XDCACHE_RAW_LINE_BITS) | |
102 | ||
103 | ||
104 | #define XDCACHE_SANITY_CHECK() do { \ | |
105 | ASSERT( XDCACHE_RAW_SHIFT >= 3 ); /* must ensure miss-align bits shift off */\ | |
106 | ASSERT( sizeof(xdcache_line_t) == (1<<XDCACHE_RAW_LINE_BITS) ); \ | |
107 | } while (0) | |
108 | ||
109 | typedef struct { | |
110 | config_addr_t * miss_addrp; /* cache of last memory miss address */ | |
111 | void (*miss)(simcpu_t * sp, uint64_t * regp, tvaddr_t addr, int op); | |
112 | xdcache_line_t line[XDCACHE_NUM_LINES]; | |
113 | } xdcache_t; | |
114 | ||
115 | ||
116 | extern void xdcache_flush(simcpu_t * sp); | |
117 | ||
118 | #if PERFORMANCE_CHECK /* { */ | |
119 | #define XDC_HIT(sp) do { (sp)->xdc_hits++; } while (0) | |
120 | #define XDC_MISS(sp) do { (sp)->xdc_misses++; } while (0) | |
121 | #define XDC_FLUSH(sp) do { (sp)->xdc_flushes++; } while (0) | |
122 | #else | |
123 | #define XDC_HIT(sp) do { } while (0) | |
124 | #define XDC_MISS(sp) do { } while (0) | |
125 | #define XDC_FLUSH(sp) do { } while (0) | |
126 | #endif /* PERFORMANCE_CHECK } */ | |
127 | ||
128 | #ifdef __cplusplus | |
129 | } | |
130 | #endif | |
131 | ||
132 | #endif /* _XDCACHE_H_ */ |