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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sparcv9 / include / sparcv9decode.h
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: sparcv9decode.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _SPARCV9DECODE_H_
29#define _SPARCV9DECODE_H_
30
31#pragma ident "@(#)sparcv9decode.h 1.15 07/03/19 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37 /*
38 * Principal instruction decoding for SPARC v9 instruction set.
39 * Eventually maybe v8 will be a defined subset of this.
40 */
41
42
43typedef enum {
44 illegal_instruction,
45 unknown_instruction,
46 unknown_fp_instruction,
47 bpcc_illegal_cc_specifier,
48 bpr_illegal_cc_specifier,
49 done_retry_illegal_fcn_field,
50 saved_fcn_invalid,
51 saved_reserved_field_non_zero,
52 tcc_reserved_field_non_zero,
53 tcc_illegal_cc_field,
54 movcc_reserved_field_non_zero,
55 movcc_illegal_cc_field,
56 movr_illegal_cc_field,
57 odd_rd_for_ldd,
58 odd_rd_for_std,
59 fpop_bit13_set,
60 illegal_fsr_specifier,
61 unimplemented_visop,
62 illtrap_reserved_field_non_zero,
63 fmovcc_reserved_field_non_zero,
64 fmovcc_illegal_cc_field,
65 flushw_reserved_field_non_zero,
66 visop36_reserved_field_non_zero,
67 sir_reserved_field_non_zero,
68 cas_reserved_field_non_zero,
69 misc_reserved_field_non_zero
70} v9_ill_instn_reason_t;
71
72
73
74
75/*
76 * Basic enumeration for the instruction types (op field) opcodes.
77 */
78
79typedef enum {
80 Ty_0 = 0, /* Branches and sethi */
81 Ty_1 = 1, /* Call */
82 Ty_2 = 2, /* Arithmetic & Misc */
83 Ty_3 = 3 /* Loads/Stores */
84} ty_code_t;
85
86
87
88
89/*
90 * An enumeration table for the op2 values for op==0
91 */
92
93typedef enum {
94 T0o3_Illtrap = 0, T0o3_BPcc,
95 T0o3_Bicc, T0o3_BPr,
96 T0o3_SetHi, T0o3_FBPfcc,
97 T0o3_FBfcc, T0o3_unknown_0x7
98} T0o3_code_t;
99
100/*
101 * An enumeration table for the op3 values for op==2
102 */
103
104typedef enum {
105 /* Col 0 (0x00 - 0x0f) */
106 T2o3_add, T2o3_and, T2o3_or, T2o3_xor,
107 T2o3_sub, T2o3_andn, T2o3_orn, T2o3_xnor,
108 T2o3_addc, T2o3_mulx, T2o3_umul, T2o3_smul,
109 T2o3_subc, T2o3_udivx, T2o3_udiv, T2o3_sdiv,
110 /* Col 1 (0x10 - 0x1f) */
111 T2o3_addcc, T2o3_andcc, T2o3_orcc, T2o3_xorcc,
112 T2o3_subcc, T2o3_andncc, T2o3_orncc, T2o3_xnorcc,
113 T2o3_addccc, T2o3_unknown_0x19, T2o3_umulcc, T2o3_smulcc,
114 T2o3_subccc, T2o3_unknown_0x1d, T2o3_udivcc, T2o3_sdivcc,
115 /* Col 2 (0x20 - 0x2f) */
116 T2o3_taddcc, T2o3_tsubcc, T2o3_taddcctv, T2o3_tsubcctv,
117 T2o3_mulscc, T2o3_sll, T2o3_srl, T2o3_sra,
118 T2o3_rdasr, T2o3_rdhpr, T2o3_rdpr, T2o3_flushw,
119 T2o3_movcc, T2o3_sdivx, T2o3_popc, T2o3_movr,
120 /* Col 3 (0x30 - 0x3f) */
121 T2o3_wrasr, T2o3_saved, T2o3_wrpr, T2o3_wrhpr,
122 T2o3_fpop_0x34, T2o3_fpop_0x35, T2o3_gop, T2o3_unknown_0x37,
123 T2o3_jmpl, T2o3_return, T2o3_tcc, T2o3_flush,
124 T2o3_save, T2o3_restore, T2o3_retry, T2o3_unknown_0x3f
125} T2o3_code_t;
126
127/*
128 * Table of op3 values for the op=3 (load/store) opcodes
129 */
130
131typedef enum {
132 /* Col 0 (0x00 - 0x0f) */
133 T3o3_lduw, T3o3_ldub, T3o3_lduh, T3o3_ldd,
134 T3o3_stw, T3o3_stb, T3o3_sth, T3o3_std,
135 T3o3_ldsw, T3o3_ldsb, T3o3_ldsh, T3o3_ldx,
136 T3o3_unknown_0x0c, T3o3_ldstub1, T3o3_stx, T3o3_swapd,
137 /* Col 1 (0x10 - 0x1f) */
138 T3o3_lduwa, T3o3_lduba, T3o3_lduha, T3o3_ldda,
139 T3o3_stwa, T3o3_stba, T3o3_stha, T3o3_stda,
140 T3o3_ldswa, T3o3_ldsba, T3o3_ldsha, T3o3_ldxa,
141 T3o3_unknown_0x1c, T3o3_ldstuba, T3o3_stxa, T3o3_swapa,
142 /* Col 2 (0x20 - 0x2f) */
143 T3o3_ldf, T3o3_ldfsr, T3o3_ldqf, T3o3_lddf,
144 T3o3_stf, T3o3_stfsr, T3o3_stqf, T3o3_stdf,
145 T3o3_unknown_0x28, T3o3_unknown_0x29, T3o3_unknown_0x2a, T3o3_unknown_0x2b,
146 T3o3_unknown_0x2c, T3o3_prefetch, T3o3_unknown_0x2e, T3o3_unknown_0x2f,
147 /* Col 3 (0x30 - 0x3f) */
148 T3o3_ldfa, T3o3_unknown_0x31, T3o3_ldqfa, T3o3_lddfa,
149 T3o3_stfa, T3o3_unknown_0x35, T3o3_stqfa, T3o3_stdfa,
150 T3o3_unknown_0x38, T3o3_unknown_0x39, T3o3_unknown_0x3a, T3o3_unknown_0x3b,
151 T3o3_casa, T3o3_prefetcha, T3o3_casxa, T3o3_unknown_0x3f
152} T3o3_code_t;
153
154
155/*
156 * Table of opf fields for the op=3, op3=0x34 floating point ops
157 */
158
159typedef enum {
160 FPop34_fmovs = 0x001, FPop34_fmovd = 0x002, FPop34_fmovq = 0x003,
161 FPop34_fnegs = 0x005, FPop34_fnegd = 0x006, FPop34_fnegq = 0x007,
162 FPop34_fabss = 0x009, FPop34_fabsd = 0x00a, FPop34_fabsq = 0x00b,
163 FPop34_fsqrts = 0x029, FPop34_fsqrtd = 0x02a, FPop34_fsqrtq = 0x02b,
164 FPop34_fadds = 0x041, FPop34_faddd = 0x042, FPop34_faddq = 0x043,
165 FPop34_fsubs = 0x045, FPop34_fsubd = 0x046, FPop34_fsubq = 0x047,
166 FPop34_fmuls = 0x049, FPop34_fmuld = 0x04a, FPop34_fmulq = 0x04b,
167 FPop34_fdivs = 0x04d, FPop34_fdivd = 0x04e, FPop34_fdivq = 0x04f,
168
169 /* following instructions are Rock only */
170 FPop34_fnadds = 0x051, FPop34_fnaddd = 0x052,
171 FPop34_fnmuls = 0x059, FPop34_fnmuld = 0x05a,
172 FPop34_fhadds = 0x061, FPop34_fhaddd = 0x062,
173 FPop34_fhsubs = 0x065, FPop34_fhsubd = 0x066,
174
175 FPop34_fsmuld = 0x069, FPop34_fdmulq = 0x06e,
176
177 /* following instructions are Rock only */
178 FPop34_fnhadds = 0x071, FPop34_fnhaddd = 0x072,
179 FPop34_fnsmuld = 0x079,
180
181 FPop34_fstox = 0x081, FPop34_fdtox = 0x082, FPop34_fqtox = 0x083,
182 FPop34_fxtos = 0x084, FPop34_fxtod = 0x088, FPop34_fxtoq = 0x08c,
183 FPop34_fitos = 0x0c4, FPop34_fdtos = 0x0c6, FPop34_fqtos = 0x087,
184 FPop34_fitod = 0x0c8, FPop34_fstod = 0x0c9, FPop34_fqtod = 0x0cb,
185 FPop34_fitoq = 0x0cc, FPop34_fstoq = 0x0cd, FPop34_fdtoq = 0x0ce,
186 FPop34_fstoi = 0x0d1, FPop34_fdtoi = 0x0d2, FPop34_fqtoi = 0x0d3
187} T3o3_fp34_opf_t;
188
189
190/*
191 * Table of opf fields for the op=3, op3=0x35 floating point ops
192 */
193
194typedef enum {
195 FPop35_fmovrsz = 0x025, FPop35_fmovrdz = 0x026, FPop35_fmovrqz = 0x027,
196 FPop35_fmovrslez = 0x045, FPop35_fmovrdlez = 0x046, FPop35_fmovrqlez = 0x047,
197 FPop35_fmovrslz = 0x065, FPop35_fmovrdlz = 0x066, FPop35_fmovrqlz = 0x067,
198 FPop35_fmovrsnz = 0x0a5, FPop35_fmovrdnz = 0x0a6, FPop35_fmovrqnz = 0x0a7,
199 FPop35_fmovrsgz = 0x0c5, FPop35_fmovrdgz = 0x0c6, FPop35_fmovrqgz = 0x0c7,
200 FPop35_fmovrsgez = 0x0e5, FPop35_fmovrdgez = 0x0e6, FPop35_fmovrqgez = 0x0e7,
201 FPop35_fmovs_fcc0 = 0x001, FPop35_fmovd_fcc0 = 0x002, FPop35_fmovq_fcc0 = 0x003,
202 FPop35_fmovs_fcc1 = 0x041, FPop35_fmovd_fcc1 = 0x042, FPop35_fmovq_fcc1 = 0x043,
203 FPop35_fmovs_fcc2 = 0x081, FPop35_fmovd_fcc2 = 0x082, FPop35_fmovq_fcc2 = 0x083,
204 FPop35_fmovs_fcc3 = 0x0c1, FPop35_fmovd_fcc3 = 0x0c2, FPop35_fmovq_fcc3 = 0x0c3,
205 FPop35_fmovs_icc = 0x101, FPop35_fmovd_icc = 0x102, FPop35_fmovq_icc = 0x103,
206 FPop35_fmovs_xcc = 0x181, FPop35_fmovd_xcc = 0x182, FPop35_fmovq_xcc = 0x183,
207 FPop35_fcmps = 0x051, FPop35_fcmpd = 0x052, FPop35_fcmpq = 0x053,
208 FPop35_fcmpes = 0x055, FPop35_fcmped = 0x056, FPop35_fcmpeq = 0x057
209} T3o3_fp35_opf_t;
210
211
212/*
213 * Table of opf fields for the op=3, op3=0x36 vis ops
214 */
215
216typedef enum {
217 VISop36_edge8 = 0x000, VISop36_edge8n = 0x001,
218 VISop36_edge8l = 0x002, VISop36_edge8ln = 0x003,
219 VISop36_edge16 = 0x004, VISop36_edge16n = 0x005,
220 VISop36_edge16l = 0x006, VISop36_edge16ln = 0x007,
221 VISop36_edge32 = 0x008, VISop36_edge32n = 0x009,
222 VISop36_edge32l = 0x00a, VISop36_edge32ln = 0x00b,
223 VISop36_array8 = 0x010, VISop36_addxc = 0x011,
224 VISop36_array16 = 0x012, VISop36_addxccc = 0x013,
225 VISop36_array32 = 0x014, VISop36_random = 0x015,
226 VISop36_umulxhi = 0x016, VISop36_lzd = 0x017,
227 VISop36_alignaddr = 0x018, VISop36_bmask = 0x019,
228 VISop36_alignaddrl = 0x01a, VISop36_cmask8 = 0x01b,
229 VISop36_cmask16 = 0x01d, VISop36_cmask32 = 0x01f,
230 VISop36_fcmple16 = 0x020, VISop36_fsll16 = 0x021,
231 VISop36_fcmpne16 = 0x022, VISop36_fsrl16 = 0x023,
232 VISop36_fcmple32 = 0x024, VISop36_fsll32 = 0x025,
233 VISop36_fcmpne32 = 0x026, VISop36_fsrl32 = 0x027,
234 VISop36_fcmpgt16 = 0x028, VISop36_fslas16 = 0x029,
235 VISop36_fcmpeq16 = 0x02a, VISop36_fsra16 = 0x02b,
236 VISop36_fcmpgt32 = 0x02c, VISop36_fslas32 = 0x02d,
237 VISop36_fcmpeq32 = 0x02e, VISop36_fsra32 = 0x02f,
238 VISop36_fmul8x16 = 0x031, VISop36_fmul8x16au = 0x033,
239 VISop36_fmul8x16al = 0x035, VISop36_fmul8sux16 = 0x036,
240 VISop36_fmul8ulx16 = 0x037, VISop36_fmuld8sux16 = 0x038,
241 VISop36_fmuld8ulx16 = 0x039, VISop36_fpack32 = 0x03a,
242 VISop36_fpack16 = 0x03b, VISop36_fpackfix = 0x03d,
243 VISop36_pdist = 0x03e, VISop36_pdistn = 0x03f,
244 VISop36_fmean16 = 0x040, VISop36_fpadd64 = 0x042,
245 VISop36_fchksm16 = 0x044, VISop36_fpsub64 = 0x046,
246 VISop36_fpmerge = 0x04b, VISop36_fexpand = 0x04d,
247 VISop36_bshuffle = 0x04c, VISop36_faligndata = 0x048,
248 VISop36_fpadd16 = 0x050, VISop36_fpadd16s = 0x051,
249 VISop36_fpadd32 = 0x052, VISop36_fpadd32s = 0x053,
250 VISop36_fpsub16 = 0x054, VISop36_fpsub16s = 0x055,
251 VISop36_fpsub32 = 0x056, VISop36_fpsub32s = 0x057,
252 VISop36_fpadds16 = 0x058, VISop36_fpadds16s = 0x059,
253 VISop36_fpadds32 = 0x05a, VISop36_fpadds32s = 0x05b,
254 VISop36_fpsubs16 = 0x05c, VISop36_fpsubs16s = 0x05d,
255 VISop36_fpsubs32 = 0x05e, VISop36_fpsubs32s = 0x05f,
256 VISop36_fzerod = 0x060, VISop36_fzeros = 0x061,
257 VISop36_fnord = 0x062, VISop36_fnors = 0x063,
258 VISop36_fandnot2d = 0x064, VISop36_fandnot2s = 0x065,
259 VISop36_fnot2d = 0x066, VISop36_fnot2s = 0x067,
260 VISop36_fandnot1d = 0x068, VISop36_fandnot1s = 0x069,
261 VISop36_fnot1d = 0x06a, VISop36_fnot1s = 0x06b,
262 VISop36_fxord = 0x06c, VISop36_fxors = 0x06d,
263 VISop36_fnandd = 0x06e, VISop36_fnands = 0x06f,
264 VISop36_fandd = 0x070, VISop36_fands = 0x071,
265 VISop36_fxnord = 0x072, VISop36_fxnors = 0x073,
266 VISop36_fsrc1d = 0x074, VISop36_fsrc1s = 0x075,
267 VISop36_fornot2d = 0x076, VISop36_fornot2s = 0x077,
268 VISop36_fsrc2d = 0x078, VISop36_fsrc2s = 0x079,
269 VISop36_fornot1d = 0x07a, VISop36_fornot1s = 0x07b,
270 VISop36_ford = 0x07c, VISop36_fors = 0x07d,
271 VISop36_foned = 0x07e, VISop36_fones = 0x07f,
272 VISop36_siam = 0x81, VISop36_movdtox = 0x110,
273 VISop36_movstouw = 0x111, VISop36_movstosw = 0x113,
274 VISop36_xmulx = 0x115, VISop36_xmulxhi = 0x116,
275 VISop36_movxtod = 0x118, VISop36_movwtos = 0x119,
276 VISop36_fucmple8 = 0x120, VISop36_fucmpne8 = 0x122,
277 VISop36_fucmpgt8 = 0x128, VISop36_fucmpeq8 = 0x12a,
278 VISop36_flcmps = 0x151, VISop36_flcmpd = 0x152
279} T3o3_fp36_opf_t;
280
281
282/*
283 * Table of opf fields for the op=3, op3=0x37 - Rock only
284 * fused multiply-add/sub floating point ops
285 */
286
287typedef enum {
288 FPop37_fmadds = 0x1, FPop37_fmaddd = 0x2,
289 FPop37_fmsubs = 0x5, FPop37_fmsubd = 0x6,
290 FPop37_fnmsubs = 0x9, FPop37_fnmsubd = 0xa,
291 FPop37_fnmadds = 0xd, FPop37_fnmaddd = 0xe
292} T3o3_fp37_op5_t;
293
294/*
295 * Table of opf fields for the op=3, op3=0x3f - Rock only
296 * unfused multiply-add/sub floating point ops
297 */
298
299typedef enum {
300 FPop3f_fumadds = 0x1, FPop3f_fumaddd = 0x2,
301 FPop3f_fumsubs = 0x5, FPop3f_fumsubd = 0x6,
302 FPop3f_fnumsubs = 0x9, FPop3f_fnumsubd = 0xa,
303 FPop3f_fnumadds = 0xd, FPop3f_fnumaddd = 0xe
304} T3o3_fp3f_op5_t;
305
306typedef enum {
307 Bcc_a = 0x8,
308 Bcc_n = 0x0,
309 Bcc_ne = 0x9,
310 Bcc_e = 0x1,
311 Bcc_g = 0xA,
312 Bcc_le = 0x2,
313 Bcc_ge = 0xB,
314 Bcc_l = 0x3,
315 Bcc_gu = 0xC,
316 Bcc_leu = 0x4,
317 Bcc_cc = 0xD,
318 Bcc_cs = 0x5,
319 Bcc_pos = 0xE,
320 Bcc_neg = 0x6,
321 Bcc_vc = 0xF,
322 Bcc_vs = 0x7
323} bcc_type_t;
324
325typedef enum {
326 FBcc_a = 0x8,
327 FBcc_n = 0x0,
328 FBcc_e = 0x9,
329 FBcc_ne = 0x1,
330 FBcc_ue = 0xA,
331 FBcc_lg = 0x2,
332 FBcc_ge = 0xB,
333 FBcc_ul = 0x3,
334 FBcc_uge = 0xC,
335 FBcc_l = 0x4,
336 FBcc_le = 0xD,
337 FBcc_ug = 0x5,
338 FBcc_ule = 0xE,
339 FBcc_g = 0x6,
340 FBcc_o = 0xF,
341 FBcc_u = 0x7
342} fbcc_type_t;
343
344
345typedef enum {
346 RCond_reserved_0x0 = 0x0,
347 RCond_z = 0x1,
348 RCond_lez = 0x2,
349 RCond_lz = 0x3,
350 RCond_reserved_0x4 = 0x4,
351 RCond_nz = 0x5,
352 RCond_gz = 0x6,
353 RCond_gez = 0x7
354} rcond_type_t;
355
356
357
358#if 0 /* { FIXME */
359/**/
360/* Support for the condition code computation*/
361/**/
362
363#define CCODE_BIT_C 0
364#define CCODE_BIT_V 1
365#define CCODE_BIT_Z 2
366#define CCODE_BIT_N 3
367
368#endif /* } */
369
370
371
372
373
374
375
376/*
377 * Support macros for the instruction decoder
378 */
379
380 /* this is for an instruction - so everything is uint32_t */
381 /* verify field [_e:_s] == 0 */
382
383#define RESERVED_FIELD(_e, _s) ( ((((uint32_t)0xffffffff)<<((_s)+31-(_e))) >> (31-(_e))) )
384#define CHECK_RESERVED_ZERO(_i, _e, _s) \
385 (( ((uint32_t)(_i)) & RESERVED_FIELD(_e, _s) ) == 0 )
386#define CHECK_RESERVED_ZERO2(_i, _e1, _s1, _e2, _s2) \
387 (( ((uint32_t)(_i)) & (RESERVED_FIELD(_e1, _s1) | \
388 RESERVED_FIELD(_e2, _s2)) ) == 0 )
389#define CHECK_RESERVED_ZERO3(_i, _e1, _s1, _e2, _s2, _e3, _s3) \
390 (( ((uint32_t)(_i)) & (RESERVED_FIELD(_e1, _s1) | \
391 RESERVED_FIELD(_e2, _s2) | RESERVED_FIELD(_e3, _s3)) ) == 0 )
392
393
394
395
396
397
398
399#define X_OP(_i) (((_i) >> 30) & 0x3)
400#define X_OP2(_i) (((_i) >> 22) & 0x7)
401#define X_OP3(_i) (((_i) >> 19) & 0x3f)
402#define X_FMT2_FCN(_i) (((_i) >> 25) & 0x3f)
403
404 /* 22bit immediate for seth_i */
405#define X_FMT2_IMM22(_i) ((_i) & 0x3FFFFF)
406
407 /* Register fields */
408#define X_RS1(_i) (((_i) >> 14) & 0x1f)
409#define X_RS2(_i) (((_i) >> 0) & 0x1f)
410#define X_RS3(_i) (((_i) >> 9) & 0x1f)
411#define X_RD(_i) (((_i) >> 25) & 0x1f)
412
413 /* Immediate bit */
414#define X_I(_i) (((_i) >> 13) & 0x1)
415
416 /* ASI number */
417#define X_ASI(_i) (((_i) >> 5) & 0xff)
418
419 /* Nasty set of shifting to ensure we extract sign extended correctly */
420#define X_SIMM13(_i) ((((int)(_i))<<(8*sizeof(int)-13))>>(8*sizeof(int)-13))
421#define X_SIMM11(_i) ((((int)(_i))<<(8*sizeof(int)-11))>>(8*sizeof(int)-11))
422#define X_SIMM10(_i) ((((int)(_i))<<(8*sizeof(int)-10))>>(8*sizeof(int)-10))
423
424
425#define X_SHIFT_SIZE_BIT(_i) (((_i) >> 12) & 0x1)
426
427#define X_SHIFT_IMM32(_i) ((_i) & 0x1f)
428#define X_SHIFT_IMM64(_i) ((_i) & 0x3f)
429
430 /* For call instruction */
431#define X_FMT1_DISP30(_i) ((_i) & 0x3fffffff)
432
433 /* For branches - the displacement, condition and annul bit */
434#define X_FMT2_DISP22(_i) ((_i) & 0x3FFFFF)
435#define X_FMT2_DISP19(_i) ((_i) & 0x7FFFF)
436#define X_FMT2_DISP16(_i) (((_i) & 0x3FFF) | (((_i)>>6) & 0xc000))
437#define X_ANNUL_BIT(_i) (((_i) >> 29) & 0x1)
438#define X_COND(_i) (((_i)>>25) & 0xf)
439#define X_RCOND(_i) (((_i)>>25) & 0x7)
440#define X_MOVRCOND(_i) (((_i)>>10) & 0x7)
441
442#define X_FMT3_RCOND(_i) (((_i) >> 10) & 0x7)
443
444#define X_FMT2_CC(_i) (((_i) >>20) & 0x3)
445typedef enum {
446 CC2bit_icc = 0x0,
447 CC2bit_xcc = 0x2
448} cc2bit_t;
449typedef enum {
450 FCC2bit_fcc0 = 0x0,
451 FCC2bit_fcc1 = 0x1,
452 FCC2bit_fcc2 = 0x2,
453 FCC2bit_fcc3 = 0x3
454} fcc2bit_t;
455
456#define X_FMT4_CC(_i) (((_i) >>11) & 0x3)
457typedef enum {
458 CC4bit_icc = 0x0,
459 CC4bit_xcc = 0x2
460} cc4bit_t;
461
462 /* For the conditional move instructions */
463
464#define X_FMT4_CC2(_i) (((_i)>>18)&1) /* =0 if FPCC =1 if ICC */
465#define X_FMT4_CC2a(_i) (((_i)>>13)&1) /* =0 if FPCC =1 if ICC */
466#define X_FMT4_COND(_i) (((_i)>>14)&0xf)
467
468#define X_MEMBAR_MASKS(_i) ((_i) & 0x7f)
469
470
471
472 /* Format 3 - done and retry instructions */
473
474#define FMT3_FCN_SHIFT 25
475#define FMT3_FCN_MASK_BITS 5
476#define FMT3_FCN_MASK_BASE ((1LL<<FMT3_FCN_MASK_BITS)-1)
477#define X_FMT3_FCN(_i) (((_i)>>FMT3_FCN_SHIFT)&FMT3_FCN_MASK_BASE)
478
479
480
481 /*
482 * Floating point instructions
483 */
484
485#define FMT3_FP_OPF_SHIFT 5
486#define FMT3_FP_OPF_MASK 0x1ff
487#define FMT3_FP_OP5_MASK 0xf
488#define X_FP_OPF( _i ) (((_i)>>FMT3_FP_OPF_SHIFT)&FMT3_FP_OPF_MASK)
489#define X_FP_OP5( _i ) (((_i)>>FMT3_FP_OPF_SHIFT)&FMT3_FP_OP5_MASK)
490#define X_FCOND(_i) (((_i)>>25) & 0x3)
491
492/* rescale reg num for fp double regs */
493#define RESCALEFPREG(_R) (_R) = ((_R) & 0x1e) | (((_R) & 1)<<5)
494
495 /*
496 * setup for the xicache processing
497 */
498
499#define SET_OP(_n) do { exec_funcp = decoded_impl_##_n ; } while (0)
500#define SET_OPv9(_n) do { exec_funcp = decoded_impl_sparcv9_##_n ; } while (0)
501
502#ifdef __cplusplus
503}
504#endif
505
506#endif /* _SPARCV9DECODE_H_ */
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