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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara2 / include / niagara2.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niagara2.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _NIAGARA2_H_
29#define _NIAGARA2_H_
30
31#pragma ident "@(#)niagara2.h 1.50 07/10/12 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#ifdef NIAGARA2 /* { */
38#include "niagara2_err_trap.h"
39
40#if INTERNAL_BUILD
41#include "stream_ma.h"
42#endif
43
44/*
45 * Niagara2 specific definitions
46 */
47#include "niagara2_device.h"
48
49/*
50 * This table describes the trap behaviour for Niagara2 ..
51 * based on the existing state (User, Priv, Hyper mode),
52 * and to which state the trap is to be delivered.
53 * Moreover, what is the priority of the trap type.
54 *
55 * The definition is based on N2 PRM, Rev. 1.0
56 */
57typedef enum {
58 SS_trap_NONE = -1,
59
60 SS_trap_legion_save_state = 0x0, /* Reserved on real HW */
61 SS_trap_power_on_reset = 0x1,
62 SS_trap_watchdog_reset = 0x2,
63 SS_trap_externally_initiated_reset = 0x3,
64 SS_trap_software_initiated_reset = 0x4,
65 SS_trap_RED_state_exception = 0x5,
66 /* 0x6 Reserved */
67 N2_trap_store_error = 0x7,
68 SS_trap_IAE_privilege_violation = 0x8,
69 SS_trap_instruction_access_MMU_miss = 0x9,
70 SS_trap_instruction_access_error = 0xa,
71 SS_trap_IAE_unauth_access = 0xb,
72 SS_trap_IAE_NFO_page = 0xc,
73 N2_trap_instruction_address_range = 0xd,
74 N2_trap_instruction_real_range = 0xe,
75 /* 0xf Reserved */
76 SS_trap_illegal_instruction = 0x10,
77 SS_trap_privileged_opcode = 0x11,
78 SS_trap_unimplemented_LDD = 0x12,
79 SS_trap_unimplemented_STD = 0x13,
80 SS_trap_DAE_invalid_ASI = 0x14,
81 SS_trap_DAE_privilege_violation = 0x15,
82 SS_trap_DAE_nc_page = 0x16,
83 SS_trap_DAE_NFO_page = 0x17,
84 /* 0x18-0x1f Reserved */
85 SS_trap_fp_disabled = 0x20,
86 SS_trap_fp_exception_ieee_754 = 0x21,
87 SS_trap_fp_exception_other = 0x22,
88 SS_trap_tag_overflow = 0x23,
89 SS_trap_clean_window = 0x24,
90 /* 0x25-0x27 clean_window reserved */
91 SS_trap_division_by_zero = 0x28,
92 SS_trap_internal_processor_error = 0x29,
93
94 SS_trap_instruction_invalid_TSB_entry = 0x2a,
95 SS_trap_data_invalid_TSB_entry = 0x2b,
96 /* 0x2c Reserved */
97 N2_trap_mem_real_range = 0x2d,
98 N2_trap_mem_address_range = 0x2e,
99 /* 0x2f Reserved */
100 SS_trap_DAE_so_page = 0x30,
101 SS_trap_data_access_MMU_miss = 0x31,
102 SS_trap_data_access_error = 0x32,
103 SS_trap_data_access_protection = 0x33,
104 SS_trap_mem_address_not_aligned = 0x34,
105 SS_trap_LDDF_mem_address_not_aligned = 0x35,
106 SS_trap_STDF_mem_address_not_aligned = 0x36,
107 SS_trap_privileged_action = 0x37,
108 SS_trap_LDQF_mem_address_not_aligned = 0x38,
109 SS_trap_STQF_mem_address_not_aligned = 0x39,
110 /* 0x3a Reserved */
111 N2_trap_unsupported_page_size = 0x3b,
112 N2_trap_control_word_queue_interrupt = 0x3c,
113 N2_trap_modular_arithmetic_interrupt = 0x3d,
114 SS_trap_instruction_real_translation_miss = 0x3e,
115 SS_trap_data_real_translation_miss = 0x3f,
116 SS_trap_sw_recoverable_error = 0x40,
117 SS_trap_interrupt_level_1 = 0x41,
118 SS_trap_interrupt_level_2 = 0x42,
119 SS_trap_interrupt_level_3 = 0x43,
120 SS_trap_interrupt_level_4 = 0x44,
121 SS_trap_interrupt_level_5 = 0x45,
122 SS_trap_interrupt_level_6 = 0x46,
123 SS_trap_interrupt_level_7 = 0x47,
124 SS_trap_interrupt_level_8 = 0x48,
125 SS_trap_interrupt_level_9 = 0x49,
126 SS_trap_interrupt_level_a = 0x4a,
127 SS_trap_interrupt_level_b = 0x4b,
128 SS_trap_interrupt_level_c = 0x4c,
129 SS_trap_interrupt_level_d = 0x4d,
130 SS_trap_interrupt_level_e = 0x4e,
131 SS_trap_interrupt_level_f = 0x4f,
132 /* SS_trap_pic_overflow = 0x4f,
133 * (shares TT 0x4f with interrupt_level_15)
134 */
135 /* 0x50-0x5d Reserved */
136 SS_trap_hstick_match = 0x5e,
137 SS_trap_trap_level_zero = 0x5f,
138 SS_trap_interrupt_vector_trap = 0x60,
139 SS_trap_RA_watchpoint = 0x61,
140 SS_trap_VA_watchpoint = 0x62,
141 SS_trap_hw_corrected_error = 0x63,
142 SS_trap_fast_instruction_access_MMU_miss = 0x64,
143 /* 0x65-0x67 Reserved */
144 SS_trap_fast_data_access_MMU_miss = 0x68,
145 /* 0x69-0x6b Reserved */
146 SS_trap_fast_data_access_protection = 0x6c,
147 /* 0x6d-0x6f Reserved */
148 /* 0x70 Reserved */
149 SS_trap_instruction_access_MMU_error = 0x71,
150 SS_trap_data_access_MMU_error = 0x72,
151 /* 0x73 Reserved */
152 SS_trap_control_transfer_instruction = 0x74,
153 SS_trap_instruction_VA_watchpoint = 0x75,
154 SS_trap_instruction_breakpoint = 0x76,
155 /* 0x77-0x7b Reserved */
156 SS_trap_cpu_mondo_trap = 0x7c,
157 SS_trap_dev_mondo_trap = 0x7d,
158 SS_trap_resumable_error = 0x7e,
159 SS_trap_nonresumable_error = 0x7f,
160
161 SS_trap_spill_0_normal = 0x80,
162 SS_trap_spill_1_normal = 0x84,
163 SS_trap_spill_2_normal = 0x88,
164 SS_trap_spill_3_normal = 0x8c,
165 SS_trap_spill_4_normal = 0x90,
166 SS_trap_spill_5_normal = 0x94,
167 SS_trap_spill_6_normal = 0x98,
168 SS_trap_spill_7_normal = 0x9c,
169
170 SS_trap_spill_0_other = 0xa0,
171 SS_trap_spill_1_other = 0xa4,
172 SS_trap_spill_2_other = 0xa8,
173 SS_trap_spill_3_other = 0xac,
174 SS_trap_spill_4_other = 0xb0,
175 SS_trap_spill_5_other = 0xb4,
176 SS_trap_spill_6_other = 0xb8,
177 SS_trap_spill_7_other = 0xbc,
178
179 SS_trap_fill_0_normal = 0xc0,
180 SS_trap_fill_1_normal = 0xc4,
181 SS_trap_fill_2_normal = 0xc8,
182 SS_trap_fill_3_normal = 0xcc,
183 SS_trap_fill_4_normal = 0xd0,
184 SS_trap_fill_5_normal = 0xd4,
185 SS_trap_fill_6_normal = 0xd8,
186 SS_trap_fill_7_normal = 0xdc,
187
188 SS_trap_fill_0_other = 0xe0,
189 SS_trap_fill_1_other = 0xe4,
190 SS_trap_fill_2_other = 0xe8,
191 SS_trap_fill_3_other = 0xec,
192 SS_trap_fill_4_other = 0xf0,
193 SS_trap_fill_5_other = 0xf4,
194 SS_trap_fill_6_other = 0xf8,
195 SS_trap_fill_7_other = 0xfc,
196
197 /* trap 0x100-0x17f, */
198 SS_trap_trap_instruction = 0x100,
199 /* htrap 0x180-0x1ff, */
200 SS_trap_htrap_instruction = 0x180,
201 SS_trap_illegal_value = 0x200
202} ss_trap_type_t;
203
204typedef struct TRAP_PRIORITY {
205 ss_trap_type_t trap_type;
206 char * trap_namep;
207 uint_t priority;
208 tflag_t from_user;
209 tflag_t from_priv;
210 tflag_t from_hyperpriv;
211} ss_trap_list_t;
212
213extern ss_trap_list_t ss_trap_list[];
214
215/*
216 * ASI's as implemented by Niagara2
217 *
218 * The definition is based on table 9-2, Chapter 9 of N2 PRM, Rev. 1.0
219 */
220typedef enum {
221 /* MANDATORY SPARC V9 ASIs */
222
223 SS_ASI_NUCLEUS = 0x4 , /* RW Implicit Address Space, nucleus context, TL>0 */
224 SS_ASI_NUCLEUS_LITTLE = 0xc , /* RW Implicit Address Space, nucleus context, TL>0 (LE) */
225 SS_ASI_AS_IF_USER_PRIMARY = 0x10, /* RW Primary Address Space, user privilege */
226 SS_ASI_AS_IF_USER_SECONDARY = 0x11, /* RW Secondary Address Space, user privilege */
227 SS_ASI_AS_IF_USER_PRIMARY_LITTLE = 0x18, /* RW Primary Address Space, user privilege (LE) */
228 SS_ASI_AS_IF_USER_SECONDARY_LITTLE = 0x19, /* RW Secondary Address Space, user privilege (LE) */
229 SS_ASI_PRIMARY = 0x80, /* RW Implicit Primary Address space */
230 SS_ASI_SECONDARY = 0x81, /* RW Implicit Secondary Address space */
231 SS_ASI_PRIMARY_NO_FAULT = 0x82, /* R Primary Address space, no fault */
232 SS_ASI_SECONDARY_NO_FAULT = 0x83, /* R Secondary Address space, no fault */
233 SS_ASI_PRIMARY_LITTLE = 0x88, /* RW Implicit Primary Address space (LE) */
234 SS_ASI_SECONDARY_LITTLE = 0x89, /* RW Implicit Secondary Address space (LE) */
235 SS_ASI_PRIMARY_NO_FAULT_LITTLE = 0x8A, /* R Primary Address space, no fault (LE) */
236 SS_ASI_SECONDARY_NO_FAULT_LITTLE = 0x8B, /* R Secondary Address space, no fault (LE) */
237
238 /* SunSPARC EXTENDED (non-V9) ASIs */
239
240 OLD_SS_ASI_PHYS_USE_EC = 0x14, /* RW physical address, non-allocating in L1 cache */
241 OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
242 SS_ASI_REAL_MEM = 0x14, /* RW physical address, non-allocating in L1 cache */
243 SS_ASI_REAL_IO = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
244 SS_ASI_BLOCK_AS_IF_USER_PRIMARY = 0x16, /* RW 64B block load/store, primary address space, user privilege */
245 SS_ASI_BLOCK_AS_IF_USER_SECONDARY = 0x17, /* RW 64B block load/store, secondary address space, user privilege */
246 OLD_SS_ASI_PHYS_USE_EC_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
247 OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
248 SS_ASI_REAL_MEM_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
249 SS_ASI_REAL_IO_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
250 SS_ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = 0x1E, /* RW 64B block load/store, primary address space, user privilege (LE) */
251 SS_ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = 0x1F, /* RW 64B block load/store, secondary address space, user privilege (LE) */
252 SS_ASI_SCRATCHPAD = 0x20, /* Scratchpad Registers */
253 SS_ASI_MMU = 0x21, /* MMU Registers */
254 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P = 0x22, /* Block initializing store/128b atomic LDDA, primary address, user privilege */
255 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S = 0x23, /* Block initializing store/128b atomic LDDA, secondary address, user privilege */
256 SS_ASI_QUAD_LDD = 0x24, /* 128b atomic LDDA */
257 SS_ASI_QUEUE = 0x25, /* Mondo Queue Pointers */
258 SS_ASI_QUAD_LDD_REAL = 0x26, /* 128b atomic LDDA, real address */
259 SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD = 0x27, /* Block initializing store/128b atomic LDDA */
260 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0x2A, /* Block initializing store/128b atomic LDDA, primary address, user priv (LE) */
261 SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0x2B, /* Block initializing store, secondary address, user privilege (LE) */
262 SS_ASI_QUAD_LDD_LITTLE = 0x2C, /* 128b atomic LDDA (LE) */
263 SS_ASI_QUAD_LDD_REAL_LITTLE = 0x2E, /* 128b atomic LDDA, real address (LE) */
264 SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE = 0x2F, /* Block initializing store/128b atomic LDDA (LE) */
265 SS_ASI_AS_IF_PRIV_PRIMARY = 0x30, /* FIXME - add support */
266 SS_ASI_AS_IF_PRIV_SECONDARY = 0x31, /* FIXME - add support */
267 SS_ASI_AS_IF_PRIV_NUCLEUS = 0x36, /* FIXME - add support */
268 SS_ASI_AS_IF_PRIV_PRIMARY_LITTLE = 0x38, /* FIXME - add support */
269 SS_ASI_AS_IF_PRIV_SECONDARY_LITTLE = 0x39, /* FIXME - add support */
270 SS_ASI_AS_IF_PRIV_NUCLEUS_LITTLE = 0x3E, /* FIXME - add support */
271 SS_ASI_STREAM_MA = 0x40, /* Asynchronous Streaming Control Register */
272 SS_ASI_CMP = 0x41, /* CMP Specific Register */
273 SS_ASI_LSU_DIAG_REG = 0x42, /* Diagnostic / Control register */
274 SS_ASI_ERROR_INJECT_REG = 0x43, /* Error Injection Register */
275
276 SS_ASI_LSU_CONTROL_REG = 0x45, /* Load/Store Unit Control Register */
277 SS_ASI_DCACHE_DATA = 0x46, /* Dcache data array diagnostics access */
278 SS_ASI_DCACHE_TAG = 0x47, /* Dcache tag and valid bit diagnostics access */
279 N2_ASI_IRF_ECC_REG = 0x48, /* IRF ECC diagnostic access */
280 N2_ASI_FRF_ECC_REG = 0x49, /* FRF ECC diagnostic access */
281 N2_ASI_STB_ACCESS = 0x4A, /* Store buffer diagnostic access */
282 N2_ASI_DESR = 0x4C, /* Disrupting Error Status Register */
283
284 N2_ASI_SPACE_PWR_MGMT = 0x4E, /* Sparc power management register */
285 SS_ASI_HYP_SCRATCHPAD = 0x4F, /* RW 0-38 Y Hypervisor Scratchpad */
286 SS_ASI_IMMU = 0x50, /* IMMU control register */
287 N2_ASI_MRA_ACCESS = 0x51, /* 0-FF8: Hardware Tablewalk MMU Register Array Access */
288 N2_ASI_MMU_REAL_RANGE = 0x52, /* 108-120: MMU TSB Real Range register 0,1,2,3
289 208-220: MMU TSB Physical Offset register 0, 1, 2, 3 */
290 N2_ITLB_PROBE = 0x53, /* ITBL Probe */
291 SS_ASI_ITLB_DATA_IN_REG = 0x54, /* IMMU data in register */
292 SS_ASI_ITLB_DATA_ACCESS_REG = 0x55, /* IMMU TLB Data Access Register */
293 SS_ASI_ITLB_TAG_READ_REG = 0x56, /* IMMU TLB Tag Read Register */
294 SS_ASI_IMMU_DEMAP = 0x57, /* IMMU TLB Demap */
295 SS_ASI_DMMU = 0x58, /* DMMU control register */
296 N2_SCRATCHPAD_ACCESS = 0x59, /* Scratchpad Register Diagnostic Access register */
297 N2_TICK_ACCESS = 0x5A, /* Tick Register Diagnostic Access register */
298 N2_TSA_ACCESS = 0x5B, /* TSA Diagnostic Access register */
299 SS_ASI_DTLB_DATA_IN_REG = 0x5C, /* DMMU data in register */
300 SS_ASI_DTLB_DATA_ACCESS_REG = 0x5D, /* DMMU TLB Data Access Register */
301 SS_ASI_DTLB_TAG_READ_REG = 0x5E, /* DMMU TLB Tag Read Register */
302 SS_ASI_DMMU_DEMAP = 0x5F, /* DMMU TLB Demap */
303 SS_ASI_CMP_CORE_INTR_ID = 0x63, /* 0: Core Interrupt ID
304 10: Core ID */
305 SS_ASI_ICACHE_INSTR = 0x66, /* Icache data array diagnostics access */
306 SS_ASI_ICACHE_TAG = 0x67, /* Icache tag and valid bit diagnostics access */
307 N2_ASI_INTR_RECEIVE = 0x72, /* Interrupt Receive Register */
308 N2_ASI_INTR_W = 0x73, /* Interrupt Vector Dispatch Register */
309 N2_ASI_INTR_R = 0x74, /* Incoming Vector Register */
310
311 SS_ASI_PST8_P = 0xC0, /* 8 bit partial pri */
312 SS_ASI_PST8_S = 0xC1, /* 8 bit partial sec */
313 SS_ASI_PST16_P = 0xC2, /* 16 bit partial pri */
314 SS_ASI_PST16_S = 0xC3, /* 16 bit partial sec */
315 SS_ASI_PST32_P = 0xC4, /* 32 bit partial pri */
316 SS_ASI_PST32_S = 0xC5, /* 32 bit partial sec */
317 SS_ASI_PST8_PL = 0xC8, /* 8 bit partial pri LE */
318 SS_ASI_PST8_SL = 0xC9, /* 8 bit partial sec LE */
319 SS_ASI_PST16_PL = 0xCA, /* 16 bit partial pri LE */
320 SS_ASI_PST16_SL = 0xCB, /* 16 bit partial sec LE */
321 SS_ASI_PST32_PL = 0xCC, /* 32 bit partial pri LE */
322 SS_ASI_PST32_SL = 0xCD, /* 32 bit partial sec LE */
323
324 SS_ASI_FL8_P = 0xD0, /* float 8 bit partial pri */
325 SS_ASI_FL8_S = 0xD1, /* float 8 bit partial sec */
326 SS_ASI_FL16_P = 0xD2, /* float 16 bit partial pri */
327 SS_ASI_FL16_S = 0xD3, /* float 16 bit partial sec */
328 SS_ASI_FL8_PL = 0xD8, /* float 8 bit partial pri LE*/
329 SS_ASI_FL8_SL = 0xD9, /* float 8 bit partial sec LE*/
330 SS_ASI_FL16_PL = 0xDA, /* float 16 bit partial pri LE */
331 SS_ASI_FL16_SL = 0xDB, /* float 16 bit partial sec LE */
332
333 SS_ASI_BLK_COMMIT_P = 0xE0, /* any type of access causes data_access_exception */
334 SS_ASI_BLK_COMMIT_S = 0xE1, /* any type of access causes data_access_exception */
335 SS_ASI_BLK_INIT_ST_QUAD_LDD_P = 0xE2, /* Block initializing store/128b atomic LDDA, primary address */
336 SS_ASI_BLK_INIT_ST_QUAD_LDD_S = 0xE3, /* Block initializing store/128b atomic LDDA, secondary address */
337 SS_ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0xEA, /* Block initializing store/128b atomic LDDA, primary address (LE) */
338 SS_ASI_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0xEB, /* Block initializing store/128b atomic LDDA, secondary address (LE) */
339 SS_ASI_BLK_P = 0xF0, /* 64B block load/store, primary address */
340 SS_ASI_BLK_S = 0xF1, /* 64B block load/store, secondary address */
341 SS_ASI_BLK_PL = 0xF8, /* 64B block load/store, primary address (LE) */
342 SS_ASI_BLK_SL = 0xF9 /* 64B block load/store, secondary address (LE) */
343
344} ss_asi_t;
345
346/*
347 * I/D-Cache size
348 */
349#define SS_ICACHE_SIZE 0x4000 /* 16K instn cache with 32B lines */
350#define SS_DCACHE_SIZE 0x2000 /* 8K data cache with 16B lines */
351
352/*
353 * L1 I-Cache Diagnostic Access, table 28-8,10, sections 28.5 of N2 PRM, Rev. 1.0
354 * (different from N1)
355 */
356#define SS_ICACHE_DATA_LINEWORD_BITS 0xff8 /* line[11:6]word[5:3]rsv2[2:0]*/
357#define SS_ICACHE_DATA_WAY_BITS 0x7000 /* way[14:12] */
358#define SS_ICACHE_TAG_LINE_BITS 0xfc0 /* line[11:6]rsvd2[5:0] */
359#define SS_ICACHE_TAG_WAY_BITS 0x7000 /* way[14:12] */
360
361/*
362 * D-Cache Diagnostic Access Sections 28.6 of N2 PRM, Rev. 1.0
363 * (same as N1)
364 */
365#define SS_DCACHE_DATA_BITS 0x1ff8 /* way[12:11]line[10:4]word[3]rsv2[2:0] */
366#define SS_DCACHE_DATA_TAG_BITS 0x7ffffff800 /* tag[39:11] */
367#define SS_DCACHE_TAG_WAYLINE_BITS 0x1ff0 /* way[12:11]line[10:4]rsvd1[3:0] */
368
369/*
370 * Macros used to map strands (virtual cores) into internal strands:
371 * core = num / 8;
372 * strand = num % 8;
373 * idx = str_to_idx[num]
374 */
375#define STRANDSPERCORE 8 /* architectural, needed to match registers */
376#define CORESPERCHIP 8
377#define STRANDS_PER_CHIP (STRANDSPERCORE * CORESPERCHIP)
378#define VALID_CORE_MASK 0xffffffffffffffffull
379#define NO_STRAND ((uint_t)-1)
380#define STRANDID2IDX(npp, s) \
381 (((uint_t)(s) < STRANDS_PER_CHIP) ? (npp)->str_to_idx[s] : NO_STRAND)
382#define VALIDIDX(npp, tidx) \
383 ((uint_t)(tidx) != NO_STRAND)
384
385/*
386 * MMU TSB config register for Niagara 2
387 */
388typedef struct {
389 uint64_t data; /* 64 bit value of the register */
390 bool_t enable; /* bit 63 */
391 bool_t use_context_0; /* bit 62 */
392 bool_t use_context_1; /* bit 61 */
393 tvaddr_t tsb_base; /* bits <39:13> */
394 bool_t ra_not_pa; /* bit 8 */
395 uint_t page_size; /* bits <6:4> */
396 uint_t tag_match_shift;
397 uint_t tsb_size; /* bits <3:0> */
398 uint8_t *tsb_base_sim; /* in sim tsb_base */
399} ss_tsb_info_t;
400
401#define INVALID_SCRATCHPAD(addr) \
402 (((addr)>=0x20 && (addr)<=0x2f) || ((addr)>=0x3f))
403#define INVALID_HYP_SCRATCHPAD(addr) ((addr)>=0x3f)
404#define SSR_HSCRATCHPAD_INDEX (SSR_ScratchPad0)
405
406/*
407 * per strand mmu registers for Niagara 2
408 */
409struct SS_MMU {
410 bool_t enabled; /* force real or virtual translations in priv/user mode */
411 bool_t is_immu; /* indicate IMMU or DMMU translation */
412 tvaddr_t fault_addr;
413 uint64_t tag_access_reg; /* content of ASI_MMU_TAG_ACCESS */
414 uint64_t watchpoint;
415};
416
417
418/*
419 * Four types of demap operation are provided for Niagara 2
420 */
421enum SS_DEMAP {
422 NA_demap_page = 0x0,
423 NA_demap_context = 0x1,
424 NA_demap_all = 0x2,
425 NA_demap_all_page = 0x3
426};
427
428/*
429 * Error registers specific for Niagara 2
430 */
431struct SS_ERROR {
432 uint8_t isfsr; /* IMMU synchronous fault status, ASI=0x50, VA=0x18 */
433 uint8_t dsfsr; /* DMMU synchronous fault status, ASI=0x58, VA=0x18 */
434 uint64_t desr; /* disrupting error status, ASI=0x4C, VA=0x0 */
435 uint64_t dfesr; /* deferred error status, ASI=0x4C, VA=0x8 */
436 tvaddr_t dsfar; /* synchronous fault address, ASI=0x58, VA=0x18 */
437 uint64_t cerer; /* core error recording enable ASI=0x4C, VA=0x10 */
438 uint64_t inject;
439};
440
441#if ERROR_INJECTION
442#include "niagara2_error.h"
443#endif
444
445/*
446 * macros used to determine the virtual core and strand Ids for Niagara 2
447 */
448#define SS_COREID_SHIFT 3
449#define SS_STRANDID_MASK MASK64(2,0) /* strand Id stored in bits 2:0 */
450
451/*
452 * Strand structure for Niagara 2
453 */
454typedef struct SS_STRAND {
455 ss_trap_type_t pending_precise_tt;
456 ss_trap_type_t pending_async_tt;
457 bool_t flag_queue_irq[4]; /* see na_qnum_t */
458 na_queue_t nqueue[4]; /* see na_qnum_t */
459
460 bool_t mmu_bypass; /* no translation if hpstate in RED or HPriv modes */
461
462 /* IRQ lock is used whenever a irq vector bit needs
463 * to be set or cleared. Pre examining irq_vector
464 * should not require holding the lock, but
465 * attention must be set *after* vector modification.
466 */
467 pthread_mutex_t irq_lock;
468 uint64_t irq_vector; /* bit63 = highest priority */
469#define INTR_VEC_MASK MASK64(5,0)
470
471 uint16_t pri_context; /* primary context 0 */
472 uint16_t sec_context; /* secondary context 0 */
473 uint16_t pri_context1; /* primary context 1 */
474 uint16_t sec_context1; /* secondary context 1 */
475 uint16_t partid; /* partition ID */
476
477 SS_CORE_NUM_FIELDS
478
479 uint8_t hwtw_config; /* hardware tablewalk config */
480 uint64_t real_range_reg[4]; /* real range (RPN -> PPN) */
481 uint64_t phy_off_reg[4]; /* physical offset */
482 uint64_t itlb_probe; /* itlb probe */
483
484 uint64_t strand_reg[SSR_Num_Regs];
485
486 ss_tsb_info_t mmu_zero_ctxt_tsb_config[4]; /* zero context tsb config */
487 ss_tsb_info_t mmu_nonzero_ctxt_tsb_config[4]; /* nonzero context tsb config */
488
489 ss_tlb_t * dtlbp; /* the D-TLB this strand uses */
490 ss_tlb_t * itlbp; /* the I-TLB this strand uses */
491
492 /* the MMU fault status registers ... */
493 ss_mmu_t dmmu;
494 ss_mmu_t immu;
495
496 ss_l1_cache_t * icachep; /* the instn cache this strand uses */
497 ss_l1_cache_t * dcachep; /* the data cache this strand uses */
498
499#if ERROR_TRAP_GEN /* { */
500 cpu_error_reg_t *cpu_err_regp;
501#endif /* } ERROR_TRAP_GEN */
502
503 /* Error handling registers */
504 ss_error_t error;
505
506 /* Other control registers */
507 uint64_t lsu_control_raw;
508
509 /*
510 * per CPU performance counters
511 */
512 uint32_t pic0;
513 uint32_t pic1;
514 uint64_t pcr;
515 uint64_t pic0_sample_base;
516 uint64_t pic1_sample_base;
517} ss_strand_t;
518
519
520/*
521 * ASI_CMP registers shared by each Niagara 2 physical core
522 */
523typedef struct NIAGARA2_CMP_REGS {
524 uint64_t core_enable_status;
525 uint64_t xir_steering;
526 bool_t tick_enable;
527 uint64_t core_running_status;
528} niagara2_cmp_regs_t;
529
530 /*
531 * Niagara2 processor itself - composed of strands, TLBs and
532 * other state.
533 */
534typedef uint64_t sparc_power_mgmt_t;
535
536#ifdef VFALLS /* { */
537 typedef union {
538 uint32_t all;
539 struct {
540 uint8_t rsvd;
541 uint8_t multi_chip;
542 uint8_t lfu;
543 uint8_t zambezi;
544 } flags;
545 } global_add_stat_t;
546
547#define GLOBAL_ADDRESSING_FLAG_EN 0xff
548#define GLOBAL_ADDRESSING_FLAG_DIS 0x0
549#define GLOBAL_ADDRESSING_ENABLE 0xffffffff
550
551#define GLOBAL_ADDRESSING_CHECK(_osp, _pseudo_dev) do { \
552 ss_proc_t *onpp; \
553 onpp = (ss_proc_t *)_osp->config_procp->procp; \
554 if (onpp->global_addressing_ok.all < GLOBAL_ADDRESSING_ENABLE) { \
555 fatal ("[0x%llx] (pc=0x%llx)\tGlobal addressing of "_pseudo_dev \
556 " not allowed. Please check that this is a multinode " \
557 "config and lfu and (optionally) Zambezi registers " \
558 "are correctly setup.\n", _osp->gid, _osp->pc); \
559 } \
560 } while (0)
561#endif /* } */
562
563struct SS_PROC {
564 config_proc_t * config_procp; /* points back to generic type */
565
566 /* data private for a Niagara2 cpu */
567 uint64_t clkfreq;
568 uint64_t core_mask;
569 uint_t nwins;
570 uint_t nglobals;
571 uint_t maxtl;
572 uint64_t ver;
573 bool_t has_fpu;
574 bool_t crypto_synchronous;
575
576 tvaddr_t rstv_addr; /* Red State Trap Vector base - copied into v9 info */
577
578 uint_t str_to_idx[STRANDS_PER_CHIP]; /* strand/ss_strandp idx */
579 uint_t nstrands; /* array size for strand/ss_strandp */
580 sparcv9_cpu_t** strand;
581
582 /* linear array of strand specific info for this Niagara2 proc */
583 ss_strand_t * ss_strandp;
584
585 sparc_power_mgmt_t *sparc_power_mgmtp; /* array of power mgmt registers/asis - one per core */
586
587 niagara2_cmp_regs_t cmp_regs; /* CMP registers, each shared by all virtual cores */
588 pthread_mutex_t cmp_lock;
589
590 bool_t tick_stop;
591 pthread_mutex_t tick_en_lock;
592
593 uint_t nitlb;
594 uint_t ndtlb;
595 ss_tlb_t * itlbp; /* linear array of I tlbs - one per core */
596 ss_tlb_t * dtlbp; /* linear array of D tlbs - one per core */
597
598 ss_tlb_spec_t itlbspec; /* parsed spec for each TLB ... */
599 ss_tlb_spec_t dtlbspec; /* contains duplicated fields FIXME */
600
601 ss_l1_cache_t * icachep; /* linear array of icaches - 1/core */
602 ss_l1_cache_t * dcachep; /* linear array of dcaches - 1/core */
603#if INTERNAL_BUILD
604 asi_stream_CWQ_t * stream_cwq_p; /* linear array of stream units */
605 asi_stream_MA_t * mod_arith_p; /* linear array of mod_arith units */
606#endif
607
608 bool_t is_inited; /* set once allocated simcpu_t for each strand */
609
610 /* JTAG registers. Note that these are aliases for ASI's*/
611 config_dev_t *jtag_devp;
612
613#ifdef VFALLS /* { */
614 /* NCX registers */
615 ncx_t *ncxp;
616 config_dev_t *ncx_devp;
617
618 /* LFU registers */
619 lfu_t *lfup;
620 config_dev_t *lfu_devp;
621
622 /* COU registers */
623 cou_t *coup;
624 config_dev_t *cou_devp;
625
626 global_add_stat_t global_addressing_ok;
627
628#endif /* } VFALLS */
629 /* SSI registers */
630 ssi_t *ssip;
631 config_dev_t *ssi_devp; /* pseudo device for SSI regs */
632
633 /* NCU registers */
634 ncu_t *ncup;
635 config_dev_t *ncu_devp; /* pseudo device for NCU regs */
636
637 /* Clock unit registers */
638 ccu_t *clockp;
639 config_dev_t *clock_devp; /* pseudo device for clock unit regs */
640
641 /* HW Debug unit registers */
642 hwdbg_t *hwdbgp;
643 config_dev_t *hwdbg_devp; /* pseudo device for debug unit regs */
644
645 /* Reset unit registers */
646 rcu_t *rcup;
647 config_dev_t *rcu_devp; /* pseudo device for reset unit regs */
648
649 /* L2 Cache controllers */
650 uint_t num_l2banks;
651 l2c_t *l2p;
652 config_dev_t *l2c_devp; /* pseudo device for l2 controller regs */
653
654 /* Memory controllers */
655 uint_t num_mbanks;
656 mcu_bank_t *mbankp;
657 config_dev_t *mcu_devp; /* pseudo device for dram ctrl regs */
658
659 error_conf_t * pend_errlistp; /* processor list of pending errors */
660 pthread_mutex_t err_lock;
661 bool_t error_check;
662 error_proc_t * errorp;
663
664 proc_debug_t proc_debug;
665
666#if ERROR_TRAP_GEN /* { */
667 ss_error_state_t ss_err_state; /* error framework state */
668 cpu_error_state_t *cpu_err_statep; /* CPU specific state */
669#endif /* } ERROR_TRAP_GEN */
670
671
672};
673
674
675/*
676 * macros used in MMU area
677 */
678/* For the moment, ISFSR and DSFSR have the same bit mask. */
679#define MMU_SFSR_MASK MASK64(3,0)
680
681#define DEFAULT_ITLB_ENTRIES 64
682#define DEFAULT_DTLB_ENTRIES 128
683#define SS_TLB_REAL_MASK MASK64(10,10)
684#define SS_TLB_IS_REAL(n) (bool_t)(((uint64_t)n >> 10) & 0x1)
685
686/* Inserting RA to PA translations forces this context value */
687#define NIAGARA2_REAL_CONTEXT 3
688
689/*
690 * chip-specific macros used for determing the fields of sun4v TTE format
691 */
692#define N2_TTET_RSVD0 MASK64(63, 61)
693#define N2_TTET_RSVD1 MASK64(47, 42)
694#define SUN4V_TTET_RSVD(n) ((uint64_t)n & (N2_TTET_RSVD0|N2_TTET_RSVD1))
695#define SUN4V_TTET_CTXT(n) (((uint64_t)n & MASK64(60, 48)) >> 48)
696#define SUN4V_TTED_RA(n) ((uint64_t)n & MASK64(55, 13))
697
698#define SUN4V_PN_UBIT 39
699#define SUN4V_PN_LBIT 13
700#define SUN4V_PN_MASK MASK64(SUN4V_PN_UBIT, SUN4V_PN_LBIT)
701
702#define UPDATE_MMU_TAG_ACCESS(_mmup, _va, _ctx) do{\
703 (_mmup)->tag_access_reg = (VA48(_va) & MASK64(63,13)) | ((_ctx) & MASK64(12,0));\
704 DBGMMU( lprintf(sp->gid, "%cMMU tag access = 0x%llx\n", (_mmup)->is_immu ? 'I' : 'D', (_mmup)->tag_access_reg); ); \
705 } while (0)
706
707#define NIAGARA2_DATA_ACCESS_PAR_BIT 61
708
709#define NIAGARA2_DATA_IN_MASK (MASK64(63,62) | MASK64(39,13) | \
710 MASK64(12,10) | MASK64(8,8) | MASK64(6,6) | MASK64(3,0))
711#define NIAGARA2_DATA_ACCESS_MASK ((1ull << NIAGARA2_DATA_ACCESS_PAR_BIT) | \
712 NIAGARA2_DATA_IN_MASK)
713
714/*
715 * macros used to calculate the phys addr of an TTE entry in the TSB
716 *
717 * ps: refers to page_size field of the TSB config register
718 * n: refers to tsb_size field of the TSB config register
719 */
720#define SUN4V_PAGE_OFFSET(ps) (uint_t)((SUN4V_PN_LBIT + 3*(ps)))
721#define SUN4V_VPN_MASK(ps) MASK64(47, SUN4V_PAGE_OFFSET(ps));
722#define SUN4V_TTE_IDX_MASK(n,ps) MASK64((21+(n)+3*(ps)),SUN4V_PAGE_OFFSET(ps))
723#define SUN4V_TSB_BASE_MASK(n) MASK64(SUN4V_PN_UBIT, 13+(n))
724
725
726
727#define SET_DTLB_FAULT(_nsp, _va) do{ (_nsp)->dmmu.fault_addr = (_va); } while (0)
728#define SET_ITLB_FAULT(_nsp, _va) do{ (_nsp)->immu.fault_addr = (_va); } while (0)
729
730/*
731 * niagara 2 function prototypes
732 */
733void niagara2_write_tsb_config(simcpu_t*, ss_tsb_info_t *tsb_config_reg, uint64_t data);
734
735/*
736 * external function prototypes used in this file
737 */
738extern ss_trap_type_t ss_tlb_insert(simcpu_t*, ss_mmu_t*, ss_tlb_t*, uint_t, bool_t, uint64_t, uint_t*, uint64_t*);
739extern ss_trap_type_t ss_tlb_insert_idx(simcpu_t*, ss_mmu_t*, ss_tlb_t*, uint_t, bool_t, uint64_t, uint_t);
740extern void ss_setup_pseudo_devs(domain_t *domainp, ss_proc_t *procp);
741
742/* Processor specific parsing for "proc" elements in config file */
743extern bool_t ss_parse_proc_entry(ss_proc_t*, domain_t *);
744
745/*
746 * default CPU version values
747 * from NG2 PRM rev 1.0, section 3.4.5
748 */
749#define SS_VER_MANUF 0x003eULL
750#define SS_VER_IMPL 0x0024ULL
751#ifdef VFALLS /* { */
752#define SS_VER_MASK 0x0028ULL
753#else /* N2 */
754#define SS_VER_MASK 0x0020ULL
755#endif /* } VFALLS */
756#define SS_VER_MAXGL 3
757#define SS_VER_MAXTL 6
758#define SS_VER_MAXWIN 7
759
760#ifdef VFALLS
761#define MAX_NODEID 0x3
762#endif
763
764/*
765 * %pcr
766 */
767#define SS_PCR_PRIV BIT(0)
768#define SS_PCR_ST BIT(1)
769#define SS_PCR_UT BIT(2)
770#define SS_PCR_HT BIT(3)
771#define SS_PCR_TOE0 BIT(4)
772#define SS_PCR_TOE1 BIT(5)
773#define SS_PCR_MASK0_SHIFT 6
774#define SS_PCR_MASK0 MASK64(13,SS_PCR_MASK0_SHIFT)
775#define SS_PCR_SL0_SHIFT 14
776#define SS_PCR_SL0 MASK64(17,SS_PCR_SL0_SHIFT)
777#define SS_PCR_OV0 BIT(18)
778#define SS_PCR_MASK1_SHIFT 19
779#define SS_PCR_MASK1 MASK64(26,SS_PCR_MASK0_SHIFT)
780#define SS_PCR_SL1_SHIFT 27
781#define SS_PCR_SL1 MASK64(30,SS_PCR_SL0_SHIFT)
782#define SS_PCR_OV1 BIT(31)
783
784#define SS_PCR_UT_ST (SS_PCR_UT | SS_PCR_ST)
785#define SS_PCR_MASK MASK64(31,0)
786#define SS_PCR_CLEAR_ON_READ (SS_PCR_OV1 | SS_PCR_OV0)
787
788#define SS_PCR_TEST_OVF_PENDING(_pcr) \
789 (((_pcr) & (SS_PCR_OV0 | SS_PCR_TOE0)) == (SS_PCR_OV0 | SS_PCR_TOE0) || \
790 ((_pcr) & (SS_PCR_OV1 | SS_PCR_TOE1)) == (SS_PCR_OV1 | SS_PCR_TOE1))
791
792#endif /* } NIAGARA2 */
793
794#ifdef __cplusplus
795}
796#endif
797
798#endif /* _NIAGARA2_H_ */
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