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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara2 / include / niagara2_device.h
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niagara2_device.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _NIAGARA2_DEVICE_H
29#define _NIAGARA2_DEVICE_H
30
31#pragma ident "@(#)niagara2_device.h 1.27 07/09/18 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#include "device.h"
38
39#define GETMASK64(x, hi, lo) (((uint64_t)(x) & MASK64((hi), (lo)))>>(lo))
40
41/* IO Device Physical Address map that is common to N2 and VF */
42
43#define PHYS_ADDR_NCU 0x8000000000
44#define PHYS_ADDR_CCU 0x8300000000
45#define PHYS_ADDR_MCU 0x8400000000
46#define PHYS_ADDR_HWDBG 0x8600000000
47#define PHYS_ADDR_DMU 0x8800000000
48#define PHYS_ADDR_RCU 0x8900000000
49#define PHYS_ADDR_L2C 0xA000000000
50#define PHYS_ADDR_PIU_LB 0xC000000000
51#define PHYS_ADDR_PIU_UB 0xCF00000000
52#define PHYS_ADDR_SSI 0xFF00000000
53#define PHYS_ADDR_JTAG 0x9000000000
54
55#define NCU_RANGE 0x100000000
56#define CCU_RANGE 0x100000000
57#define L2C_RANGE 0x2000000000
58#define SSI_RANGE 0x10000000 /* Note this covers only the SSI CSR space and not the boot ROM.
59 Boot ROM is taken care of by the conf file */
60#define RCU_RANGE 0x100000000
61#define JTAG_RANGE 0x100000000
62
63#ifdef VFALLS /* { */
64
65#define PHYS_ADDR_NCX 0x8100000000
66#define PHYS_ADDR_COU 0x8110000000
67#define PHYS_ADDR_LFU 0x8120000000
68#define PHYS_ADDR_ZAM 0x8130000000
69
70#define PCIADDR2NODE(addr) ((addr & MASK64(35,34)) >> 34)
71
72#define NCX_RANGE 0x10000000
73#define COU_RANGE 0x10000000
74#define LFU_RANGE 0x10000000
75
76#define PHYS_ADDR_NCU_REMOTE(_node_id) (0xE000000000 + (_node_id * 0x400000000))
77#define PHYS_ADDR_CCU_REMOTE(_node_id) (0xE300000000 + (_node_id * 0x400000000))
78#define PHYS_ADDR_MCU_REMOTE(_node_id) (0xD000000000 + (_node_id * 0x400000000))
79#define PHYS_ADDR_DMU_REMOTE(_node_id) (0xD200000000 + (_node_id * 0x400000000))
80#define PHYS_ADDR_RCU_REMOTE(_node_id) (0xD300000000 + (_node_id * 0x400000000))
81#define PHYS_ADDR_PIU_REMOTE(_node_id) (0xC000000000 + (_node_id * 0x400000000))
82#define PHYS_ADDR_JTAG_REMOTE(_node_id) (0x9200000000 + (_node_id * 0x400000000))
83#define PHYS_ADDR_NCX_REMOTE(_node_id) (0xE100000000 + (_node_id * 0x400000000))
84#define PHYS_ADDR_COU_REMOTE(_node_id) (0xE110000000 + (_node_id * 0x400000000))
85#define PHYS_ADDR_LFU_REMOTE(_node_id) (0xE120000000 + (_node_id * 0x400000000))
86
87#define MAGIC_SSI 0xFFFFFF0000 /* Magic SSI address where SYS_MODE_REG info is stored
88 for consumption by reset(dumb and standalone) */
89
90#else /* N2 */
91/*
92 * N2 specific IO device physical addess map
93 */
94
95#define PHYS_ADDR_NIU 0x8100000000
96
97#endif /* } VFALLS */
98
99#define PSEUDO_DEV_NAME_NCU "ncu"
100#define PSEUDO_DEV_NAME_CCU "ccu" /* clock unit */
101#define PSEUDO_DEV_NAME_MCU "mcu" /* dram */
102#define PSEUDO_DEV_NAME_L2C "l2c" /* L2 Control */
103#define PSEUDO_DEV_NAME_SSI "ssi"
104#define PSEUDO_DEV_NAME_HWDBG "hwdbg" /* Hardware debug */
105#define PSEUDO_DEV_NAME_RCU "rcu" /* Reset Unit */
106#define PSEUDO_DEV_NAME_JTAG "jtag" /* JTAG/TAP region */
107#ifdef VFALLS /* { */
108#define PSEUDO_DEV_NAME_NCX "ncx" /* Non-cache Crossbar region */
109#define PSEUDO_DEV_NAME_COU "cou" /* Coherency Unit */
110#define PSEUDO_DEV_NAME_LFU "lfu" /* Link Framing Unit */
111#endif /* } VFALLS */
112
113#define PHYS_ADDR_MASK 0xFF00000000
114
115/*
116 * NCU address mapped registers (MSB[39:32] = 0x80)
117 */
118#define NCU_TARGETS 64 /* number of virtual cores */
119#define NCU_DEV_MAX 128 /* max number of device Ids */
120#define NCU_DEV_ERR 1 /* device Id for ECC error */
121#define NCU_DEV_SSI 2 /* device Id for SSI interrupt */
122
123#define NCU_DEV_NIU_LB 64 /* device Id range for NIU interrupt */
124#define NCU_DEV_NIU_UB NCU_DEV_MAX-1
125
126#define NCU_INT_MAN_CPUID(n) (((n) & MASK64(13, 8)) >> 8)
127#define NCU_INT_ACK 0
128#define NCU_INT_NACK -1
129
130#define NCU_INT_TGTOFFSET_MASK ((NCU_TARGETS * 8) - 1)
131
132#define NCU_MONDO_INT_MASK 0x40fff
133#define NCU_MONDO_INT_BUSY MASK64(6,6)
134
135#define NCU_REG_MASK 0x4ffff
136#define NCU_SOC_MASK MASK64(42,40)|MASK64(38,37)|MASK64(35,34)|MASK64(32,31)|MASK64(29,0)
137
138#define UINT64_RANGE_CHECK(_low, _val, _high) \
139 (((uint64_t)(_val) - (uint64_t)(_low)) < ((uint64_t)(_high) - (uint64_t)(_low)))
140
141typedef enum {
142 INT_MAN = 0x00000,
143 MONDO_INT_VEC = 0x00a00,
144 SER_NUM = 0x01000,
145 EFU_STAT = 0x01008,
146 CORE_AVAIL = 0x01010, /* same as ASI_CORE_AVAILABLE */
147 BANK_AVAIL = 0x01018,
148 BANK_ENABLE = 0x01020,
149 BANK_ENABLE_STATUS = 0x01028,
150 L2_IDX_HASH_EN = 0x01030,
151 L2_IDX_HASH_EN_STATUS = 0x01038,
152 PCIE_A_MEM32_OFFSET_BASE = 0x02000,
153 PCIE_A_MEM32_OFFSET_MASK = 0x02008,
154 PCIE_A_MEM64_OFFSET_BASE = 0x02010,
155 PCIE_A_MEM64_OFFSET_MASK = 0x02018,
156 PCIE_A_IOCON_OFFSET_BASE = 0x02020,
157 PCIE_A_IOCON_OFFSET_MASK = 0x02028,
158 PCIE_A_FSH = 0x02030,
159 SOC_ESR = 0x03000,
160 SOC_LOG_ENABLE = 0x03008,
161 SOC_INTERRUPT_ENABLE = 0x03010,
162 SOC_ERROR_INJECTION = 0x03018,
163 SOC_FATAL_ERROR_ENABLE = 0x03020,
164 SOC_PENDING_ERROR_STATUS = 0x03028, /* same as SOC_ESR */
165 SOC_SII_ERROR_SYNDROME = 0x03030,
166 SOC_NCU_ERROR_SYNDROME = 0x03038,
167 MONDO_INT_DATA0 = 0x40000,
168 MONDO_INT_DATA1 = 0x40200,
169 MONDO_INT_ADATA0 = 0x40400,
170 MONDO_INT_ADATA1 = 0x40600,
171 MONDO_INT_BUSY = 0x40800,
172 MONDO_INT_ABUSY = 0x40a00
173} ncu_reg_offset_t;
174
175typedef struct {
176 uint64_t int_man[NCU_DEV_MAX];
177 uint64_t mondo_int_vec;
178 uint64_t ser_num;
179 uint64_t efu_stat;
180 uint64_t bank_enb;
181 uint64_t bank_enb_stat;
182 bool_t l2_idx_hash_en_stat;
183 uint64_t pcie_a_mem32_offset_base;
184 uint64_t pcie_a_mem32_offset_mask;
185 uint64_t pcie_a_mem64_offset_base;
186 uint64_t pcie_a_mem64_offset_mask;
187 uint64_t pcie_a_iocon_offset_base;
188 uint64_t pcie_a_iocon_offset_mask;
189 uint64_t pcie_a_fsh;
190 uint64_t soc_esr;
191 uint64_t soc_log_enb;
192 uint64_t soc_intr_enb;
193 uint64_t soc_err_steering; /* mapped in JTAG space */
194 uint64_t soc_err_inject;
195 uint64_t soc_fatal_enb;
196 uint64_t soc_sii_err_syndrome;
197 uint64_t soc_ncu_err_syndrome;
198 uint64_t mondo_int_data0[NCU_TARGETS];
199 uint64_t mondo_int_data1[NCU_TARGETS];
200 uint64_t mondo_int_busy[NCU_TARGETS];
201} ncu_reg_t;
202
203
204/*
205 * PIU region map address
206 */
207#define PIU_MAX_REGION 4
208#define PIU_REGION_OFFSET_MASK MASK64(35,24)
209#define PIU_REGION_OFFSET_MASK_HI MASK64(39,36)
210
211typedef struct {
212 uint64_t base;
213 uint64_t mask;
214 uint64_t size;
215 int func;
216 bool_t enable;
217 uint8_t priority;
218 int align_size;
219 int reverse_endian;
220} map_info_t;
221
222typedef enum {
223 PIU_REGION_CFGIO = 0,
224 PIU_REGION_MEM32 = 1,
225 PIU_REGION_MEM64 = 2,
226 PIU_REGION_8MB = 3,
227 PIU_REGION_UNMAPPED
228} piu_region_t;
229
230
231/*
232 * NCU pseudo device
233 */
234typedef struct {
235 ncu_reg_t regs; /* NCU CSRs */
236 map_info_t map[PIU_MAX_REGION]; /* PIU region map info */
237 pthread_mutex_t ncu_lock; /* hold this lock for any ncu register access */
238 int node_id;
239} ncu_t;
240
241
242/*
243 * DMU 8MB configu region address map
244 */
245#define DMU_8MB_GAP_MASK MASK64(31,23)
246#define DMU_8MB_OFFSET_MASK MASK64(22,0)
247
248
249/*
250 * L2 Cache controller definition
251 */
252#define L2_BANKS 8
253
254/*
255 * L2 Cache Diagnostic Access section 28.17.1 N2 PRM, Rev. 1.2
256 */
257typedef struct L2C {
258 uint64_t * diag_datap;
259 uint64_t * diag_tagp;
260#define L2_TAG MASK64(39,18) /* table 28-46 */
261#define L2_TAG_ECC MASK64(5,0)
262 uint64_t * diag_vuadp;
263#define L2_ODDEVEN_SHIFT 22 /* table 28-43 */
264#define L2_WAY_MASK 0xf << 18
265#define L2_WAY MASK64(21,18) & L2_WAY_MASK
266#define L2_LINE MASK64(17,9) /* vs. MASK64(17,8) for N1 */
267#define L2_BANK MASK64(8,6) /* vs. MASK64(7,6) for N1 */
268#define L2_WORD MASK64(5,3)
269#define L2_VDSEL MASK64(22,22)
270#define L2_DM_MASK MASK64(21,6)
271 /*
272 * index into data with way/line/bank/word/oddeven bits
273 * access 64bits: 32bit data, 7bit ECC, plus rsvd bits, total of 8MB
274 */
275#define L2_DATA_SIZE ((L2_WAY|L2_LINE|L2_BANK|L2_WORD|(1<<L2_ODDEVEN_SHIFT))+8)
276 /*
277 * index into tags with way/line/bank bits
278 * access 64bits: 22bit tag, 6bit ECC plus rsvd bits (512K size)
279 */
280#define L2_TAG_SIZE (((L2_WAY|L2_LINE|L2_BANK)>>3)+8)
281 /*
282 * index into vuad with way/line/bank bits
283 * access 64bits: valid/dirty or alloc/used bits and associated parity (64K size)
284 */
285#define L2_VUAD_SIZE (((L2_LINE|L2_BANK|(L2_VDSEL>>4))>>3)+8)
286
287 uint32_t control[L2_BANKS]; /* table 28-34 */
288
289#ifdef VFALLS /* { */
290#define L2_NODEID MASK64(24,23)
291#define L2_NODEID_SHIFT 23
292#endif /* } */
293
294#define L2_DBGEN MASK64(21,21)
295#define L2_DBGEN_SHIFT 21
296#define L2_ERRORSTEER MASK64(20,15)
297#define L2_SCRUBINTERVAL MASK64(14,3)
298#define L2_SCRUBENABLE MASK64(2,2)
299#define L2_DMMODE MASK64(1,1)
300#define L2_DIS MASK64(0,0)
301
302 uint64_t error_enable[L2_BANKS]; /* table 12-20 */
303#define L2_DBG_TRIG_EN MASK64(2,2)
304#define L2_NCEEN MASK64(1,1)
305#define L2_CEEN MASK64(0,0)
306
307 uint64_t error_status[L2_BANKS]; /* table 12-21 */
308#ifdef VFALLS
309 uint64_t error_status_ii[L2_BANKS]; /* VF PRM table 12-2 */
310#endif
311 uint64_t error_address[L2_BANKS];
312 uint64_t error_notdata[L2_BANKS];
313 uint8_t error_inject[L2_BANKS];
314 uint16_t bist_ctl[L2_BANKS];
315} l2c_t;
316
317/*
318 * L2 Cache Error Registers, section 12.10.2 of N2 PRM, Rev. 1.0
319 */
320#define BIT(i) ((uint64_t)1<<i)
321
322#define L2_MEU_bit BIT(63)
323#define L2_MEC_bit BIT(62)
324#define L2_RW_bit BIT(61)
325#define L2_MODA_bit BIT(60)
326#define L2_LDAC_bit BIT(53)
327#define L2_LDAU_bit BIT(52)
328#define L2_LDWC_bit BIT(51)
329#define L2_LDWU_bit BIT(50)
330#define L2_LDRC_bit BIT(49)
331#define L2_LDRU_bit BIT(48)
332#define L2_LDSC_bit BIT(47)
333#define L2_LDSU_bit BIT(46)
334#define L2_LTC_bit BIT(45)
335#define L2_LRF_bit BIT(44)
336#define L2_LVF_bit BIT(43)
337#define L2_DAC_bit BIT(42)
338#define L2_DAU_bit BIT(41)
339#define L2_DRC_bit BIT(40)
340#define L2_DRU_bit BIT(39)
341#define L2_DSC_bit BIT(38)
342#define L2_DSU_bit BIT(37)
343#define L2_VEC_bit BIT(36)
344#define L2_VEU_bit BIT(35)
345#define L2_LVC_bit BIT(34)
346#define L2_SYND_MASK MASK64(27,0)
347
348#define L2_TID(val) (((uint64_t)val & 0x3f) << 54)
349#define L2_FAKE_SYND_SINGLE 0x43 /* single bit error on bit 0 */
350#define L2_FAKE_SYND_DOUBLE 0x33 /* uncorrectible double bit error */
351#define L2_FAKE_SYND_POISON 0x03 /* poisoned ecc */
352
353/*
354 * bits captured for some error type, table 12-26, section 12.10.3 of N2 PRM, Rev. 1.0
355 */
356#define L2_PA_LINE(val) (val & MASK64(39,6))
357#define L2_PA_QUAD(val) (val & MASK64(39,4))
358#define L2_INDEX(val) (val & MASK64(21,6))
359#define L2_DIR_IDX(val) (val & MASK64(15,6))
360
361/*
362 * SSI
363 */
364typedef struct SSI {
365 uint64_t timeout;
366 uint64_t log;
367 uint64_t magic_ssi;
368} ssi_t;
369
370/*
371 * HWDBG
372 */
373typedef struct HWDBG {
374 uint64_t debug_port_config;
375 uint64_t io_quiesce_control;
376} hwdbg_t;
377
378/*
379 * Reset Unit
380 */
381typedef struct RCU {
382 uint64_t reset_gen;
383 uint64_t reset_status;
384 uint64_t reset_source;
385#ifdef VFALLS /* { */
386 uint64_t comt_divs;
387 uint64_t comt_cfg;
388 uint64_t clk_steer;
389 uint64_t comt_lock_time;
390
391#endif /* } */
392} rcu_t;
393
394/*
395 * Clock Unit
396 */
397#define RC_DELAY_MASK 0xffff
398#define RC_DELAY_SHIFT 9
399#define RC_BYPASS_SHIFT 8
400#define RC_FREQ_SEL_MASK 0x3
401#define RC_FREQ_SEL_SHIFT 6
402#define RC_ANALOG_SEL_MASK 0x3
403#define RC_ANALOG_SEL_SHIFT 4
404#define RC_MODE_SHIFT 3
405#define RC_NOISE_CELL_SEL_MASK 0x7
406#define RC_NOISE_CELL_SEL_SHIFT 0
407#define RC_REG_MASK MASK64(24, 0)
408
409typedef struct {
410 uint64_t ctl;
411 uint8_t freqidx[3];
412 double phase[3];
413 double frequency[4][3];
414 double noise[4][3];
415} rand_state_t;
416
417typedef struct CCU {
418 uint64_t control;
419 rand_state_t rand_state;
420} ccu_t;
421
422/*
423 * Memory controller
424 */
425
426/*
427 * max number of AMBs per channel
428 * note that for 2 channel mode this may need to be
429 * 16 to support acces to FBD_CHNL_STATE reg
430 */
431
432#define MAX_AMBS 16
433/* active link trained state for fbd_chnl_state */
434#define L0_STATE 0x6
435
436typedef struct {
437 uint8_t val; /* value for reg */
438 uint8_t ambstate[MAX_AMBS]; /* state for each amb off */
439}fbstate_t;
440
441/* fbdimm regs */
442typedef enum {
443 FBD_VID_DID = 0x000,
444 FBDS = 0x140,
445 EMASK = 0x18c,
446 FERR = 0x190,
447 NERR = 0x194,
448 PSBYTE3_0 = 0x1b0,
449 PSBYTE7_4 = 0x1b4,
450 PSBYTE11_8 = 0x1b8,
451 PSBYTE13_12 = 0x1bc,
452 C2DINCRCUR_CMD2DATANXT = 0x1e8,
453 MBCSR = 0x340,
454 DAREFTC = 0x370,
455 MTR_DSREFTC = 0x374,
456 DRT = 0x378,
457 DRC = 0x37c,
458 DCALCSR = 0x440,
459 DCALADDR = 0x444,
460 DDR2ODTC = 0x4fc,
461 FBDIMM_ILLEGAL_REG = -1
462} fbdimm_ctl_regs_t;
463
464typedef struct AMB {
465 uint32_t vid_did;
466 uint32_t fbds;
467 uint32_t emask;
468 uint32_t ferr;
469 uint32_t nerr;
470 uint32_t psbyte3_0;
471 uint32_t psbyte7_4;
472 uint32_t psbyte11_8;
473 uint32_t psbyte13_12;
474 uint32_t c2dincrcur_cmd2datanxt;
475 uint32_t mbcsr;
476 uint32_t dareftc;
477 uint32_t mtr_dsreftc;
478 uint32_t drt;
479 uint32_t drc;
480 uint32_t dcalcsr;
481 uint32_t dcaladdr;
482 uint32_t ddr2odtc;
483} amb_ctl_t;
484
485/* extract ambaddr and ambid from Configuration Register Access Address Reg */
486#define AMBID(reg) ((reg & MASK64(14, 11)) >> 11)
487#define AMBADDR(reg) (reg & MASK64(10, 2))
488
489/* link regs */
490/*
491 * FBDS0: FBD Status 0
492Bit Attr Default Description
4937:5 RV 0h Reserved
4944 RO 0h SP: Parity: This bit contains an odd parity bit that
495 covers the S[3:0] field.
4963 RO 0h S3: Northbound Debug Event(1 = asserted, 0 = inactive):
497 This bit is used to communicate debug events to the
498 host.
4992:1 RO 0h S[2:1]: Thermal Trip: This field indicates various
500 thermal conditions of the AMB as follows:
501 00 Below TEMPLO
502 01 Above TEMPLO
503 10 Above TEMPMID and falling
504 11 Above TEMPMID and rising
505 The TEMPLO threshold is generally used to inform the
506 host to accelerate refresh events. The TEMPMID threshold
507 is generally used to inform the host that a thermal
508 limit has been exceeded and that thermal throttling is
509 needed. Refer to the RAS chapter for more details on
510 thermal management.
5110 RO 0h S0: ERROR Asserted: This bit indicates an error has been
512 detected by the AMB. Errors can be alert or other type.
513*/
514#define S0_ERROR (1ULL << 0)
515
516/* ddr regs */
517/*
518DRC: DRAM Controller Mode Register
519Bit Attr Default Description
52031:30 RV 00 Reserved
52129 RW 0 INITDONE: Initialization Complete. This scratch bit
522 communicates software state from the AMB to BIOS. BIOS
523 sets this bit to 1 after initialization of the DRAM
524 memory array is complete. This bit has no effect on AMB
525 operation.
52628 RV 0 Reserved
52727:24 RWST 0 CLKDIS: clock[3:0] output disable
52823 RWST 0 SEQADDR: When set to 1 turns off address balancing to
529 support DRAMs programmed for Sequential Burst Type
53019:22 RV 00 Reserved
53118 RWST 1 ODTZ: On-Die Termination Strength. 0 Disabled 1
532 Enabled
53317 RWST 0 HLDDIS: command/address hold disable
53416 RWST 0 BALDIS: command/address balancing disable
53515 RW 0 CADIS: command/address output disable
53614 RW 0 CSDIS: chip select output disable
53713 RW 0 ODTDIS: ODT output disable
53812 RWST 1 CKEFRCLOW: CKE Force Low Forces CKE low. Must be cleared
539 to enable normal DDR functionality. This bit overrides
540 the CKE1 and CKE0 fields described below, and also
541 overrides all channel commands and other hardware
542 fuctions that would otherwise affect the state of the
543 CKE outputs.
54411 RW 0 CKEDIS: CKE output disable
54510 RWST 0 CKE1: CKE output 1 control and status. Software can
546 write to this bit to change the state of the CKE 1
547 output. Hardware will update this bit with the current
548 status of the CKE1 output two core cycles after a
549 channel command or other hardware function changes the
550 state of the CKE1 output. 1 = CKE1 pads asserted. 0
551 = CKE1 pads de-asserted.
5529 RWST 0 CKE0: CKE output 0 control and status. Software can
553 write to this bit to change the state of the CKE 0
554 output. Hardware will update this bit with the current
555 status of the CKE 0 output two core cycles after a
556 channel command or other hardware function changes the
557 state of the CKE 0 output. 1 = CKE0 pads asserted. 0
558 = CKE0 pads de-asserted.
5598 RWST 0 BL: DRAM burst length. 1 = bl8 0 = bl4
5607:4 RWST 2h AL: DRAM Additive Latency [3:0]
5613:0 RWST 3h CL: DRAM CAS Latency [3:0]
562*/
563#define CKEFRCLOW (1ULL << 12)
564#define CKE1 (1ULL << 10)
565#define CKE0 (1ULL << 9)
566
567typedef struct MCU_BANK {
568 uint8_t cas_addr_width;
569 uint8_t ras_addr_width;
570 uint8_t cas_lat;
571 uint16_t scrub_freq;
572 uint16_t refresh_freq;
573 uint16_t refresh_counter;
574 uint8_t scrub_enable;
575 uint8_t trrd;
576 uint8_t trc;
577 uint8_t trcd;
578 uint8_t twtr;
579 uint8_t trtw;
580 uint8_t trtp;
581 uint8_t tras;
582 uint8_t trp;
583 uint8_t twr;
584 uint8_t trfc;
585 uint8_t tmrd;
586 uint8_t fawin;
587 uint8_t tiwtr;
588 uint8_t dimm_stack;
589 uint16_t ext_wr_mode2;
590 uint16_t ext_wr_mode1;
591 uint16_t ext_wr_mode3;
592 uint8_t eight_bank_mode;
593 uint8_t branch_disabled;
594 uint8_t sel_lo_addr_bits;
595 uint8_t single_chnl_mode;
596#ifdef VFALLS
597 uint8_t mirror_mode;
598#endif VFALLS
599 uint8_t dimm_init;
600 uint8_t init_status;
601 uint8_t dimm_present;
602 uint8_t failover_status;
603 uint64_t failover_mask;
604 uint8_t power_down_mode;
605 fbstate_t fbd_chnl_state;
606 amb_ctl_t amb[MAX_AMBS];
607 uint8_t fbd_fast_reset_flag;
608 uint8_t fbd_chnl_reset;
609 uint8_t ts1_sb_nb_mapping;
610 uint32_t ts1_test_parameter;
611 uint16_t ts3_failover_config;
612 uint32_t electrical_idle_detected;
613 uint8_t disable_state_period;
614 uint8_t disable_state_period_done;
615 uint32_t calibrate_state_period;
616 uint8_t calibrate_state_period_done;
617 uint16_t training_state_min_time;
618 uint8_t training_state_done;
619 uint8_t training_state_timeout;
620 uint8_t testing_state_done;
621 uint8_t testing_state_timeout;
622 uint8_t polling_state_done;
623 uint8_t polling_state_timeout;
624 uint8_t config_state_done;
625 uint8_t config_state_timeout;
626 uint16_t dram_per_rank_cke;
627 uint8_t l0s_duration;
628 uint8_t chnl_sync_frame_freq;
629 uint16_t chnl_read_lat;
630 uint16_t chnl_capability;
631 uint8_t loopback_mode_cntl;
632 uint32_t serdes_config_bus;
633 uint64_t serdes_invpair;
634 uint64_t serdes_test_config_bus;
635 uint16_t config_reg_access_addr;
636 uint32_t config_reg_access_data;
637 uint64_t error_status;
638 uint64_t error_address;
639 uint64_t error_inject;
640 uint16_t error_counter;
641 uint64_t error_location;
642 uint64_t error_retry;
643 uint64_t fbd_error_synd;
644 uint64_t fbd_inj_error_src;
645 uint64_t fbr_count;
646 uint8_t perf_ctl;
647 uint64_t perf_count;
648 uint32_t open_bank_max;
649 uint16_t prog_time_cntr;
650 uint8_t dbg_trg_en;
651 uint64_t ibist_nbfib_ctl;
652 uint64_t ibist_sbfib_ctl;
653} mcu_bank_t;
654
655/*
656 * DRAM Error Registers, section 12.12.1 of N2 PRM, Rev. 1.0
657 */
658#define DRAM_MEU_bit BIT(63)
659#define DRAM_MEC_bit BIT(62)
660#define DRAM_DAC_bit BIT(61)
661#define DRAM_DAU_bit BIT(60)
662#define DRAM_DSC_bit BIT(59)
663#define DRAM_DSU_bit BIT(58)
664#define DRAM_DBU_bit BIT(57)
665#define DRAM_MEB_bit BIT(56)
666#define DRAM_FBU_bit BIT(55)
667#define DRAM_FBR_bit BIT(54)
668#define DRAM_SYND_MASK MASK64(15,0)
669
670#define DRAM_FAKE_SYND_SINGLE 0x00010101 /* nibble 31, bit 1 in error */
671#define DRAM_FAKE_SYND_DOUBLE 0x00000101 /* uncorrectible multi-nibble error */
672#define DRAM_FAKE_SYND_POISON 0x00008221 /* poisoned ecc */
673
674
675/*
676 * SSI
677 */
678typedef enum {
679 SSI_TIMEOUT = 0x10088,
680 SSI_LOG = 0x00018
681} ssi_reg_t;
682
683/*
684 * HW Debug Unit
685 */
686typedef enum {
687 DEBUG_PORT_CONFIG = 0x0,
688 IO_QUIESCE_CONTROL = 0x8
689} hwdbg_reg_t;
690
691/*
692 * Reset Unit
693 */
694typedef enum {
695#ifdef VFALLS /* { */
696 COMT_DIVS = 0x920,
697 COMT_CFG = 0x940,
698 CLK_STEER = 0x960,
699 COMT_LOCK_TIME = 0x970,
700#endif /* } */
701 RESET_GEN = 0x808,
702 RESET_STATUS = 0x810,
703 RESET_SOURCE = 0x818
704
705} rcu_reg_t;
706
707/*
708 * JTAG
709 */
710typedef enum {
711 INT_VECTOR_DISPATCH = 0x1cc0000,
712 ASI_CORE_AVAILABLE = 0x1040000,
713 ASI_CORE_ENABLE_STATUS = 0x1040010,
714 ASI_CORE_ENABLE = 0x1040020,
715 ASI_CORE_RUNNING_RW = 0x1040050,
716 ASI_CORE_RUNNING_STATUS = 0x1040058,
717 ASI_CORE_RUNNING_W1S = 0x1040060,
718 ASI_CORE_RUNNING_W1C = 0x1040068,
719 SOC_ERROR_STEERING = 0x1041000
720} jtag_reg_t;
721
722#ifdef VFALLS /* { */
723/*
724 * NCX
725 */
726typedef enum {
727 CF_SYS_MODE_REG = 0x8,
728 CF_SLOW_PULSE_WAIT = 0x18,
729 NCX_TIC_EN_SLOW = 0x20,
730 NCX_TWR = 0x1000,
731 NCX_TPESR = 0x1008,
732 NCX_TPELSE = 0x1010,
733 NCX_TPEAR = 0x1018
734} ncx_reg_t;
735
736#define SM_E2WAY_SEL_SHIFT 9
737#define SM_E3WAY_SEL_SHIFT 8
738#define SM_E4WAY_SEL_SHIFT 7
739#define SM_EXTERN_HUB_SEL_SHIFT 6
740#define SM_NODE_SEL_MASK 0x3
741#define SM_NODE_SEL_SHIFT 4
742#define SM_PLANE_EN_SEL_MASK 0xf
743#define SM_PLANE_EN_SEL_SHIFT 0
744#define SM_REG_MASK MASK64(9, 0)
745
746#define SM_EWAY_BITS(_sys_mode) (((_sys_mode) >> SM_E4WAY_SEL_SHIFT) & \
747 7)
748#define SM_2_NODE(_sys_mode) (((_sys_mode) >> SM_NODE_SEL_SHIFT) & \
749 SM_NODE_SEL_MASK)
750
751typedef struct NCX {
752 uint64_t sys_mode;
753 uint64_t tick_en_slow;
754 uint64_t slow_pulse_wait;
755 uint64_t twr;
756 uint64_t tpesr;
757 uint64_t tpelse;
758 uint64_t tpear;
759} ncx_t;
760
761/*
762 * COU
763 */
764#define COU_LINK_MAX 4ULL
765#define COU_LINK_SHIFT 12
766#define COU_LINK_MASK ((COU_LINK_MAX-1) << COU_LINK_SHIFT)
767
768typedef enum {
769 COU_ERR_ENABLE_REG = 0x00,
770 COU_ESR = 0x10,
771 COU_EAR = 0x18
772} cou_reg_t;
773
774typedef struct COU {
775 uint64_t cou_err_enable[COU_LINK_MAX];
776 uint64_t cou_esr[COU_LINK_MAX];
777 uint64_t cou_ear[COU_LINK_MAX];
778} cou_t;
779
780/*
781 * LFU
782 */
783typedef enum {
784 CL_INIT_STATE = 0x0,
785 CL_CFG_REG = 0x8,
786 CL_SERDES_CFG = 0x58,
787 CL_SER_INVPAIR = 0x60,
788 CL_TEST_CFG = 0x68,
789 CL_ERROR_STAT = 0x80
790} lfu_reg_t;
791
792#define LFU_MAX_LINKS 0x4
793#define LFU_LINK_MASK 0x3000
794#define LFU_LINK_L0 0x5
795#define LFU_LINK_MASTER_EN 0x3
796#define LFU_LINK_SLAVE_EN 0x1
797
798typedef struct LFU {
799 uint64_t cl_init_state[LFU_MAX_LINKS];
800 uint64_t cl_cfg_reg[LFU_MAX_LINKS];
801 uint64_t cl_serdes_cfg[LFU_MAX_LINKS];
802 uint64_t cl_ser_invpair[LFU_MAX_LINKS];
803 uint64_t cl_test_cfg[LFU_MAX_LINKS];
804 uint64_t cl_error_stat[LFU_MAX_LINKS];
805} lfu_t;
806
807#endif /* } VFALLS */
808
809/*
810 * Clock unit
811 */
812typedef enum {
813 CLOCK_CONTROL = 0x00,
814 RAND_CTL = 0x20,
815 RAND_GEN = 0x30
816} ccu_reg_t;
817
818/*
819 * L2 Cache Registers, section 28.17 of N2 PRM, Rev. 1.0
820 */
821typedef enum {
822 L2_DIAG_DATA = 0x0, /* Table 28-44 */
823 L2_DIAG_TAG = 0x4, /* Table 28-46 */
824 L2_DIAG_VUAD = 0x6, /* Table 28-50 */
825 L2_TAG_BIST = 0x8, /* Table 28-51 */
826 L2_CONTROL = 0x9, /* Table 28-34 */
827 L2_ERROR_ENABLE = 0xa, /* Table 12-20 */
828 L2_ERROR_STATUS = 0xb, /* Table 12-21 */
829#ifdef VFALLS
830 L2_ERROR_STATUS_II = 0xf, /* VF PRM, Table 12-2 */
831#endif
832 L2_ERROR_ADDRESS = 0xc, /* Table 12-25 */
833 L2_ERROR_INJECT = 0xd, /* Table 12-29 */
834 L2_ERROR_NOTDATA = 0xe /* Table 12-27 */
835} l2c_reg_t;
836
837/*
838 * DRAM controller section 25.10 of N2 RPM, Rev. 1.0
839 */
840typedef enum {
841 DRAM_CAS_ADDR_WIDTH = 0x000,
842 DRAM_RAS_ADDR_WIDTH = 0x008,
843 DRAM_CAS_LAT = 0x010,
844 DRAM_SCRUB_FREQ = 0x018,
845 DRAM_REFRESH_FREQ = 0x020,
846 DRAM_OPEN_BANK_MAX = 0x028,
847 DRAM_REFRESH_COUNTER = 0x038,
848 DRAM_SCRUB_ENABLE = 0x040,
849 DRAM_PROG_TIME_CNTR = 0x048,
850 DRAM_TRRD = 0x080,
851 DRAM_TRC = 0x088,
852 DRAM_TRCD = 0x090,
853 DRAM_TWTR = 0x098,
854 DRAM_TRTW = 0x0a0,
855 DRAM_TRTP = 0x0a8,
856 DRAM_TRAS = 0x0b0,
857 DRAM_TRP = 0x0b8,
858 DRAM_TWR = 0x0c0,
859 DRAM_TRFC = 0x0c8,
860 DRAM_TMRD = 0x0d0,
861 DRAM_FAWIN = 0x0d8,
862 DRAM_TIWTR = 0x0e0,
863 DRAM_DIMM_STACK = 0x108,
864 DRAM_EXT_WR_MODE2 = 0x110,
865 DRAM_EXT_WR_MODE1 = 0x118,
866 DRAM_EXT_WR_MODE3 = 0x120,
867 DRAM_8_BANK_MODE = 0x128,
868 DRAM_BRANCH_DISABLED = 0x138,
869 DRAM_SEL_LO_ADDR_BITS = 0x140,
870 DRAM_SINGLE_CHNL_MODE = 0x148, /* Table 25-30, possible PRM doc error */
871#ifdef VFALLS
872 DRAM_MIRROR_MODE = 0x150,
873#endif
874 DRAM_DIMM_INIT = 0x1a0,
875 DRAM_INIT_STATUS = 0x210,
876 DRAM_DIMM_PRESENT = 0x218,
877 DRAM_FAILOVER_STATUS = 0x220,
878 DRAM_FAILOVER_MASK = 0x228,
879 DRAM_DBG_TRG_EN = 0x230,
880 DRAM_POWER_DOWN_MODE = 0x238,
881 DRAM_ERROR_STATUS = 0x280,
882 DRAM_ERROR_ADDRESS = 0x288,
883 DRAM_ERROR_INJECT = 0x290,
884 DRAM_ERROR_COUNTER = 0x298,
885 DRAM_ERROR_LOCATION = 0x2a0,
886 DRAM_ERROR_RETRY = 0x2a8,
887 DRAM_PERF_CTL = 0x400,
888 DRAM_PERF_COUNT = 0x408,
889 FBD_CHNL_STATE = 0x800,
890 FBD_FAST_RESET_FLAG = 0x808,
891 FBD_CHNL_RESET = 0x810,
892 TS1_SB_NB_MAPPING = 0x818,
893 TS1_TEST_PARAMETER = 0x820,
894 TS3_FAILOVER_CONFIG = 0x828,
895 ELECTRICAL_IDLE_DETECTED = 0x830,
896 DISABLE_STATE_PERIOD = 0x838,
897 DISABLE_STATE_PERIOD_DONE = 0x840,
898 CALIBRATE_STATE_PERIOD = 0x848,
899 CALIBRATE_STATE_PERIOD_DONE = 0x850,
900 TRAINING_STATE_MIN_TIME = 0x858,
901 TRAINING_STATE_DONE = 0x860,
902 TRAINING_STATE_TIMEOUT = 0x868,
903 TESTING_STATE_DONE = 0x870,
904 TESTING_STATE_TIMEOUT = 0x878,
905 POLLING_STATE_DONE = 0x880,
906 POLLING_STATE_TIMEOUT = 0x888,
907 CONFIG_STATE_DONE = 0x890,
908 CONFIG_STATE_TIMEOUT = 0x898,
909 DRAM_PER_RANK_CKE = 0x8a0,
910 L0S_DURATION = 0x8a8,
911 CHNL_SYNC_FRAME_FREQ = 0x8b0,
912 CHNL_READ_LAT = 0x8b8,
913 CHNL_CAPABILITY = 0x8c0,
914 LOOPBACK_MODE_CNTL = 0x8c8,
915 SERDES_CONFIG_BUS = 0x8d0,
916 SERDES_INVPAIR = 0x8d8,
917 SERDES_TEST_CONFIG_BUS = 0x8e0,
918 CONFIG_REG_ACCESS_ADDR = 0x900,
919 CONFIG_REG_ACCESS_DATA = 0x908,
920 DRAM_FBD_ERROR_SYND = 0xc00,
921 DRAM_FBD_INJ_ERROR_SRC = 0xc08,
922 DRAM_FBR_COUNT = 0xc10,
923 IBIST_SBFIB_CTL = 0xe80,
924 IBIST_NBFIB_CTL = 0xec0,
925 DRAM_ILLEGAL_REG = -1
926} ss_memory_ctl_reg_t;
927
928/*
929 * prototypes
930 */
931void niagara2_pcie_mapping(simcpu_t *sp, ncu_t *ncup, piu_region_t region);
932
933
934#ifdef __cplusplus
935}
936#endif
937
938#endif /* _NIAGARA2_DEVICE_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.