projects / OpenSPARC-T2-SAM / blame
| Commit | Line | Data |
|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: niagara2_error.h | |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 7 | * | |
| 8 | * The above named program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public | |
| 10 | * License version 2 as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * The above named program is distributed in the hope that it will be | |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public | |
| 18 | * License along with this work; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 20 | * | |
| 21 | * ========== Copyright Header End ============================================ | |
| 22 | */ | |
| 23 | /* | |
| 24 | * Copyright 2005 Sun Microsystems, Inc. All rights reserved. | |
| 25 | * Use is subject to license terms. | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef _NIAGARA2_ERROR_H | |
| 29 | #define _NIAGARA2_ERROR_H | |
| 30 | ||
| 31 | #pragma ident "@(#)niagara2_error.h 1.2 06/08/28 SMI" | |
| 32 | ||
| 33 | #ifdef __cplusplus | |
| 34 | extern "C" { | |
| 35 | #endif | |
| 36 | ||
| 37 | #if ERROR_INJECTION | |
| 38 | /* | |
| 39 | * Niagara 2 Error Types. At the present, it only defines the errors detected by the core. | |
| 40 | */ | |
| 41 | enum ERROR_TYPE { | |
| 42 | NONE = 0xffff, | |
| 43 | /* | |
| 44 | * errors handled by SS_trap_instruction_access_MMU_error (table 12-7, PRM v1.0) | |
| 45 | */ | |
| 46 | ITTM = 0x01, | |
| 47 | ITTP = 0x02, | |
| 48 | ITDP = 0x03, | |
| 49 | ITMU = 0x04, | |
| 50 | ITL2U = 0x05, | |
| 51 | ITL2ND = 0x06, | |
| 52 | ICL2U = 0x07, | |
| 53 | ICL2ND = 0x08, | |
| 54 | /* | |
| 55 | * errors handled by SS_trap_internal_processor_error (table 12-8, PRM v1.0) | |
| 56 | */ | |
| 57 | IRFU = 0x09, | |
| 58 | IRFC = 0x0a, | |
| 59 | FRFU = 0x0b, | |
| 60 | FRFC = 0x0c, | |
| 61 | SBDLC = 0x0d, | |
| 62 | SBDLU = 0x0e, | |
| 63 | MRAU = 0x0f, | |
| 64 | TSAC = 0x10, | |
| 65 | TSAU = 0x11, | |
| 66 | SCAC = 0x12, | |
| 67 | SCAU = 0x13, | |
| 68 | TCCP = 0x14, | |
| 69 | TCCU = 0x15, | |
| 70 | /* | |
| 71 | * errors handled by SS_trap_data_access_MMU_error (table 12-8, PRM v1.0) | |
| 72 | */ | |
| 73 | DTTM = 0x16, | |
| 74 | DTTP = 0x17, | |
| 75 | DTDP = 0x18, | |
| 76 | DTMU = 0x19, | |
| 77 | DTL2U = 0x1a, | |
| 78 | DTL2ND = 0x1b, | |
| 79 | /* | |
| 80 | * errors handled by SS_trap_data_access_error (table 12-8, PRM v1.0) | |
| 81 | */ | |
| 82 | DCL2U = 0x1c, | |
| 83 | DCL2ND = 0x1d, | |
| 84 | SOCU = 0x1e, | |
| 85 | /* | |
| 86 | * errors handled by SS_trap_hw_corrected_error (table 12-13, PRM v1.0) | |
| 87 | */ | |
| 88 | ICVP = 0x1f, | |
| 89 | ICTP = 0x20, | |
| 90 | ICTM = 0x21, | |
| 91 | ICDP = 0x22, | |
| 92 | DCVP = 0x23, | |
| 93 | DCTP = 0x24, | |
| 94 | DCTM = 0x25, | |
| 95 | DCDP = 0x26, | |
| 96 | L2C = 0x27, | |
| 97 | SBDPC = 0x28, | |
| 98 | SOCC = 0x29, | |
| 99 | /* | |
| 100 | * errors handled by SS_trap_sw_recoverable_error (table 12-13, PRM v1.0) | |
| 101 | */ | |
| 102 | SBDPU = 0x2a, | |
| 103 | TCCD = 0x2b, | |
| 104 | TCUD = 0x2c, | |
| 105 | MAMU = 0x2d, | |
| 106 | MAL2C = 0x2e, | |
| 107 | MAL2U = 0x2f, | |
| 108 | MAL2ND = 0x30, | |
| 109 | CWQL2C = 0x31, | |
| 110 | CWQL2U = 0x32, | |
| 111 | CWQL2ND = 0x33, | |
| 112 | L2C1 = 0x34, /* FIXME: L2C defined twice, rename it to L2C1 for now */ | |
| 113 | L2U = 0x35, | |
| 114 | L2ND = 0x36, | |
| 115 | ITL2C = 0x37, | |
| 116 | ICL2C = 0x38, | |
| 117 | DTL2C = 0x39, | |
| 118 | DCL2C = 0x3a, | |
| 119 | SOCU1 = 0x3b /* FIXME: SOCU defined twice, rename it to SOCU1 for now */ | |
| 120 | }; | |
| 121 | ||
| 122 | #define ERROR_MAXNUM 0x40 /* maximum number of errors handled currently */ | |
| 123 | ||
| 124 | typedef struct SS_ERROR_DESC { | |
| 125 | error_type_t error_type; | |
| 126 | char *error_name; | |
| 127 | ss_trap_type_t trap_type; | |
| 128 | char *trap_name; | |
| 129 | int trap_priority; | |
| 130 | int error_code; | |
| 131 | char *enable_name; | |
| 132 | uint64_t enable_bit; | |
| 133 | } ss_error_desc_t; | |
| 134 | ||
| 135 | ss_error_desc_t ss_error_list[ERROR_MAXNUM]; | |
| 136 | ||
| 137 | /* | |
| 138 | * L2 error enable register, table 12-20, N2 PRM, Rev. 1.0 | |
| 139 | */ | |
| 140 | #define NA_NCEEN MASK64(1,1) | |
| 141 | #define NA_CEEN MASK64(0,0) | |
| 142 | ||
| 143 | ||
| 144 | /* | |
| 145 | * Niagara2 error injection routine prototypes | |
| 146 | */ | |
| 147 | void niagara2_init_error_list(); | |
| 148 | bool_t itlb_hit_error_match(simcpu_t *sp, tlb_entry_t *tep); | |
| 149 | bool_t dtlb_hit_error_match(simcpu_t *sp, int op, tlb_entry_t *tep, tpaddr_t va); | |
| 150 | bool_t l2dram_access_error_match(simcpu_t *sp, int op, tpaddr_t pa); | |
| 151 | bool_t tlb_data_access_error_match(simcpu_t *sp, ss_mmu_t *mmup, uint64_t idx); | |
| 152 | bool_t tlb_tag_access_error_match(simcpu_t *sp, ss_mmu_t *mmup, uint64_t idx); | |
| 153 | void xicache_error_match(simcpu_t *sp, tpaddr_t pa); | |
| 154 | ||
| 155 | #endif /* ERROR_INJECTION */ | |
| 156 | ||
| 157 | #ifdef __cplusplus | |
| 158 | } | |
| 159 | #endif | |
| 160 | ||
| 161 | #endif /* _NIAGARA2_ERROR_H */ |