Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / obp / obp / arch / sun4v / hslave.fth

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\ Hypervisor Software File: hslave.fth
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\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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\ ========== Copyright Header End ============================================
id: @(#)hslave.fth 1.3 07/05/04
purpose:
copyright: Copyright 2007 Sun Microsystems, Inc.  All Rights Reserved
copyright: Use is subject to license terms.

headerless

label start-slave-cpus
   \ Turn OFF everything except for PRIV bit in %pstate

   %g0  h# f			wrpil
   %g0  4			wrpstate
   %i0		      %g1	move
   %i1		      %g2	move
   %g0  0			wrtba
   \ XXX %g0  0		%r22	wrasr	\ Clear SoftInt Reg.
   %g0  7			wrcleanwin
   %g0  0			wrotherwin
   %g0  0			wrwstate
   %g0  0			wrcanrestore
   %g0  6			wrcansave
   %g0  0			wrcwp
   %g1			%i0	move
   %g2			%i1	move
   %g0  0			wrtl	\ TL = 0
   %g0  0                       wrgl

   %g0  h# 16		%o5	add
   %g0  0 always		htrapif
   %g0  h# 20			wrasi
   %o1  %g0 h# 08  %asi		stxa	\ MID in scratchpad1

   %i1			%o1	move	\ Size of Memory
   setup-i/d-tlbs		call
   %i0			%o0	move	\ Base of Memory

   \ ick ick
   \ need a PA, so we reverse engineer one
   \ this needs to move to 'reset'..
   mmu-info >mmu-miss-pa rombase + 4meg 1- land %o0 set \ relative to start
   %i0  %o0 memory-asi	%o0	ldxa	\ PA
   %o1				get-mid
   %o1  /mmu-miss-area log2 %o1	sllx
   %o0  %o1		%o0	add
   %g0  h# 30		%o1	add
   %o0  %g0  %o1 h# 20		stxa	\ Scratch6, MISS AREA PA
   mmu-miss-area-func#	%o5	set
   %g0 fast-trap# always	htrapif	\ set it

   \ Set the base register
   ROMbase              base    set

   \ Set %tba register
   base			%g0	wrtba

   %g0 1                %o0  add	\ MMU On
   %g0 mmu-on-off-func# %o5  add
   here origin - 	%g4  set
   base  %g4		%g4  add
   %g4 h# 18            %o1  add	\ Return PC
   %g0 fast-trap#    always  htrapif
   nop

   \ Set up register
   prom-main-task	up	set

   release-slaves? origin- scr set
   scr  base		scr	add
   scr  %g0		sc2	ld
   begin
      sc2  %g0	%g0	subcc
   0<> until
      scr  %g0	sc2	ld

   scr			rdpstate
   scr  h# 16	scr	or
   scr  0			wrpstate

   \ can clear post-run magic in %i5
   %g0		%i5	move

   \ Enter the initial idle loop
   slave-init		always brif
   nop
end-code

1 4 h# 10 0 hypercall: hyper-startcpu
: idle-slaves ( -- )
   0 tba@ >physical drop		( 0 tba )
   start-slave-cpus origin- over +	( 0 tba pc )
   max-#cpus 0  do			( 0 tba pc )
      mid@ i <>  if			( 0 tba pc )
	 \ Start CPU only if there is a node for it in MD
	 i mid-ok? if			( 0 tba pc )
            0 i >cpu-struct >cpu-status ! ( 0 tba pc )
            3dup i hyper-startcpu	( 0 tba pc status )
	    0= if			( 0 tba pc )
	       \ Give a second for the CPU to park in slave loop
	       get-msecs d# 1000 + begin ( 0 tba pc msecs )
	          get-msecs over <	( 0 tba pc msecs timeout? )
	          i >cpu-struct >cpu-status @ 0= and ( 0 tba pc msecs ok? )
	          while 10 ms 		( 0 tba pc msecs )
	       repeat drop		( 0 tba pc )
	    then			( 0 tba pc )
	 then				( 0 tba pc )
      then				( 0 tba pc )
   loop	 3drop				(  )
;

stand-init: Kicking slave CPU(s) into idle loop
   init-per-cpu-data
   ['] init-per-cpu-data is slave-idle-loop-hook
   idle-slaves
;

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