[OpenSPARC-T2-SAM] / obp / obp / arch / sun4v / mmumiss.fth

\ ========== Copyright Header Begin ==========================================
\ 
\ Hypervisor Software File: mmumiss.fth
\ 
\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
\ 
\  - Do no alter or remove copyright notices
\ 
\  - Redistribution and use of this software in source and binary forms, with 
\    or without modification, are permitted provided that the following 
\    conditions are met: 
\ 
\  - Redistribution of source code must retain the above copyright notice, 
\    this list of conditions and the following disclaimer.
\ 
\  - Redistribution in binary form must reproduce the above copyright notice,
\    this list of conditions and the following disclaimer in the
\    documentation and/or other materials provided with the distribution. 
\ 
\    Neither the name of Sun Microsystems, Inc. or the names of contributors 
\ may be used to endorse or promote products derived from this software 
\ without specific prior written permission. 
\ 
\     This software is provided "AS IS," without a warranty of any kind. 
\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
\ 
\ You acknowledge that this software is not designed, licensed or
\ intended for use in the design, construction, operation or maintenance of
\ any nuclear facility. 
\ 
\ ========== Copyright Header End ============================================
id: @(#)mmumiss.fth 1.1 06/02/16
purpose: 
copyright: Copyright 2006 Sun Microsystems, Inc.  All Rights Reserved
copyright: Use is subject to license terms.

headers

0 >mmu-defer per-cpu-defer: va>tte-data

headerless

: null-va>tte-data ( vadr ctx -- false )  2drop false  ;

stand-init: Initialising the per CPU miss handler
   ['] null-va>tte-data  ['] va>tte-data 3 perform-action
;

: va>tte-installed?  ( -- flag )
   addr va>tte-data
   dup x@ 0<> swap
   token@ ['] null-va>tte-data  <> and
;

: prom-virt? ( vadr -- flag )
   dup monvirtbase RAMtop between  ( vadr flag )
   swap vpt-base u>= or        ( flag )
;
: (set-tte-soft ( tte virt -- tte' )
   prom-virt?  if  >tte-soft  then
;
' (set-tte-soft is set-tte-soft

: find-prom-tte ( virtual -- phys-lo phys-hi )
   dup pgmap@  dup valid-tte?  if  ( va tte )
      tuck tte>size 1- and     ( tte offset )
      s>d rot tte> d+          ( phys-lo phys-hi )
   else                        ( tte )
      drop -1 -1               ( -1 -1 )
   then                        ( phys-lo phys-hi )
;

headers
: find-client-tte ( vadr context# -- tte vadr' true -or- false )
   dup 0=  if			   ( vaddr context# )
      over  vpt-base u>=  if  2drop false  exit  then
   then				   ( vaddr context# )

   va>tte-installed?  if           ( vadr context# )
      2dup  va>tte-data  if        ( vadr context# tte )
	 rot swap dup tte>size     ( context# vadr tte size )
	 rot swap round-down       ( context# tte vadr )
	 \ Merge VA and CTX#
	 rot or                    ( tte vadr" )
      else                         ( vadr context# )
	 2drop  false  exit
      then                         ( tte vadr )
   else                            ( vadr context# )
      \ We can't handle contexts other than 0
      if  drop false  exit  then   ( vadr )
      dup pgmap@ tuck valid-tte?  0=  if      ( tte vadr )
	 2drop false  exit
      then                         ( tte vadr )
   then  true                      ( tte vadr true )
;

headerless
: (>physical) ( virt -- phys-lo phys-hi )
   dup prom-virt?  if  find-prom-tte exit  then
   dup 0  find-client-tte  if ( virt tte virt'  )
      drop tuck  tte>size     ( tte virt size )
      1-  and                 ( tte offset )
      s>d  rot  tte> d+       ( phys-lo phys-hi )
   else                       ( virt )
      drop -1 -1              ( -1 -1 )
   then                       ( phys-lo phys-hi )
;
' (>physical) is >physical

headers
: map? ( vadr -- )
   dup prom-virt?  if             ( vadr )
      dup pgmap@                  ( vadr tte )
   else                           ( vadr )
      dup 0  find-client-tte  if  ( vadr tte vadr' )
	 drop                     ( vadr tte )
      else                        ( vadr )
	 false                    ( vadr inv-tte )
      then                        ( vadr tte )
   then  (.map)                   (  )
;

headerless
: resolve-immu-miss ( vadr -- ok? )
   va>va,ctx  find-client-tte  if  ( tte vadr )
      itlb-tar-dir!  true          ( ok )
   else                            (  )
      false                        ( flag )
   then                            ( ok? )
;

: resolve-dmmu-miss ( vadr -- ok? )
   va>va,ctx  find-client-tte  if  ( tte vadr )
      dtlb-tar-dir!  true          ( flag )
   else                            (  )
      false                        ( flag )
   then                            ( ok? )
;

code dmmu-miss-return  ( ok? -- )
   tos				%l1	move
   %g0  h# 38			%l5	add
   %l5  %g0  h# 20		%l5	ldxa	\ CPU struct PA
   0 >dmmu-miss-state		%l0	set
   %l0  %l5			%g5	add	\ CPU save area
   %l1				%g0	cmp
   restore-cpu-state		0<>	brif
   %g0				%g4	move
   %g0  2			%g4	add	\ restore and come here
   restore-cpu-state		always	brif
   %g7					rdpc
   %g0  2				wrgl
   0 >dmmu-miss-state		%g1	set
   small-forth-save-state	always	brif
					nop
c;

code immu-miss-return  ( ok? -- )
   tos				%l1	move
   %g0  h# 38			%l5	add
   %l5  %g0  h# 20		%l5	ldxa	\ CPU struct PA
   0 >immu-miss-state		%l0	set
   %l0  %l5			%g5	add	\ CPU save area
   %l1				%g0	cmp
   restore-cpu-state		0<>	brif
   %g0				%g4	move
   %g0  2			%g4	add	\ restore and come here
   restore-cpu-state		always	brif
   %g7					rdpc
   %g0  2				wrgl
   0 >immu-miss-state		%g1	set
   small-forth-save-state	always	brif
					nop
c;

headers
defer dmmu-miss-enter-hook ( adr -- adr )
defer dmmu-miss-exit-hook  ( ok? -- ok? )
defer immu-miss-enter-hook ( adr -- adr )
defer immu-miss-exit-hook  ( ok? -- ok? )
headerless

' noop to dmmu-miss-enter-hook
' noop to dmmu-miss-exit-hook
' noop to immu-miss-enter-hook
' noop to immu-miss-exit-hook

: immu-miss-handler  ( vadr -- )
   immu-miss-enter-hook  ( vadr )
   resolve-immu-miss     ( ok? )
   immu-miss-exit-hook   ( ok? )
   immu-miss-return      (  )
;

: dmmu-miss-handler  ( vadr -- )
   dmmu-miss-enter-hook  ( vadr )
   resolve-dmmu-miss     ( ok? )
   dmmu-miss-exit-hook   ( ok? )
   dmmu-miss-return      (  )
;

label dmmu-miss-start ( -- vadr )
   %g0  h# 38			%g1	add
   %g1  %g0  h# 20		%g1	ldxa		\ CPU struct PA
   0 >dmmu-miss-state		%g5	set
   %g5  %g1			%g5	add		\ DMMU stacks
   %g0				%g6	move		\ Small Save
   save-cpu-state		always	brif
   %g7					rdpc

   \ We are now in a normal TL=0, IE=1, CWP=0 environment
   \ Set up Forth Machine
   0 >dmmu-miss-state		%l0	set
   'body dmmu-miss-handler	%l7	set
   setup-small-forth-engine	always	brif	nop
end-code

label immu-miss-start ( -- vadr )
   %g0  h# 38			%g1	add
   %g1  %g0  h# 20		%g1	ldxa		\ CPU struct PA
   0 >immu-miss-state		%g5	set
   %g5  %g1			%g5	add		\ DMMU stacks
   %g0				%g6	move		\ Small Save
   save-cpu-state		always	brif
   %g7					rdpc

   \ We are now in a normal TL=0, IE=1, CWP=0 environment
   \ Set up Forth Machine
   0 >dmmu-miss-state		%l0	set
   'body immu-miss-handler	%l7	set
   setup-small-forth-engine	always	brif	nop
end-code

headerless

label immu-miss-trap
   %g0  h# 30			%g5	add		\ scratch offset
   %g0  h# 10			%g6	add		\ CONTEXT offset
   %g0  %g5 h# 20		%g4	ldxa		\ MMU INFO PTR
   %g4  %g6 memory-asi		%g1	ldxa		\ Context
   %g0  h# 08			%g6	add		\ FAULT offset
   %g4  %g6 memory-asi		%g4	ldxa		\ %g4 = Fault Address.
   %g1  %g0			%g0	subcc
   immu-miss-start 0<>			brif
   %o7				%g5	move		\ save %o7
   tte-lookup				call
   nop							\ (delay) can use??
   \ %g3 = TTE
   \ %g4 = VA
   %g3	%g0			%g0	subcc
   immu-miss-start 0>=			brif
   %g5				%o7	move		\ restore link
   %g3  d# 59			%g1	sllx		\ soft[0]==1 ?
   immu-miss-start 0>=			brif
   %g3  7			%g1	and		\ (delay)
   %g1  3			%g1	mulx
   %g1  d# 13			%g1	add
   %g4	%g1			%g4	srlx
   %g4  %g1			%g4	sllx		\ VA aligned
   %o0				%g7	move
   %o1				%g6	move
   %o2				%g5	move
   %g4				%o0	move		\ VA
   %g0				%o1	move		\ CTX
   %o3				%g4	move
   %g3				%o2	move		\ TTE
   %g0  2			%o3	add		\ ITLB
   %g0 map-addr-htrap# always		htrapif
   %o0  %g0			%g0	subcc		\ Test error code
   save-state 0<>			brif		\ Abort if non-zero
   nop							\ (delay)
   %g7				%o0	move
   %g6				%o1	move
   %g5				%o2	move
   %g4				%o3	move
					retry
end-code

label dmmu-miss-trap
   %g0  h# 30			%g5	add		\ scratch offset
   %g0  h# 50			%g6	add		\ CONTEXT offset
   %g0  %g5 h# 20		%g4	ldxa		\ MMU INFO PTR
   %g4  %g6 memory-asi		%g1	ldxa		\ Context
   %g0  h# 48			%g6	add		\ FAULT offset 
   %g4  %g6 memory-asi		%g4	ldxa		\ %g4 = Fault Address.
   %g1  %g0			%g0	subcc
   dmmu-miss-start 0<>			brif
   %o7				%g5	move		\ save %o7 (delay)
   tte-lookup				call
   nop							\ (delay) can use??
   \ %g3 = TTE
   \ %g4 = VA
   %g3	%g0			%g0	subcc
   dmmu-miss-start 0>=			brif
   %g5				%o7	move		\ restore link (delay)
   %g3  d# 59			%g1	sllx		\ soft[0]
   dmmu-miss-start 0>=			brif
   %g3  7			%g1	and		\ (delay)
   %g1  3			%g1	mulx
   %g1  d# 13			%g1	add
   %g4	%g1			%g4	srlx
   %g4  %g1			%g4	sllx		\ VA aligned
   %o0				%g7	move
   %o1				%g6	move
   %o2				%g5	move
   %g4				%o0	move		\ VA
   %g0				%o1	move		\ CTX
   %o3				%g4	move
   %g3				%o2	move		\ TTE
   %g0  1			%o3	add		\ DTLB
   %g0 map-addr-htrap# always		htrapif
   %o0  %g0			%g0	subcc		\ Test error code
   save-state 0<>			brif		\ Abort if non-zero
   nop							\ (delay)
   %g7				%o0	move
   %g6				%o1	move
   %g5				%o2	move
   %g4				%o3	move
					retry
end-code
Commit	Line	Data
920dae64 AT	1	\ ========== Copyright Header Begin ==========================================
	2	\
	3	\ Hypervisor Software File: mmumiss.fth
	4	\
	5	\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	\
	7	\ - Do no alter or remove copyright notices
	8	\
	9	\ - Redistribution and use of this software in source and binary forms, with
	10	\ or without modification, are permitted provided that the following
	11	\ conditions are met:
	12	\
	13	\ - Redistribution of source code must retain the above copyright notice,
	14	\ this list of conditions and the following disclaimer.
	15	\
	16	\ - Redistribution in binary form must reproduce the above copyright notice,
	17	\ this list of conditions and the following disclaimer in the
	18	\ documentation and/or other materials provided with the distribution.
	19	\
	20	\ Neither the name of Sun Microsystems, Inc. or the names of contributors
	21	\ may be used to endorse or promote products derived from this software
	22	\ without specific prior written permission.
	23	\
	24	\ This software is provided "AS IS," without a warranty of any kind.
	25	\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	26	\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	27	\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	28	\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	29	\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	30	\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	31	\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	32	\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	33	\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	34	\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	35	\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	36	\
	37	\ You acknowledge that this software is not designed, licensed or
	38	\ intended for use in the design, construction, operation or maintenance of
	39	\ any nuclear facility.
	40	\
	41	\ ========== Copyright Header End ============================================
	42	id: @(#)mmumiss.fth 1.1 06/02/16
	43	purpose:
	44	copyright: Copyright 2006 Sun Microsystems, Inc. All Rights Reserved
	45	copyright: Use is subject to license terms.
	46
	47	headers
	48
	49	0 >mmu-defer per-cpu-defer: va>tte-data
	50
	51	headerless
	52
	53	: null-va>tte-data ( vadr ctx -- false ) 2drop false ;
	54
	55	stand-init: Initialising the per CPU miss handler
	56	['] null-va>tte-data ['] va>tte-data 3 perform-action
	57	;
	58
	59	: va>tte-installed? ( -- flag )
	60	addr va>tte-data
	61	dup x@ 0<> swap
	62	token@ ['] null-va>tte-data <> and
	63	;
	64
65	: prom-virt? ( vadr -- flag )
66	dup monvirtbase RAMtop between ( vadr flag )
67	swap vpt-base u>= or ( flag )
68	;
69	: (set-tte-soft ( tte virt -- tte' )
70	prom-virt? if >tte-soft then
71	;
72	' (set-tte-soft is set-tte-soft
73
74	: find-prom-tte ( virtual -- phys-lo phys-hi )
75	dup pgmap@ dup valid-tte? if ( va tte )
76	tuck tte>size 1- and ( tte offset )
77	s>d rot tte> d+ ( phys-lo phys-hi )
78	else ( tte )
79	drop -1 -1 ( -1 -1 )
80	then ( phys-lo phys-hi )
81	;
82
83	headers
84	: find-client-tte ( vadr context# -- tte vadr' true -or- false )
85	dup 0= if ( vaddr context# )
86	over vpt-base u>= if 2drop false exit then
87	then ( vaddr context# )
88
89	va>tte-installed? if ( vadr context# )
90	2dup va>tte-data if ( vadr context# tte )
91	rot swap dup tte>size ( context# vadr tte size )
92	rot swap round-down ( context# tte vadr )
93	\ Merge VA and CTX#
94	rot or ( tte vadr" )
95	else ( vadr context# )
96	2drop false exit
97	then ( tte vadr )
98	else ( vadr context# )
99	\ We can't handle contexts other than 0
100	if drop false exit then ( vadr )
101	dup pgmap@ tuck valid-tte? 0= if ( tte vadr )
102	2drop false exit
103	then ( tte vadr )
104	then true ( tte vadr true )
105	;
106
107	headerless
108	: (>physical) ( virt -- phys-lo phys-hi )
109	dup prom-virt? if find-prom-tte exit then
110	dup 0 find-client-tte if ( virt tte virt' )
111	drop tuck tte>size ( tte virt size )
112	1- and ( tte offset )
113	s>d rot tte> d+ ( phys-lo phys-hi )
114	else ( virt )
115	drop -1 -1 ( -1 -1 )
116	then ( phys-lo phys-hi )
117	;
118	' (>physical) is >physical
119
120	headers
121	: map? ( vadr -- )
122	dup prom-virt? if ( vadr )
123	dup pgmap@ ( vadr tte )
124	else ( vadr )
125	dup 0 find-client-tte if ( vadr tte vadr' )
126	drop ( vadr tte )
127	else ( vadr )
128	false ( vadr inv-tte )
129	then ( vadr tte )
130	then (.map) ( )
131	;
132
133	headerless
134	: resolve-immu-miss ( vadr -- ok? )
135	va>va,ctx find-client-tte if ( tte vadr )
136	itlb-tar-dir! true ( ok )
137	else ( )
138	false ( flag )
139	then ( ok? )
140	;
141
142	: resolve-dmmu-miss ( vadr -- ok? )
143	va>va,ctx find-client-tte if ( tte vadr )
144	dtlb-tar-dir! true ( flag )
145	else ( )
146	false ( flag )
147	then ( ok? )
148	;
149
150	code dmmu-miss-return ( ok? -- )
151	tos %l1 move
152	%g0 h# 38 %l5 add
153	%l5 %g0 h# 20 %l5 ldxa \ CPU struct PA
154	0 >dmmu-miss-state %l0 set
155	%l0 %l5 %g5 add \ CPU save area
156	%l1 %g0 cmp
157	restore-cpu-state 0<> brif
158	%g0 %g4 move
159	%g0 2 %g4 add \ restore and come here
160	restore-cpu-state always brif
161	%g7 rdpc
162	%g0 2 wrgl
163	0 >dmmu-miss-state %g1 set
164	small-forth-save-state always brif
165	nop
166	c;
167
168	code immu-miss-return ( ok? -- )
169	tos %l1 move
170	%g0 h# 38 %l5 add
171	%l5 %g0 h# 20 %l5 ldxa \ CPU struct PA
172	0 >immu-miss-state %l0 set
173	%l0 %l5 %g5 add \ CPU save area
174	%l1 %g0 cmp
175	restore-cpu-state 0<> brif
176	%g0 %g4 move
177	%g0 2 %g4 add \ restore and come here
178	restore-cpu-state always brif
179	%g7 rdpc
180	%g0 2 wrgl
181	0 >immu-miss-state %g1 set
182	small-forth-save-state always brif
183	nop
184	c;
185
186	headers
187	defer dmmu-miss-enter-hook ( adr -- adr )
188	defer dmmu-miss-exit-hook ( ok? -- ok? )
189	defer immu-miss-enter-hook ( adr -- adr )
190	defer immu-miss-exit-hook ( ok? -- ok? )
191	headerless
192
193	' noop to dmmu-miss-enter-hook
194	' noop to dmmu-miss-exit-hook
195	' noop to immu-miss-enter-hook
196	' noop to immu-miss-exit-hook
197
198	: immu-miss-handler ( vadr -- )
199	immu-miss-enter-hook ( vadr )
200	resolve-immu-miss ( ok? )
201	immu-miss-exit-hook ( ok? )
202	immu-miss-return ( )
203	;
204
205	: dmmu-miss-handler ( vadr -- )
206	dmmu-miss-enter-hook ( vadr )
207	resolve-dmmu-miss ( ok? )
208	dmmu-miss-exit-hook ( ok? )
209	dmmu-miss-return ( )
210	;
211
212	label dmmu-miss-start ( -- vadr )
213	%g0 h# 38 %g1 add
214	%g1 %g0 h# 20 %g1 ldxa \ CPU struct PA
215	0 >dmmu-miss-state %g5 set
216	%g5 %g1 %g5 add \ DMMU stacks
217	%g0 %g6 move \ Small Save
218	save-cpu-state always brif
219	%g7 rdpc
220
221	\ We are now in a normal TL=0, IE=1, CWP=0 environment
222	\ Set up Forth Machine
223	0 >dmmu-miss-state %l0 set
224	'body dmmu-miss-handler %l7 set
225	setup-small-forth-engine always brif nop
226	end-code
227
228	label immu-miss-start ( -- vadr )
229	%g0 h# 38 %g1 add
230	%g1 %g0 h# 20 %g1 ldxa \ CPU struct PA
231	0 >immu-miss-state %g5 set
232	%g5 %g1 %g5 add \ DMMU stacks
233	%g0 %g6 move \ Small Save
234	save-cpu-state always brif
235	%g7 rdpc
236
237	\ We are now in a normal TL=0, IE=1, CWP=0 environment
238	\ Set up Forth Machine
239	0 >dmmu-miss-state %l0 set
240	'body immu-miss-handler %l7 set
241	setup-small-forth-engine always brif nop
242	end-code
243
244	headerless
245
246	label immu-miss-trap
247	%g0 h# 30 %g5 add \ scratch offset
248	%g0 h# 10 %g6 add \ CONTEXT offset
249	%g0 %g5 h# 20 %g4 ldxa \ MMU INFO PTR
250	%g4 %g6 memory-asi %g1 ldxa \ Context
251	%g0 h# 08 %g6 add \ FAULT offset
252	%g4 %g6 memory-asi %g4 ldxa \ %g4 = Fault Address.
253	%g1 %g0 %g0 subcc
254	immu-miss-start 0<> brif
255	%o7 %g5 move \ save %o7
256	tte-lookup call
257	nop \ (delay) can use??
258	\ %g3 = TTE
259	\ %g4 = VA
260	%g3 %g0 %g0 subcc
261	immu-miss-start 0>= brif
262	%g5 %o7 move \ restore link
263	%g3 d# 59 %g1 sllx \ soft[0]==1 ?
264	immu-miss-start 0>= brif
265	%g3 7 %g1 and \ (delay)
266	%g1 3 %g1 mulx
267	%g1 d# 13 %g1 add
268	%g4 %g1 %g4 srlx
269	%g4 %g1 %g4 sllx \ VA aligned
270	%o0 %g7 move
271	%o1 %g6 move
272	%o2 %g5 move
273	%g4 %o0 move \ VA
274	%g0 %o1 move \ CTX
275	%o3 %g4 move
276	%g3 %o2 move \ TTE
277	%g0 2 %o3 add \ ITLB
278	%g0 map-addr-htrap# always htrapif
279	%o0 %g0 %g0 subcc \ Test error code
280	save-state 0<> brif \ Abort if non-zero
281	nop \ (delay)
282	%g7 %o0 move
283	%g6 %o1 move
284	%g5 %o2 move
285	%g4 %o3 move
286	retry
287	end-code
288
289	label dmmu-miss-trap
290	%g0 h# 30 %g5 add \ scratch offset
291	%g0 h# 50 %g6 add \ CONTEXT offset
292	%g0 %g5 h# 20 %g4 ldxa \ MMU INFO PTR
293	%g4 %g6 memory-asi %g1 ldxa \ Context
294	%g0 h# 48 %g6 add \ FAULT offset
295	%g4 %g6 memory-asi %g4 ldxa \ %g4 = Fault Address.
296	%g1 %g0 %g0 subcc
297	dmmu-miss-start 0<> brif
298	%o7 %g5 move \ save %o7 (delay)
299	tte-lookup call
300	nop \ (delay) can use??
301	\ %g3 = TTE
302	\ %g4 = VA
303	%g3 %g0 %g0 subcc
304	dmmu-miss-start 0>= brif
305	%g5 %o7 move \ restore link (delay)
306	%g3 d# 59 %g1 sllx \ soft[0]
307	dmmu-miss-start 0>= brif
308	%g3 7 %g1 and \ (delay)
309	%g1 3 %g1 mulx
310	%g1 d# 13 %g1 add
311	%g4 %g1 %g4 srlx
312	%g4 %g1 %g4 sllx \ VA aligned
313	%o0 %g7 move
314	%o1 %g6 move
315	%o2 %g5 move
316	%g4 %o0 move \ VA
317	%g0 %o1 move \ CTX
318	%o3 %g4 move
319	%g3 %o2 move \ TTE
320	%g0 1 %o3 add \ DTLB
321	%g0 map-addr-htrap# always htrapif
322	%o0 %g0 %g0 subcc \ Test error code
323	save-state 0<> brif \ Abort if non-zero
324	nop \ (delay)
325	%g7 %o0 move
326	%g6 %o1 move
327	%g5 %o2 move
328	%g4 %o3 move
329	retry
330	end-code