[OpenSPARC-T2-SAM] / obp / obp / fm / kernel / sparc / moveslow.fth

\ ========== Copyright Header Begin ==========================================
\ 
\ Hypervisor Software File: moveslow.fth
\ 
\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
\ 
\  - Do no alter or remove copyright notices
\ 
\  - Redistribution and use of this software in source and binary forms, with 
\    or without modification, are permitted provided that the following 
\    conditions are met: 
\ 
\  - Redistribution of source code must retain the above copyright notice, 
\    this list of conditions and the following disclaimer.
\ 
\  - Redistribution in binary form must reproduce the above copyright notice,
\    this list of conditions and the following disclaimer in the
\    documentation and/or other materials provided with the distribution. 
\ 
\    Neither the name of Sun Microsystems, Inc. or the names of contributors 
\ may be used to endorse or promote products derived from this software 
\ without specific prior written permission. 
\ 
\     This software is provided "AS IS," without a warranty of any kind. 
\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
\ 
\ You acknowledge that this software is not designed, licensed or
\ intended for use in the design, construction, operation or maintenance of
\ any nuclear facility. 
\ 
\ ========== Copyright Header End ============================================
\ moveslow.fth 1.5 93/10/21
\ Copyright 1985-1990 Bradley Forthware

\ Mike Saari's blazing `move' ...
\ This implements the MOVE instruction.  It is optimized
\ for speed, particularly when longword stores may be used.
\ This version omits the doubleword optimization for machines where
\ doubleword operations do not work.

code (move)  ( src dst cnt -- )
			\ tos = Count
   sp 1 /n*  scr   nget	\ scr = Src address
   sp 0 /n*  sc1   nget	\ sc1 = Dst address
			\ sc2 = Temp. data being transferred
			\ sc3 = src xor drc, low bits=0 indicates compatible
			\ sc4 = Working src in loops
			\       (also temp last+1 address)
			\ sc5 = Working dst in loops
			\ sc6 = Loop index

   scr sc1  %g0  subcc	\ Src > dst?
   > if			\ Then copy low-to-high
      scr sc1  sc3  xor		\ (delay) sc3 low bits=0 indicates compatible

      tos h# 10   %g0  subcc	\ Enough bytes to bother optimizing?
      >= if			\ Otherwise, just skip to byte move
         sc3 1    %g0  andcc	\ (delay) =0 if at least shortword aligned
         0= if			\ Otherwise, just skip to byte move

            scr 1   %g0  andcc		\ (delay) Not on halfword boundary?
            0<> if		\ Ensure halfword alignment (lower)
               scr 0  sc2  ldub		\ (delay) Load bottom byte
               sc2  sc1 0  stb		\ Store byte
               scr 1  scr  add		\ Advance by one byte
               sc1 1  sc1  add		\  "
               tos 1  tos  sub		\ Decrement count
            then

            sc3 2   %g0  andcc		\ =0 if at least longword aligned
            0= if			\ Otherwise, skip to halfword case

               scr 2  %g0  andcc	\ (delay) Not on longword boundary?
               0<> if			\ Ensure longword alignment (lower)
                  scr 0  sc2  lduh	\ (delay) Load bottom halfword
                  sc2  sc1 0  sth	\ Store halfword
                  scr 2  scr  add	\ Advance by one halfword
                  sc1 2  sc1  add	\  "
                  tos 2  tos  sub       \ Decrement count
               then

				\ Longword Copy Loop (low-to-high)
               tos 3    sc6  andn	\ Index w/ even multiples of 4
               scr sc6  scr  add	\ src = src+index
               scr   4  sc4  sub	\ Working src = src+index-4
               sc1 sc6  sc1  add	\ dst = dst+index
               sc1   4  sc5  sub	\ Working dst = dst+index-4
               %g0 sc6  sc6  subcc	\ Negate index
               begin
               < while
                  sc6 4     sc6  addcc	\ (delay) Increment index
                  sc4 sc6   sc2  ld	\ Load longword
               repeat
                  sc2   sc5 sc6  st	\ (delay) Store longword
               tos 3   tos   and	\ At end, adjust cnt for few remaining

            else 		\ Halfword Copy Loop (low-to-high)
               nop			\ (delay)
               tos 1  sc6  andn		\ Index w/ even multiples of 2
               scr sc6  scr  add	\ src = src+index
               scr   2  sc4  sub	\ Working src = src+index-2
               sc1 sc6  sc1  add	\ dst = dst+index
               sc1   2  sc5  sub	\ Working dst = dst+index-2
               %g0 sc6  sc6  subcc	\ Negate index
               begin
               < while
                  sc6 2     sc6  addcc	\ (delay) Increment index
                  sc4 sc6   sc2  lduh	\ Load halfword
               repeat
                  sc2   sc5 sc6  sth	\ (delay) Store halfword

               tos 1   tos   and	\ At end, adjust cnt for few remaining
            then
         then
      then	\ Now do a normal byte move for all remaining bytes (at top)

      \ Byte Copy Loop (low-to-high)
				\ (tos = index)
      scr tos  scr  add
      scr   1  sc4  sub		\ Working src = src+cnt-1
      sc1 tos  sc1  add
      sc1   1  sc5  sub		\ Working dst = dst+cnt-1
      %g0 tos  sc6  subcc	\ Negate index
      begin
      < while
         sc6 1     sc6  addcc	\ (delay) Increment cnt
         sc4 sc6   sc2  ldub	\ Load byte
      repeat
         sc2   sc5 sc6  stb	\ (delay) Store byte

   else  		\ Copy high-to-low case
      nop			\ (delay)
      tos h# 10   %g0  subcc	\ Enough bytes to bother optimizing?
      >= if			\ Otherwise, just skip to byte move
         sc3 1    %g0  andcc	\ (delay) =0 if at least shortword aligned
         0= if			\ Otherwise, just skip to byte move

            scr tos  sc4  add		\ (delay) Calculate last+1 address

            sc4 1    %g0  andcc		\ Not on halfword boundary? (at top)
            0<> if		\ Ensure halfword alignment (at top)
               sc4 -1   sc2  ldub	\ (delay) Load top byte
               tos 1    tos  sub	\ Decrement count
               sc2  sc1 tos  stb	\ Store byte
               sc4 1    sc4  sub	\ Recalculate last+1 address
            then

            sc3 2   %g0  andcc		\ =0 if at least longword aligned
            0= if		\ Otherwise, skip to halfword case

               sc4 2    %g0  andcc	\ (delay) Not on longword boundary? (at top)
               0<> if		\ Ensure longword alignment (at top)
                  sc4 -2   sc2  lduh	\ (delay) Load top halfword
                  tos 2    tos  sub	\ Decrement count
                  sc2  sc1 tos  sth	\ Store halfword
                  sc4 2    sc4  sub	\ Recalculate last+1 address
               then

				\ Longword Copy Loop (high-to-low)
               scr 4   sc4   add	\ Working src = src+4
               sc1 4   sc5   add	\ Working dst = dst+4
               tos 4   sc6   subcc	\ Loop index = cnt-4
               begin
               >= while
                  sc6 4     sc6  subcc	\ (delay) Decrement index
                  sc4 sc6   sc2  ld	\ Load longword
               repeat
                  sc2   sc5 sc6  st	\ (delay) Store longword

               tos 3   tos   and	\ At end, adjust cnt for few remaining

            else		\ Halfword Copy Loop (high-to-low)
               nop			\ (delay)
               scr 2   sc4   add	\ Working src = src+2
               sc1 2   sc5   add	\ Working dst = dst+2
               tos 2   sc6   subcc	\ Loop index = cnt-2
               begin
               >= while
                  sc6 2     sc6  subcc	\ (delay) Decrement index
                  sc4 sc6   sc2  lduh	\ Load halfword
               repeat
                  sc2   sc5 sc6  sth	\ (delay) Store halfword

               tos 1   tos   and	\ At end, adjust cnt for few remaining
            then
         then
      then	\ Now do a normal byte move for all remaining bytes (at bottom)

      \ Byte Copy Loop (high-to-low)
      scr 1     sc4  add	\ Working src = src+1
      sc1 1     sc5  add	\ Working dst = dst+1
      tos 1     tos  subcc	\ Loop index = cnt-1
      begin
      >= while
         tos 1     tos  subcc	\ (delay) Decrement index
         sc4 tos   sc2  ldub	\ Load byte
      repeat
         sc2   sc5 tos  stb	\ (delay) Store byte
   then

   sp 2 /n*  tos   nget	\ Delete 3 stack items
   sp 3 /n*  sp    add	\   "
c;
defer move
' (move) is move
Commit	Line	Data
920dae64 AT	1	\ ========== Copyright Header Begin ==========================================
	2	\
	3	\ Hypervisor Software File: moveslow.fth
	4	\
	5	\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	\
	7	\ - Do no alter or remove copyright notices
	8	\
	9	\ - Redistribution and use of this software in source and binary forms, with
	10	\ or without modification, are permitted provided that the following
	11	\ conditions are met:
	12	\
	13	\ - Redistribution of source code must retain the above copyright notice,
	14	\ this list of conditions and the following disclaimer.
	15	\
	16	\ - Redistribution in binary form must reproduce the above copyright notice,
	17	\ this list of conditions and the following disclaimer in the
	18	\ documentation and/or other materials provided with the distribution.
	19	\
	20	\ Neither the name of Sun Microsystems, Inc. or the names of contributors
	21	\ may be used to endorse or promote products derived from this software
	22	\ without specific prior written permission.
	23	\
	24	\ This software is provided "AS IS," without a warranty of any kind.
	25	\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	26	\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	27	\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	28	\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	29	\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	30	\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	31	\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	32	\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	33	\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	34	\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	35	\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	36	\
	37	\ You acknowledge that this software is not designed, licensed or
	38	\ intended for use in the design, construction, operation or maintenance of
	39	\ any nuclear facility.
	40	\
	41	\ ========== Copyright Header End ============================================
	42	\ moveslow.fth 1.5 93/10/21
	43	\ Copyright 1985-1990 Bradley Forthware
	44
	45	\ Mike Saari's blazing `move' ...
	46	\ This implements the MOVE instruction. It is optimized
	47	\ for speed, particularly when longword stores may be used.
	48	\ This version omits the doubleword optimization for machines where
	49	\ doubleword operations do not work.
	50
	51	code (move) ( src dst cnt -- )
	52	\ tos = Count
	53	sp 1 /n* scr nget \ scr = Src address
	54	sp 0 /n* sc1 nget \ sc1 = Dst address
	55	\ sc2 = Temp. data being transferred
	56	\ sc3 = src xor drc, low bits=0 indicates compatible
	57	\ sc4 = Working src in loops
	58	\ (also temp last+1 address)
	59	\ sc5 = Working dst in loops
	60	\ sc6 = Loop index
	61
	62	scr sc1 %g0 subcc \ Src > dst?
	63	> if \ Then copy low-to-high
	64	scr sc1 sc3 xor \ (delay) sc3 low bits=0 indicates compatible
65
66	tos h# 10 %g0 subcc \ Enough bytes to bother optimizing?
67	>= if \ Otherwise, just skip to byte move
68	sc3 1 %g0 andcc \ (delay) =0 if at least shortword aligned
69	0= if \ Otherwise, just skip to byte move
70
71	scr 1 %g0 andcc \ (delay) Not on halfword boundary?
72	0<> if \ Ensure halfword alignment (lower)
73	scr 0 sc2 ldub \ (delay) Load bottom byte
74	sc2 sc1 0 stb \ Store byte
75	scr 1 scr add \ Advance by one byte
76	sc1 1 sc1 add \ "
77	tos 1 tos sub \ Decrement count
78	then
79
80	sc3 2 %g0 andcc \ =0 if at least longword aligned
81	0= if \ Otherwise, skip to halfword case
82
83	scr 2 %g0 andcc \ (delay) Not on longword boundary?
84	0<> if \ Ensure longword alignment (lower)
85	scr 0 sc2 lduh \ (delay) Load bottom halfword
86	sc2 sc1 0 sth \ Store halfword
87	scr 2 scr add \ Advance by one halfword
88	sc1 2 sc1 add \ "
89	tos 2 tos sub \ Decrement count
90	then
91
92	\ Longword Copy Loop (low-to-high)
93	tos 3 sc6 andn \ Index w/ even multiples of 4
94	scr sc6 scr add \ src = src+index
95	scr 4 sc4 sub \ Working src = src+index-4
96	sc1 sc6 sc1 add \ dst = dst+index
97	sc1 4 sc5 sub \ Working dst = dst+index-4
98	%g0 sc6 sc6 subcc \ Negate index
99	begin
100	< while
101	sc6 4 sc6 addcc \ (delay) Increment index
102	sc4 sc6 sc2 ld \ Load longword
103	repeat
104	sc2 sc5 sc6 st \ (delay) Store longword
105	tos 3 tos and \ At end, adjust cnt for few remaining
106
107	else \ Halfword Copy Loop (low-to-high)
108	nop \ (delay)
109	tos 1 sc6 andn \ Index w/ even multiples of 2
110	scr sc6 scr add \ src = src+index
111	scr 2 sc4 sub \ Working src = src+index-2
112	sc1 sc6 sc1 add \ dst = dst+index
113	sc1 2 sc5 sub \ Working dst = dst+index-2
114	%g0 sc6 sc6 subcc \ Negate index
115	begin
116	< while
117	sc6 2 sc6 addcc \ (delay) Increment index
118	sc4 sc6 sc2 lduh \ Load halfword
119	repeat
120	sc2 sc5 sc6 sth \ (delay) Store halfword
121
122	tos 1 tos and \ At end, adjust cnt for few remaining
123	then
124	then
125	then \ Now do a normal byte move for all remaining bytes (at top)
126
127	\ Byte Copy Loop (low-to-high)
128	\ (tos = index)
129	scr tos scr add
130	scr 1 sc4 sub \ Working src = src+cnt-1
131	sc1 tos sc1 add
132	sc1 1 sc5 sub \ Working dst = dst+cnt-1
133	%g0 tos sc6 subcc \ Negate index
134	begin
135	< while
136	sc6 1 sc6 addcc \ (delay) Increment cnt
137	sc4 sc6 sc2 ldub \ Load byte
138	repeat
139	sc2 sc5 sc6 stb \ (delay) Store byte
140
141	else \ Copy high-to-low case
142	nop \ (delay)
143	tos h# 10 %g0 subcc \ Enough bytes to bother optimizing?
144	>= if \ Otherwise, just skip to byte move
145	sc3 1 %g0 andcc \ (delay) =0 if at least shortword aligned
146	0= if \ Otherwise, just skip to byte move
147
148	scr tos sc4 add \ (delay) Calculate last+1 address
149
150	sc4 1 %g0 andcc \ Not on halfword boundary? (at top)
151	0<> if \ Ensure halfword alignment (at top)
152	sc4 -1 sc2 ldub \ (delay) Load top byte
153	tos 1 tos sub \ Decrement count
154	sc2 sc1 tos stb \ Store byte
155	sc4 1 sc4 sub \ Recalculate last+1 address
156	then
157
158	sc3 2 %g0 andcc \ =0 if at least longword aligned
159	0= if \ Otherwise, skip to halfword case
160
161	sc4 2 %g0 andcc \ (delay) Not on longword boundary? (at top)
162	0<> if \ Ensure longword alignment (at top)
163	sc4 -2 sc2 lduh \ (delay) Load top halfword
164	tos 2 tos sub \ Decrement count
165	sc2 sc1 tos sth \ Store halfword
166	sc4 2 sc4 sub \ Recalculate last+1 address
167	then
168
169	\ Longword Copy Loop (high-to-low)
170	scr 4 sc4 add \ Working src = src+4
171	sc1 4 sc5 add \ Working dst = dst+4
172	tos 4 sc6 subcc \ Loop index = cnt-4
173	begin
174	>= while
175	sc6 4 sc6 subcc \ (delay) Decrement index
176	sc4 sc6 sc2 ld \ Load longword
177	repeat
178	sc2 sc5 sc6 st \ (delay) Store longword
179
180	tos 3 tos and \ At end, adjust cnt for few remaining
181
182	else \ Halfword Copy Loop (high-to-low)
183	nop \ (delay)
184	scr 2 sc4 add \ Working src = src+2
185	sc1 2 sc5 add \ Working dst = dst+2
186	tos 2 sc6 subcc \ Loop index = cnt-2
187	begin
188	>= while
189	sc6 2 sc6 subcc \ (delay) Decrement index
190	sc4 sc6 sc2 lduh \ Load halfword
191	repeat
192	sc2 sc5 sc6 sth \ (delay) Store halfword
193
194	tos 1 tos and \ At end, adjust cnt for few remaining
195	then
196	then
197	then \ Now do a normal byte move for all remaining bytes (at bottom)
198
199	\ Byte Copy Loop (high-to-low)
200	scr 1 sc4 add \ Working src = src+1
201	sc1 1 sc5 add \ Working dst = dst+1
202	tos 1 tos subcc \ Loop index = cnt-1
203	begin
204	>= while
205	tos 1 tos subcc \ (delay) Decrement index
206	sc4 tos sc2 ldub \ Load byte
207	repeat
208	sc2 sc5 tos stb \ (delay) Store byte
209	then
210
211	sp 2 /n* tos nget \ Delete 3 stack items
212	sp 3 /n* sp add \ "
213	c;
214	defer move
215	' (move) is move