[OpenSPARC-T2-SAM] / sam-t2 / docs / mmi / PciBusIf.html

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<title>SPARC Architectural Model: Device and Utility API</title>
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<h2>class PciBusIf</h2>
#include "pci.h"

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<pre>
virtual int busif_access(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint32_t size, uint64_t* buf);
virtual int busif_add_device(const char *devname, int device, int function);
virtual int busif_delete_device(const char *devname);
virtual int busif_map(const char *devname, pci_space_t, uint64_t base, uint64_t size);
virtual int busif_unmap(const char *devname, pci_space_t);
virtual int busif_add_interrupt(const char *device_name, int *device_number, int *slot_irl, const char **host);
virtual int busif_free_interrupt(int dev_number);
virtual int busif_interrupt_in(bool set, int dev_type, int dev_number, int line);
virtual int busif_set_int_pin(int pin, bool raise, int device, module_t *caller);
virtual int busif_dma_out(uint64_t vaddr, void *data, long count, module_t *caller);
virtual int busif_dma_in(uint64_t vaddr, void *data, long count, module_t *caller);
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<h4>Description</h4>
This is an abstract class that defines the interface between modules connected to a PCI Bus.
This configuration is an example:
<p><pre>
schizo24 &lt;-&gt; schizo24A &lt;-&gt; sample24A1
         &lt;-&gt; schizo24B &lt;-&gt; sample24B1
</pre>
<p> schizo24&nbsp;&nbsp; is a PCI host bridge at AID=24 (0x18).
<br>schizo24A&nbsp; is PCI bus#0 on leaf A of the schizo.
<br>schizo24B&nbsp; is PCI bus#0 on leaf B. (Leaf B is NOT bus#1!)
<br>sample24A1 is PCI device 1 on schizo24A.
<br>sample24B1 is PCI device 1 on schizo24B.
<p>The configuration file looks like this:
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sysconf schizo  schizo24   aid=24 pciA=schizo24A pciB=schizo24B
sysconf pci_bus schizo24A  bridge=schizo24
sysconf sample  sample24A1 bus=schizo24A dev=1 fun=0
sysconf pci_bus schizo24B  bridge=schizo24
sysconf sample  sample24B1 bus=schizo24B dev=1 fun=0
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<p>Both schizo and pci_bus export the PciBusIf interface.
<p>PCI devices, like sample, call the PciBusIf interface, and they export a PciDevIf interface.
<p><b>busif_access</b>: I/O access in the downstream direction (from CPU to device).
A CPU read or write first goes to a schizo based on the address range (determined by aid).
The schizo routes the access to either pciA or pciB depending on the address range.
The pci_bus routes the access to one of its devices
depending on the device PCI address range (see PciDev::dev_set_space).
The last access is done through the PciDevIf interface.
<p><b>busif_dma_out</b> and <b>busif_dma_in</b>: I/O access in the upstream direction.
DMA works with PCI addresses.
The host bridge (schizo) has an IOMMU which translates PCI addresses into physical memory addresses.
<p><b>busif_add_device</b> and <b>busif_delete_device</b> attach or detach devices on a bus.
A device attaches itself to a bus when it detects that the bus has been configured.
The bus maps the device into the PCI configuration space.
<p><b>busif_map</b> and <b>busif_unmap</b> manage PCI address space mappings for devices.
This is used for PCI I/O, mem32, and mem64 spaces (but not config space.)
<p><b>busif_add_interrupt</b> and <b>busif_free_interrupt</b> manage interrupt resources in the host bridge (schizo).
A PCI device makes a request for an interrupt vector. The pci_bus simply forwards it towards the bridge.
<p><b>busif_interrupt_in</b> requests an interrupt. Called by a PCI device.
<p><b>busif_set_int_pin</b> requests an interrupt on pin A, B, C, or D.
The host bridge assigns interrupt resources automatically.
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Commit	Line	Data
920dae64 AT	1	<html>
	2	<head>
	3	<title>SPARC Architectural Model: Device and Utility API</title>
	4	</head>
	5	<body bgcolor="#FFFFFF" LANG="en-US">
	6
	7	<h2>class PciBusIf</h2>
	8	#include "pci.h"
	9
	10	<font size=-1>
	11	<pre>
	12	virtual int busif_access(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint32_t size, uint64_t* buf);
	13	virtual int busif_add_device(const char *devname, int device, int function);
	14	virtual int busif_delete_device(const char *devname);
	15	virtual int busif_map(const char *devname, pci_space_t, uint64_t base, uint64_t size);
	16	virtual int busif_unmap(const char *devname, pci_space_t);
	17	virtual int busif_add_interrupt(const char device_name, int device_number, int slot_irl, const char *host);
	18	virtual int busif_free_interrupt(int dev_number);
	19	virtual int busif_interrupt_in(bool set, int dev_type, int dev_number, int line);
	20	virtual int busif_set_int_pin(int pin, bool raise, int device, module_t *caller);
	21	virtual int busif_dma_out(uint64_t vaddr, void data, long count, module_t caller);
	22	virtual int busif_dma_in(uint64_t vaddr, void data, long count, module_t caller);
	23	</pre>
	24	</font>
	25
	26	<h4>Description</h4>
	27	This is an abstract class that defines the interface between modules connected to a PCI Bus.
	28	This configuration is an example:
	29	<p><pre>
	30	schizo24 <-> schizo24A <-> sample24A1
	31	<-> schizo24B <-> sample24B1
	32	</pre>
	33	<p> schizo24   is a PCI host bridge at AID=24 (0x18).
	34	<br>schizo24A  is PCI bus#0 on leaf A of the schizo.
	35	<br>schizo24B  is PCI bus#0 on leaf B. (Leaf B is NOT bus#1!)
	36	<br>sample24A1 is PCI device 1 on schizo24A.
	37	<br>sample24B1 is PCI device 1 on schizo24B.
	38	<p>The configuration file looks like this:
	39	<font size=-1>
	40	<pre>
	41	sysconf schizo schizo24 aid=24 pciA=schizo24A pciB=schizo24B
	42	sysconf pci_bus schizo24A bridge=schizo24
	43	sysconf sample sample24A1 bus=schizo24A dev=1 fun=0
	44	sysconf pci_bus schizo24B bridge=schizo24
	45	sysconf sample sample24B1 bus=schizo24B dev=1 fun=0
	46	</pre>
	47	</font>
	48	<p>Both schizo and pci_bus export the PciBusIf interface.
	49	<p>PCI devices, like sample, call the PciBusIf interface, and they export a PciDevIf interface.
	50	<p><b>busif_access</b>: I/O access in the downstream direction (from CPU to device).
	51	A CPU read or write first goes to a schizo based on the address range (determined by aid).
	52	The schizo routes the access to either pciA or pciB depending on the address range.
	53	The pci_bus routes the access to one of its devices
	54	depending on the device PCI address range (see PciDev::dev_set_space).
	55	The last access is done through the PciDevIf interface.
	56	<p><b>busif_dma_out</b> and <b>busif_dma_in</b>: I/O access in the upstream direction.
	57	DMA works with PCI addresses.
	58	The host bridge (schizo) has an IOMMU which translates PCI addresses into physical memory addresses.
	59	<p><b>busif_add_device</b> and <b>busif_delete_device</b> attach or detach devices on a bus.
	60	A device attaches itself to a bus when it detects that the bus has been configured.
	61	The bus maps the device into the PCI configuration space.
	62	<p><b>busif_map</b> and <b>busif_unmap</b> manage PCI address space mappings for devices.
	63	This is used for PCI I/O, mem32, and mem64 spaces (but not config space.)
	64	<p><b>busif_add_interrupt</b> and <b>busif_free_interrupt</b> manage interrupt resources in the host bridge (schizo).
65	A PCI device makes a request for an interrupt vector. The pci_bus simply forwards it towards the bridge.
66	<p><b>busif_interrupt_in</b> requests an interrupt. Called by a PCI device.
67	<p><b>busif_set_int_pin</b> requests an interrupt on pin A, B, C, or D.
68	The host bridge assigns interrupt resources automatically.
69	</body>
70	</html>