Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / docs / mmi / sam-mmi.html
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1<html>
2<head>
3 <title>SPARC Architectural Model: Device and Utility API</title>
4</head>
5<body bgcolor="#FFFFFF" LANG="en-US">
6&nbsp;
7<h2>SPARC Architectural Model: Device and Utility API</h2>
8<h4>Overview and Examples</h4>
9<ul>
10 <a href="intro.html">Introduction</a>
11<br><a href="SAM-modules.html">SAM device modules</a>
12</ul>
13
14<h4>Common Classes</h4>
15SAM devices have been implemented using a common Module base class. This is not part of MMI, but uses MMI to provide a C++ class interface with several features common to all classes.
16<ul>
17<li><a href="Module.html">Module</a> &nbsp;&nbsp; base class for all modules
18<li><a href="PciDev.html">PciDev</a>&nbsp;&nbsp; base class for PCI devices
19<li> <a href="PciDevIf.html">PciDevIf</a>&nbsp;&nbsp; PCI device interface
20<li><a href="PciBusIf.html">PciBusIf</a>&nbsp;&nbsp; PCI bus interface
21</ul>
22
23<h4>Module instantiation</h4>
24<ul>
25 <li><a href="mmi_register_instance_creator.html">mmi_register_instance_creator</a>
26 <li><a href="mmi_register_instance.html">mmi_register_instance</a>
27 <li><a href="mmi_get_instance.html">mmi_get_instance</a>
28</ul>
29
30<h4>Module connectivity</h4>
31<ul>
32 <li><a href="mmi_map_physio.html">mmi_map_physio</a>
33 <li><a href="mmi_register_config_cb.html">mmi_register_config_cb</a>
34 <li><a href="mmi_register_interface_cb.html">mmi_register_interface_cb</a>
35 <li><a href="mmi_get_interface.html">mmi_get_interface</a>
36 <li><a href="mmi_register_modinfo_cb.html">mmi_register_modinfo_cb</a>
37</ul>
38
39<h4>Interrupts</h4>
40<ul>
41 <li><a href="mmi_interrupt.html">mmi_interrupt_packet</a>
42 <li><a href="mmi_interrupt.html">mmi_interrupt_vector</a>
43</ul>
44
45<h2> SAM-dependent MMI functions </h2>
46These functions are provided for SAM-specific devices, tracing features etc.
47
48<h4>Callbacks (SAM-dependent)</h4>
49<ul>
50<li><a href="mmi_register_cb_data.html">mmi_register_cb_data</a>
51<li><a href="mmi_get_cb_data.html">mmi_get_cb_data</a>
52<li><a href="mmi_register_cb_cycle.html">mmi_register_cb_cycle</a>
53<li><a href="mmi_register_cb_cycle.html">mmi_unregister_cb_cycle</a>
54<li><a href="mmi_register_cb_instr.html">mmi_register_cb_instr</a>
55<li><a href="mmi_register_cb_instr.html">mmi_register_cb_memop</a>
56<li><a href="mmi_register_cb_instr.html">mmi_register_cb_trap</a>
57<li><a href="mmi_register_cb_instr.html">mmi_register_cb_trapexit</a>
58<li><a href="mmi_register_cb_instr.html">mmi_register_cb_tlb</a>
59<li><a href="mmi_register_cb_instr.html">mmi_register_cb_cpustate</a>
60<li><a href="mmi_register_cb_dma.html">mmi_register_cb_dma</a>
61<li><a href="mmi_set_cb_mask.html">mmi_set_cb_mask</a>
62<li><a href="mmi_register_io_action.html">mmi_register_io_action</a>
63<li><a href="mmi_register_asi_action.html">mmi_register_asi_action</a>
64</ul>
65
66<h4>Memory access</h4>
67<ul>
68<li><a href="mmi_get_memobj.html">mmi_get_memobj</a>
69<li><a href="mmi_iommu_va2pa.html">mmi_iommu_va2pa</a>
70<li><a href="mmi_memread.html">mmi_memread8s</a>
71<li><a href="mmi_memread.html">mmi_memread8u</a>
72<li><a href="mmi_memread.html">mmi_memread16s</a>
73<li><a href="mmi_memread.html">mmi_memread16u</a>
74<li><a href="mmi_memread.html">mmi_memread32s</a>
75<li><a href="mmi_memread.html">mmi_memread32u</a>
76<li><a href="mmi_memread.html">mmi_memread64s</a>
77<li><a href="mmi_memread.html">mmi_memread64u</a>
78<li><a href="mmi_memread_blk.html">mmi_memread_blk</a>
79<li><a href="mmi_memwrite.html">mmi_memwrite8</a>
80<li><a href="mmi_memwrite.html">mmi_memwrite16</a>
81<li><a href="mmi_memwrite.html">mmi_memwrite32</a>
82<li><a href="mmi_memwrite.html">mmi_memwrite64</a>
83<li><a href="mmi_memwrite_blk.html">mmi_memwrite_blk</a>
84<li><a href="mmi_mem_atomics.html">mmi_mem_casx</a>
85</ul>
86
87
88<h4>Examine and Modify cpu registers</h4>
89<ul>
90<li><a href="mmi_get_cpu_ireg.html">mmi_get_cpu_ireg</a>
91<li><a href="mmi_get_cpu_ireg.html">mmi_get_cpu_freg</a>
92<li><a href="mmi_get_cpu_ireg.html">mmi_get_cpu_ctlreg</a>
93<li><a href="mmi_get_cpu_ireg.html">mmi_get_cpu_tlreg</a>
94<li><a href="mmi_set_cpu_ireg.html">mmi_set_cpu_ireg</a>
95<li><a href="mmi_set_cpu_ireg.html">mmi_set_cpu_freg</a>
96<li><a href="mmi_set_cpu_ireg.html">mmi_set_cpu_ctlreg</a>
97<li><a href="mmi_set_cpu_ireg.html">mmi_set_cpu_tlreg</a>
98</ul>
99
100<h4>Simulator control and status</h4>
101<ul>
102<li><a href="mmi_get_ncpu.html">mmi_get_ncpu</a>
103<li><a href="mmi_get_ncpu.html">mmi_get_cpuid</a>
104<li><a href="mmi_get_ncpu.html">mmi_get_cpuptr</a>
105<li><a href="mmi_get_cpufreq.html">mmi_get_cpufreq</a>
106<li><a href="mmi_get_comment_string.html">mmi_get_comment_string</a>
107<li><a href="mmi_delay_execution.html">mmi_delay_execution</a>
108<li><a href="mmi_complete_delayed_load.html">mmi_complete_delayed_load</a>
109<li><a href="mmi_run.html">mmi_stop</a>
110<li><a href="mmi_run.html">mmi_run</a>
111<li><a href="mmi_run.html">mmi_is_stopped</a>
112<li><a href="mmi_run.html">mmi_run single_thread</a>
113<li><a href="mmi_perror.html">mmi_perror</a>
114</ul>
115
116<h4>User Interface</i>
117<ul>
118<li><a href="mmi_register_ui_variable.html">mmi_register_ui_variable</a>
119</ul>
120
121</body>
122</html>