Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / api / sam / src / 1c2t_2sas_scsi_fc.rc
CommitLineData
920dae64
AT
1conf ramsize 256M
2conf mips 100
3conf stickfreq 1417000000
4
5# number of worker-threads per physical cpu
6conf cpu_per_thread 1
7
8# hypervisor partition description, size 8k
9load bin 1c2t-hv.bin 0x180000
10
11# machine description , size 8k
12load bin 1c2t-md.bin 0x100000
13
14# nvram for obp, size 8k
15load bin ./nvram.bin 0x1f11000000
16
17sysconf cpu name=cpu0 cpu-type=riesling_n2_vcpu clock-frequency=1417000000 id=0
18sysconf cpu name=cpu1 cpu-type=riesling_n2_vcpu clock-frequency=1417000000 id=1
19
20sysconf ioram reset start_pa=0xfff0000000 size=0x10000 file=reset.bin sparse
21sysconf ioram hv start_pa=0xfff0010000 size=0x70000 file=q.bin sparse
22sysconf ioram obp start_pa=0xfff0080000 size=0x80000 file=openboot.bin sparse
23
24# hypervisor console device
25sysconf serial_4v hypervisor-console base=0xfff0ca0000 size=0x1000
26
27# guest console device
28sysconf serial_4v guest-console base=0x9f10002000 size=0x51
29
30# tod device
31sysconf tod_4v tod base=0xfff0d22000 size=0x8 tod=01010000002000
32
33# ncu, piu
34sysconf n2_ncu ncu
35sysconf n2_piu piu bus=pcie_a ncu=ncu
36
37# PCIe bus attached to piu
38sysconf pcie_bus pcie_a bridge=piu
39
40# PCIe-PCIe switch, downstram are two PCIe buses: pcie_b and pcie_c
41sysconf pcie_bridge b_0 bus=pcie_a dev=0 fun=0 secbus=pcie_int upstream
42sysconf pcie_bus pcie_int bridge=b_0
43sysconf pcie_bridge b_1 bus=pcie_int dev=0 fun=0 secbus=pcie_b
44sysconf pcie_bridge b_2 bus=pcie_int dev=1 fun=0 secbus=pcie_c
45sysconf pcie_bridge b_3 bus=pcie_int dev=2 fun=0 secbus=pcie_d
46sysconf pcie_bus pcie_b bridge=b_1
47sysconf pcie_bus pcie_c bridge=b_2
48sysconf pcie_bus pcie_d bridge=b_3
49
50# SAS controller 1
51sysconf sas sas0 bus=pcie_b dev=0 fun=0 targets=sasdisk.init
52
53# SAS controller 2
54sysconf sas sas1 bus=pcie_c dev=0 fun=0 targets=sasdisk1.init
55
56# PCIe-PCI bridge
57sysconf bridge b0 bus=pcie_d dev=0 fun=0 secbus=pcia
58sysconf bridge b2 bus=pcie_d dev=0 fun=2 secbus=pcib
59
60# PCI bus
61sysconf pci_bus pcia bridge=b0
62sysconf pci_bus pcib bridge=b2
63
64# SCSI controller
65sysconf scsi scsi0 bus=pcia dev=1 fun=0 targets=scsidisk.init
66
67# ll
68sysconf ll ll0 bus=pcia dev=2 fun=0
69
70#gem
71sysconf gem ge1 bus=pcia dev=3 fun=0
72
73# fc controller
74sysconf fc fc1 bus=pcib dev=1 fun=0 targets=fcdisk.init
75
76#cassini
77sysconf cassini ce0 bus=pcib dev=7 fun=0
78
79# to start the SAM FE, commented for now
80#mod load py libpy.so
81#py -i ./pfe/samefe/sam_n2.py --blaze n2