Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / api / sam / src / sam-s10.py
CommitLineData
920dae64
AT
1# ========== Copyright Header Begin ==========================================
2#
3# OpenSPARC T2 Processor File: sam-s10.py
4# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6#
7# The above named program is free software; you can redistribute it and/or
8# modify it under the terms of the GNU General Public
9# License version 2 as published by the Free Software Foundation.
10#
11# The above named program is distributed in the hope that it will be
12# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14# General Public License for more details.
15#
16# You should have received a copy of the GNU General Public
17# License along with this work; if not, write to the Free Software
18# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19#
20# ========== Copyright Header End ============================================
21# ToDo
22#
23# Commandline options:
24# -a for auto boot
25# -p for number of running strands
26# -m for mask of running strands (iso -p)
27# -w for number of worker threads
28
29cfg_cpu = '1c1t'
30#cfg_cpu = '1c2t'
31#cfg_cpu = '8c4t'
32
33bin = [
34 #('nvram1-auto', 0x1f11000000)
35 ('nvram1', 0x1f11000000)
36, (cfg_cpu+'-md.bin', 0x1f12000000)
37, (cfg_cpu+'-hv.bin', 0x1f12080000)
38, ('reset.bin', 0xfff0000000)
39, ('q.bin', 0xfff0010000)
40, ('openboot.bin', 0xfff0080000)
41, ('disk1', 0x1f40000000)
42]
43
44print
45for (file,base) in bin:
46 print 'Loading %(base)s - %(file)s' % {'file':file, 'base':hex(base)}
47 sim.mem.load(file,base)
48
49# Hack the guest console address to morf a RAM
50# address into a I/O address.
51
52guest_bin = 0x1f12080148
53guest_old = 0x1f10000000
54guest_new = 0x9f10000000
55
56for i in range(0,64):
57 if sim.mem.x[guest_bin] == guest_old:
58 print
59 print 'Patching guest console UART address at',guest_bin
60 sim.mem.x[guest_bin] = guest_new
61 break
62 guest_bin += 0x50
63
64print
65
66def dec(x):
67 return '%d' % x
68
69import os
70
71def q():
72 os._exit(0)
73
74