Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / dev / resetgen / src / N2_ResetGen.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: N2_ResetGen.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================

#include <iostream>
#include <unistd.h>
#include "N2_ResetGen.h"
#include "N2_Model.h"
#include "SS_Io.h"
#include "N2_Cpu.h"

using namespace std;

N2_ResetGen::N2_ResetGen( N2_Model* _model, SS_AddressMap* map, SS_Paddr lo, SS_Paddr hi )/*{{{*/
 :
  model(_model)
{
  // N2 RESET_GEN, 0x89_0000_0808, 8-byte
  if ((lo != 0x8900000808) || (hi != 0x8900000808+7))
  {
    cerr << "ERROR: N2_ResetGen (0x89_0000_0808) being given wrong range, lo=0x" << hex << lo << " hi=0x" << hi << endl;
    return;
  }
  map->add(lo,hi,this,SS_AddressMap::REL,N2_ResetGen::access);
}
/*}}}*/
N2_ResetGen::~N2_ResetGen()/*{{{*/
{
}
/*}}}*/

void N2_ResetGen::access( void* obj, uint_t sid, SS_Access::Type type, SS_Paddr pa, uint_t size, uint64_t* data )/*{{{*/
{
  N2_ResetGen* self = (N2_ResetGen*)obj;

  switch (type)
  {
    case SS_Access::LOAD:
      // reset_gen is always reset to 0 after the corresponding reset action
      // is completed
      *data = 0; 
      break;
    case SS_Access::STORE:
      // reset_gen[3] : dbr_gen
      // reset_gen[1] : xir_gen
      // reset_gen[0] : wmr_gen
      // behavior is undefined if more than one bit is written 1
      if (*data & 0x1)
      {
        // wmr_gen, chipwide wmr
        self->model->warm_reset();
      }
      else if (*data & 0x2)
      {
        // xir_gen, xir strands in ASI_XIR_STEERING
	self->model->xtrn_reset();
      }
      else if (*data & 0x8)
      {
        // dbr_gen, chipwide dbr
	self->model->warm_reset();
      }
      break;
    default: 
      assert(0);
  }
}
/*}}}*/