[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / cpu / bin / N2_State.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: N2_State.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

import sys

from SS_State import *
from SS_Setup import *

setup = setups[sys.argv[1]]


n2_asi_regs=[

  SS_AsiCtrReg('N2','lsu_ctr',PRIVATE,
  [
    ('ic'		, 0, 0,RW,0),
    ('dc'		, 1, 1,RW,0),
    ('im'		, 2, 2,RW,0),
    ('dm'		, 3, 3,RW,0),
    ('se'		, 4, 4,RW,0),
    ('we'		,23,23,RW,0),
    ('re'		,24,24,RW,0),
    ('bm'		,25,32,RW,0),
    ('mode'		,33,34,RW,0)
  ])
, SS_AsiCtrReg('N2','partition_id',PRIVATE,
  [
    (''			, 0, 2,RW,0)
  ])
, SS_AsiCtrReg('N2','context',PRIVATE,
  [	
    (''			, 0,12,RW,0)
  ])
, SS_AsiCtrReg('N2','physical_offset',PRIVATE,
  [
    ('ptv'		,13,39,RW,0)
  ])
, SS_AsiCtrReg('N2','real_range',PRIVATE,
  [
    ('rpn_low'		, 0,26,RW,0),
    ('rpn_high'		,27,53,RW,0),
    ('enable'		,63,63,RW,0)
  ])
, SS_AsiCtrReg('N2','tsb_config',PRIVATE,
  [
    ('tsb_size'     	, 0, 3,RW,0),
    ('page_size'    	, 4, 7,RW,0),
    ('ra_not_pa'    	, 8, 8,RW,0),
    ('tsb_base'     	,13,39,RW,0),
    ('use_context'  	,61,62,RW,0),
    ('valid'        	,63,63,RW,0)
  ])
, SS_AsiCtrReg('N2','tsb_pointer',PRIVATE,
  [
    ('pa'		, 0,39,RW,0)
  ])
, SS_AsiCtrReg('N2','inst_sfsr',PRIVATE,
  [
    ('error_type'	, 0, 2,RW,0)
  ],
  [
  	'// N2 PRM Rev 1.1 Tbl 12-7\n'
	'// ISFSR Error Codes\n'

	'// Instruction Access MMU Errors\n'
	'static const ITTM	= 1;\n'
	'static const ITTP	= 2;\n'
	'static const ITDP	= 3;\n'
	'static const ITMU	= 4;\n'
	'static const ITL2U	= 5;\n'
	'static const ITL2ND	= 6;\n'

	'// Instruction Access Errors\n'
	'static const ICL2U	= 1;\n'
	'static const ICL2ND	= 2;\n'
  ])
, SS_AsiCtrReg('N2','data_sfsr',PRIVATE,
  [
    ('error_type'	, 0, 3,RW,0)
  ],
  [
    	'// N2 PRM Rev 1.1 Tbl 12-8\n'
	'    // DSFSR Error Codes\n'

	'   // Internal Processor Error\n'
	'   static const IRFU	= 1;\n'
	'   static const IRFC	= 2;\n'
	'   static const FRFU	= 3;\n'
	'   static const FRFC	= 4;\n'
	'   static const SBDLC	= 5;\n'
	'   static const SBDLU	= 6;\n'
	'   static const MRAU	= 7;\n'
	'   static const TSAC	= 8;\n'
	'   static const TSAU	= 9;\n'
	'   static const SCAC	= 10;\n'
	'   static const SCAU	= 11;\n'
	'   static const TCCP	= 12;\n'
	'   static const TCUP	= 13;\n'

	'   // Data Access MMU Error\n'
	'   static const DTTM	= 1;\n'
	'   static const DTTP	= 2;\n'
	'   static const DTDP	= 3;\n'
	'   static const DTMU	= 4;\n'
	'   static const DTL2U	= 5;\n'
	'   static const DTL2ND	= 6;\n'

	'   // Data Access Error\n'
	'   static const DCL2U	= 1;\n'
	'   static const DCL2ND	= 2;\n'
	'   static const SOCU	= 4;\n'
 
  ])
, SS_AsiCtrReg('N2','data_sfar',PRIVATE,
  [
    ('error_addr'	, 0,47,RW,0)
  ])
, SS_AsiCtrReg('N2','demap',PRIVATE,
  [
    ('context'      	, 4, 5,RW,0),
    ('type'		, 6, 7,RW,0),
    ('real'		,10,10,RW,0),
    ('va'		,13,63,RW,0)
  ])
, SS_AsiCtrReg('N2','tag_target',PRIVATE,
  [
    ('va'		, 0,41,RO,0),
    ('context'      	,48,60,RO,0)
  ])
, SS_AsiCtrReg('N2','tag_access',PRIVATE,
  [
    ('context'		, 0,12,RW,0),
    ('va' 	     	,13,63,RW,0) # 48-63 are signext of 47
  ])
, SS_AsiCtrReg('N2','hwtw_config',PRIVATE,
  [ 
    ('burst'		, 0, 0,RW,0),
    ('predict'		, 1, 1,RW,0)
  ])
, SS_AsiCtrReg('N2','tw_control',PRIVATE,
  [
    ('stp'		, 0, 0,RW,0)
  ])
, SS_AsiCtrReg('N2','tw_status', SHARED,
  [ 
    ('stp'		, 0, 7,RO,0),					
    ('htp'		,32,39,RO,0)
  ])
, SS_AsiCtrReg('N2','inst_wp',SHARED,
  [
    ('enabled'		, 0, 0,RW,0),
    ('va'		, 2,47,RW,0)
  ])
, SS_AsiCtrReg('N2','data_wp',PRIVATE,
  [
    ('va'		, 3,47,RW,0),
    ('pa'		, 3,39,RW,0),
    ('va_high'		,48,63,RW,0)
  ])
, SS_AsiCtrReg('N2','strand_available',SHARED,
  [
    (''			, 0,63,RW,0)
  ])
, SS_AsiCtrReg('N2','strand_enable',SHARED,
  [	
    (''			, 0,63,RW,0)
  ])
, SS_AsiCtrReg('N2','strand_enable_status',SHARED,
  [
    (''			, 0,63,RO,0)
  ])
, SS_AsiCtrReg('N2','strand_running',SHARED,
  [
    (''			, 0,63,RW,0)
  ])
, SS_AsiCtrReg('N2','strand_running_status',SHARED,
  [
    (''			, 0,63,RO,0)
  ])
, SS_AsiCtrReg('N2','xir_steering',SHARED,
  [
    (''			, 0,63,RW,0)
  ])
, SS_AsiCtrReg('N2','tick_enable',SHARED,
  [
    (''			, 0, 1,RW,0)
  ])
, SS_AsiCtrReg('N2','core_intr_id',PRIVATE,
  [
    ('intr_id_lo'	, 0, 5,RO,0),
    ('intr_id_hi'	, 6,15,RO,0)
  ])
, SS_AsiCtrReg('N2','core_id',PRIVATE,
  [
    ('core_id'		, 0, 5,RO,0),
    ('max_core_id'	,16,21,RO,0x3f),
    ('max_strand_id'	,32,37,RO,7)
  ])
, SS_AsiCtrReg('N2','power_mgmt',SHARED,
  [
    (''			, 0,15,RW,0)
  ])
, SS_AsiCtrReg('N2','cerer',SHARED,
  [
    ('cwql2nd'		, 0,0,RW,0),
    ('cwql2u'		, 1,1,RW,0),
    ('cwql2c'		, 2,2,RW,0),
    ('mal2nd'		, 3,3,RW,0),
    ('mal2u'		, 4,4,RW,0),
    ('mal2c'		, 5,5,RW,0),
    ('tcud'		, 6,6,RW,0),
    ('tccd'		, 7,7,RW,0),
    ('mamu'		, 8,8,RW,0),
    ('sbdpu_sbiou'	, 9,9,RW,0),
    ('sbdpc'    	, 10,10,RW,0),
    ('dcdp'             , 11,11,RW,0),
    ('dctm'     	, 12,12,RW,0),
    ('dctp'     	, 13,13,RW,0),
    ('dcvp'		, 14,14,RW,0),
    ('icdp'		, 15,15,RW,0),
    ('ictm'		, 16,16,RW,0),
    ('ictp'		, 17,17,RW,0),
    ('icvp'		, 18,18,RW,0),
    ('l2nd'		, 19,19,RW,0),
    ('l2u_socu'		, 20,20,RW,0),
    ('l2c_socc'		, 21,21,RW,0),
    ('rsvd0'		, 22,22,RO,0),
    ('sbapp'		, 23,23,RW,0),
    ('rsvd1'		, 24,26,RO,0),
    ('tcup'		, 27,27,RW,0),
    ('tccp'		, 28,28,RW,0),
    ('scau'		, 29,29,RW,0),
    ('scac'		, 30,30,RW,0),
    ('tsau'		, 31,31,RW,0),
    ('tsac'		, 32,32,RW,0),
    ('mrau'		, 33,33,RW,0),
    ('rsvd2'		, 34,35,RO,0),
    ('sbdlu'		, 36,36,RW,0),
    ('sbdlc'		, 37,37,RW,0),
    ('dcl2nd'		, 38,38,RW,0),
    ('dcl2u'		, 39,39,RW,0),
    ('dcl2c'		, 40,40,RW,0),
    ('rsvd3'		, 41,45,RO,0),
    ('dtdp'		, 46,46,RW,0),
    ('dttm'		, 47,47,RW,0),
    ('dttp'		, 48,48,RW,0),
    ('rsvd4'		, 49,49,RO,0),
    ('frf'		, 50,50,RW,0),
    ('rsvd5'		, 51,51,RO,0),
    ('irf'		, 52,52,RW,0),
    ('icl2nd'		, 53,53,RW,0),
    ('icl2u'		, 54,54,RW,0),
    ('icl2c'		, 55,55,RW,0),
    ('rsvd6'		, 56,57,RO,0),
    ('hwtwl2'		, 58,58,RW,0),
    ('hwtwmu'		, 59,59,RW,0),
    ('rsvd7'		, 60,60,RO,0),
    ('ittm'		, 61,61,RW,0),
    ('itdp'		, 62,62,RW,0),
    ('ittp'		, 63,63,RW,0),
  ])
, SS_AsiCtrReg('N2','seter',PRIVATE,
  [
    ('rsvd0'		, 0,59,RO,0),
    ('dhcce'		, 60,60,RW,0),
    ('de'		, 61,61,RW,0),
    ('pscce'		, 62,62,RW,0),
    ('rsvd1'		,63,63,RO,0)
  ])
, SS_AsiCtrReg('N2','desr',PRIVATE,
  [
    ('erraddr'		, 0,10,RO,0),
    ('errtype'		,56,60,RO,0),
    ('s'		,61,61,RO,0),
    ('me'		,62,62,RO,0),
    ('f'		,63,63,RO,0)
  ],
  [
  	'// N2 PRM Rev 1.1 Tbl 12-13\n'
	'    // DESR Correctable Error Codes\n'
	'    static const CE_ICVP	= 1;\n'
	'    static const CE_ICTP	= 2;\n'
	'    static const CE_ICTM	= 3;\n'
	'    static const CE_ICDP	= 4;\n'
	'    static const CE_DCVP	= 5;\n'
	'    static const CE_DCTP	= 6;\n'
	'    static const CE_DCTM	= 7;\n'
	'    static const CE_DCDP	= 8;\n'
	'    static const CE_L2C 	= 9;\n'
	'    static const CE_SBDPC	= 10;\n'
	'    static const CE_SOCC	= 11;\n'

	'    // DESR Recoverable Error Codes\n'
	'    static const RE_SBDPU	= 6;\n'
	'    static const RE_TCCD	= 14;\n'
	'    static const RE_TCUD	= 15;\n'
	'    static const RE_MAMU	= 7;\n'
	'    static const RE_MAL2C	= 8;\n'
	'    static const RE_MAL2U	= 9;\n'
	'    static const RE_MAL2ND	= 10;\n'
	'    static const RE_CWQL2C	= 11;\n'
	'    static const RE_CWQL2U	= 12;\n'
	'    static const RE_CWQL2ND	= 13;\n'
	'    static const RE_L2C	= 20;\n'
	'    static const RE_L2U	= 16;\n'
	'    static const RE_L2NC	= 17;\n'
	'    static const RE_ITL2C	= 1;\n'
	'    static const RE_ICL2C	= 2;\n'
	'    static const RE_DTL2C	= 3;\n'
	'    static const RE_DCL2C	= 4;\n'
	'    static const RE_SOCU	= 19;\n'
])
, SS_AsiCtrReg('N2','dfesr',SHARED,
  [
    ('stbindex'		,55,57,RW,0),
    ('priv'		,58,59,RW,0),
    ('type'		,60,61,RW,0)
  ],
  [
    'const static uint_t USER_PRIV = 0;\n'
    '   const static uint_t PRIV_PRIV = 1;\n'
    '   const static uint_t HPRIV_PRIV = 2;\n'
    '   const static uint_t UNKNOWN_PRIV = 3;\n'
  ])
, SS_AsiCtrReg('N2','clesr',SHARED,
  [
    ('t0'		,48,49,RW,0),
    ('t1'		,50,51,RW,0),
    ('t2'		,52,53,RW,0),
    ('t3'		,54,55,RW,0),
    ('t4'		,56,57,RW,0),
    ('t5'		,58,59,RW,0),
    ('t6'		,60,61,RW,0),
    ('t7'		,62,63,RW,0)
  ])
, SS_AsiCtrReg('N2','error_inject',SHARED,
  [
    ('eccmask'		, 0, 7,RW,0),
    ('stdu'		,17,17,RW,0),
    ('stau'		,19,19,RW,0),
    ('mrau'		,20,20,RW,0),
    ('tsau'		,21,21,RW,0),
    ('tccu'		,22,22,RW,0),
    ('scau'		,23,23,RW,0),
    ('frcu'		,24,24,RW,0),
    ('ircu'		,25,25,RW,0),
    ('dmtu'		,26,26,RW,0),
    ('dmdu'		,27,27,RW,0),
    ('imtu'		,28,28,RW,0),
    ('imdu'		,29,29,RW,0),
    ('ene'		,31,31,RW,0)
  ])
, SS_AsiCtrReg('N2','inst_mask',SHARED,
  [
    ('iw'		, 0,31,RW,0),
    ('en_rs2'		,32,32,RW,0),
    ('en_asi'		,33,33,RW,0),
    ('en_i'		,34,34,RW,0),
    ('en_rs1'		,35,35,RW,0),
    ('en_op3'		,36,36,RW,0),
    ('en_rd'		,37,37,RW,0),
    ('en_op'		,38,38,RW,0)
  ])
, SS_AsiCtrReg('N2','lsu_diag',SHARED,
  [
    ('iassocdis'	, 0, 0,RW,0),
    ('dassocdis'	, 1, 1,RW,0)
  ])
, SS_AsiCtrReg('N2','decr',SHARED,
  [
    ('df_de'		,48,49,RW,0),
    ('de_de'		,50,51,RW,0),
    ('pe_de'		,52,53,RW,0),
    ('tct_de'		,54,55,RW,0),
    ('dpa_de'		,56,57,RW,0),
    ('dva_de'		,58,59,RW,0),
    ('iva_de'		,60,61,RW,0),
    ('iwa_de'		,62,63,RW,0)
  ])
, SS_AsiCtrReg('N2','overlap_mode',SHARED,
  [
    ('ovlp_0'		, 0, 1,RW,0),
    ('ovlp_1'		, 2, 3,RW,0),
    ('ovlp_2'		, 4, 5,RW,0),
    ('ovlp_3'		, 6, 7,RW,0),
    ('ovlp_4'		, 8, 9,RW,0),
    ('ovlp_5'		,10,11,RW,0),
    ('ovlp_6'		,12,13,RW,0),
    ('ovlp_7'		,14,15,RW,0)
  ])
, SS_AsiCtrReg('N2','rst_vec_mask',SHARED,
  [
    ('vec_mask'		, 0, 0,RW,0)
  ])
, SS_AsiCtrReg('N2','intr_r',PRIVATE,
  [
    ('vector'     	, 0, 5,RW,0)
  ])
, SS_AsiCtrReg('N2','intr_w',SHARED,
  [
    ('vector'     	, 0, 5,RW,0),	
    ('strand'		, 8,13,RW,0)
  ]) 
, SS_AsiCtrReg('N2','intr_queue_ptr',PRIVATE,
  [
    ('offset'		, 6,17,RW,0)
  ])
, SS_AsiCtrReg('N2','tick_access',PRIVATE,
  [
    ('index'     	, 3, 4,RW,0),	
    ('data_np'		, 5, 5,RW,0)
  ], 
  [
        'enum TickAccessIndex\n'
        '    {\n'
        '      TICK_CMPR_INDX     = 0,\n'
        '      STICK_CMPR_INDX    = 1,\n'
        '      HSTICK_CMPR_INDX   = 2,\n'
        '      TICK_ACCESS_MAX    = 3\n'
        '    };\n'
  ])
, SS_CtrReg('N2','pcr','asr',16,RWRWRW,64,
  [
    ('priv'		, 0, 0,RW,0),
    ('st'		, 1, 1,RW,0),
    ('ut'		, 2, 2,RW,0),
    ('ht'		, 3, 3,RW,0), # RO in user & priv
    ('toe'		, 4, 5,RW,0),
    ('mask0'		, 6,13,RW,0),
    ('sl0'		,14,17,RW,0),
    ('ov0'		,18,18,RW,0),
    ('mask1'		,19,26,RW,0),
    ('sl1'		,27,30,RW,0),
    ('ov1'		,31,31,RW,0),
    ('ov0wr' 		,62,62,RW,0),
    ('ov1wr' 		,63,63,RW,0)
  ])
, SS_CtrReg('N2','pic','asr',17,RWRWRW,64,
  [
    ('l'		, 0,31,RW,0),
    ('h'		,32,63,RW,0)
  ])
, SS_CtrReg('N2','tstate', 'prf', 2,RWRW__,64,
  [
    ('cwp'   		, 0, 2, RW, 0),
    ('pstate'		, 8,20, RO, 0),
    (''      		, 9, 9, RW, X),	# ie
    (''      		,10,10, RW, X),	# priv
    (''      		,11,11, RW, X),	# am
    (''      		,12,12, RW, X),	# pef
    (''      		,16,16, RW, X),	# tle
    (''      		,17,17, RW, X),	# cle
    (''      		,20,20, RW, X),	# tct
    ('asi'   		,24,31, RW, 0),
    ('ccr'   		,32,39, RW, 0),
    ('gl'    		,40,41, RW, 0) 	# one bit less the SS
  ])	
, SS_CtrReg('N2','tlb_data',0,0,0,64,
  [
    ('size'		, 0, 3,RW,0),
    ('w'   		, 6, 6,RW,0),
    ('p'   		, 8, 8,RW,0),
    ('cp'  		,10,10,RW,0),
    ('e'  		,11,11,RW,0),
    ('ie'  		,12,12,RW,0),
    ('pa'  		,13,39,RW,0),
    ('parity'		,61,61,RW,0),
    ('nfo' 		,62,62,RW,0),
    ('v'   		,63,63,RW,0)
  ])
, SS_CtrReg('N2','tag_read',0,0,0,64,
  [
    ('context'     	, 0,12,RW,0),	
    ('va_ra'		,13,47,RW,0), 
    ('used'		,58,58,RW,0), 
    ('parity'		,59,59,RW,0), 
    ('real'		,60,60,RW,0), 
    ('pid'		,61,63,RW,0)
  ]) 
, SS_CtrReg('N2','itlb_probe_addr',0,0,0,64,
  [
    ('real'		, 4, 4,RW,0),
    ('va'		, 5,39,RW,0)
  ])
, SS_CtrReg('N2','itlb_probe_data',0,0,0,64,
  [
    ('pa'		,13,39,RW,0),
    ('dp'		,60,60,RW,0),
    ('tp'		,61,61,RW,0),
    ('mh'		,62,62,RW,0),
    ('v'		,63,63,RW,0)
  ])
, SS_CtrReg('N2','tlb_index',0,0,0,64,
  [
    ('index'		, 3, 9,RW,0),
    ('flag'		,10,10,RW,0)
  ])
, SS_CtrReg('N2','tsb_tte_tag',0,0,0,64,
  [
    ('va'     		, 0,41,RW,0),	
    ('reserved0'	,42,47,RW,0),
    ('context'		,48,60,RW,0),
    ('reserved1'	,61,63,RW,0)
  ]) 
, SS_CtrReg('N2','tsb_tte_data',0,0,0,64,
  [
    ('size'		, 0, 3,RW,0),
    ('sw0' 		, 4, 5,RW,0),
    ('w'   		, 6, 6,RW,0),
    ('x'   		, 7, 7,RW,0),
    ('p'   		, 8, 8,RW,0),
    ('cv'  		, 9, 9,RW,0),
    ('cp'  		,10,10,RW,0),
    ('e'   		,11,11,RW,0),
    ('ie'  		,12,12,RW,0),
    ('pa'  		,13,55,RW,0),
    ('pa_zero_ext'	,40,55,RW,0),
    ('sw1' 		,56,61,RW,0),
    ('nfo' 		,62,62,RW,0),
    ('v'   		,63,63,RW,0)
  ])
, SS_CtrReg('N2','scratchpad_access',0,0,0,64,
  [
    ('index'     	, 3, 5,RW,0),	
    ('data_np'		, 6, 6,RW,0)
  ]) 
, SS_CtrReg('N2','gl'        , 'prf',16,RWRW__, 8,
  [
    ('', 0, 3, RW, 0)
  ])
]

h_file=open('%s' % sys.argv[2],'w')

h_base_name = sys.argv[2].split('/')[-1].split('.')[0]

h_file.write('#ifndef __'+h_base_name+'_h__\n')
h_file.write('#define __'+h_base_name+'_h__\n')
h_file.write('\n')
h_file.write('#include "SS_AsiCtrReg.h"\n')
h_file.write('\n')

for reg in n2_asi_regs:
  reg.cpp(h_file)

h_file.write('\n')
h_file.write('#endif\n')
h_file.write('\n')

h_file.close()
Commit	Line	Data
920dae64 AT	1	# ========== Copyright Header Begin ==========================================
	2	#
	3	# OpenSPARC T2 Processor File: N2_State.py
	4	# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	5	# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	6	#
	7	# The above named program is free software; you can redistribute it and/or
	8	# modify it under the terms of the GNU General Public
	9	# License version 2 as published by the Free Software Foundation.
	10	#
	11	# The above named program is distributed in the hope that it will be
	12	# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	# General Public License for more details.
	15	#
	16	# You should have received a copy of the GNU General Public
	17	# License along with this work; if not, write to the Free Software
	18	# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	19	#
	20	# ========== Copyright Header End ============================================
	21
	22	import sys
	23
	24	from SS_State import *
	25	from SS_Setup import *
	26
	27	setup = setups[sys.argv[1]]
	28
	29
	30	n2_asi_regs=[
	31
	32	SS_AsiCtrReg('N2','lsu_ctr',PRIVATE,
	33	[
	34	('ic' , 0, 0,RW,0),
	35	('dc' , 1, 1,RW,0),
	36	('im' , 2, 2,RW,0),
	37	('dm' , 3, 3,RW,0),
	38	('se' , 4, 4,RW,0),
	39	('we' ,23,23,RW,0),
	40	('re' ,24,24,RW,0),
	41	('bm' ,25,32,RW,0),
	42	('mode' ,33,34,RW,0)
	43	])
	44	, SS_AsiCtrReg('N2','partition_id',PRIVATE,
	45	[
	46	('' , 0, 2,RW,0)
	47	])
	48	, SS_AsiCtrReg('N2','context',PRIVATE,
	49	[
	50	('' , 0,12,RW,0)
	51	])
	52	, SS_AsiCtrReg('N2','physical_offset',PRIVATE,
	53	[
	54	('ptv' ,13,39,RW,0)
	55	])
	56	, SS_AsiCtrReg('N2','real_range',PRIVATE,
	57	[
	58	('rpn_low' , 0,26,RW,0),
	59	('rpn_high' ,27,53,RW,0),
	60	('enable' ,63,63,RW,0)
	61	])
	62	, SS_AsiCtrReg('N2','tsb_config',PRIVATE,
	63	[
	64	('tsb_size' , 0, 3,RW,0),
65	('page_size' , 4, 7,RW,0),
66	('ra_not_pa' , 8, 8,RW,0),
67	('tsb_base' ,13,39,RW,0),
68	('use_context' ,61,62,RW,0),
69	('valid' ,63,63,RW,0)
70	])
71	, SS_AsiCtrReg('N2','tsb_pointer',PRIVATE,
72	[
73	('pa' , 0,39,RW,0)
74	])
75	, SS_AsiCtrReg('N2','inst_sfsr',PRIVATE,
76	[
77	('error_type' , 0, 2,RW,0)
78	],
79	[
80	'// N2 PRM Rev 1.1 Tbl 12-7\n'
81	'// ISFSR Error Codes\n'
82
83	'// Instruction Access MMU Errors\n'
84	'static const ITTM = 1;\n'
85	'static const ITTP = 2;\n'
86	'static const ITDP = 3;\n'
87	'static const ITMU = 4;\n'
88	'static const ITL2U = 5;\n'
89	'static const ITL2ND = 6;\n'
90
91	'// Instruction Access Errors\n'
92	'static const ICL2U = 1;\n'
93	'static const ICL2ND = 2;\n'
94	])
95	, SS_AsiCtrReg('N2','data_sfsr',PRIVATE,
96	[
97	('error_type' , 0, 3,RW,0)
98	],
99	[
100	'// N2 PRM Rev 1.1 Tbl 12-8\n'
101	' // DSFSR Error Codes\n'
102
103	' // Internal Processor Error\n'
104	' static const IRFU = 1;\n'
105	' static const IRFC = 2;\n'
106	' static const FRFU = 3;\n'
107	' static const FRFC = 4;\n'
108	' static const SBDLC = 5;\n'
109	' static const SBDLU = 6;\n'
110	' static const MRAU = 7;\n'
111	' static const TSAC = 8;\n'
112	' static const TSAU = 9;\n'
113	' static const SCAC = 10;\n'
114	' static const SCAU = 11;\n'
115	' static const TCCP = 12;\n'
116	' static const TCUP = 13;\n'
117
118	' // Data Access MMU Error\n'
119	' static const DTTM = 1;\n'
120	' static const DTTP = 2;\n'
121	' static const DTDP = 3;\n'
122	' static const DTMU = 4;\n'
123	' static const DTL2U = 5;\n'
124	' static const DTL2ND = 6;\n'
125
126	' // Data Access Error\n'
127	' static const DCL2U = 1;\n'
128	' static const DCL2ND = 2;\n'
129	' static const SOCU = 4;\n'
130
131	])
132	, SS_AsiCtrReg('N2','data_sfar',PRIVATE,
133	[
134	('error_addr' , 0,47,RW,0)
135	])
136	, SS_AsiCtrReg('N2','demap',PRIVATE,
137	[
138	('context' , 4, 5,RW,0),
139	('type' , 6, 7,RW,0),
140	('real' ,10,10,RW,0),
141	('va' ,13,63,RW,0)
142	])
143	, SS_AsiCtrReg('N2','tag_target',PRIVATE,
144	[
145	('va' , 0,41,RO,0),
146	('context' ,48,60,RO,0)
147	])
148	, SS_AsiCtrReg('N2','tag_access',PRIVATE,
149	[
150	('context' , 0,12,RW,0),
151	('va' ,13,63,RW,0) # 48-63 are signext of 47
152	])
153	, SS_AsiCtrReg('N2','hwtw_config',PRIVATE,
154	[
155	('burst' , 0, 0,RW,0),
156	('predict' , 1, 1,RW,0)
157	])
158	, SS_AsiCtrReg('N2','tw_control',PRIVATE,
159	[
160	('stp' , 0, 0,RW,0)
161	])
162	, SS_AsiCtrReg('N2','tw_status', SHARED,
163	[
164	('stp' , 0, 7,RO,0),
165	('htp' ,32,39,RO,0)
166	])
167	, SS_AsiCtrReg('N2','inst_wp',SHARED,
168	[
169	('enabled' , 0, 0,RW,0),
170	('va' , 2,47,RW,0)
171	])
172	, SS_AsiCtrReg('N2','data_wp',PRIVATE,
173	[
174	('va' , 3,47,RW,0),
175	('pa' , 3,39,RW,0),
176	('va_high' ,48,63,RW,0)
177	])
178	, SS_AsiCtrReg('N2','strand_available',SHARED,
179	[
180	('' , 0,63,RW,0)
181	])
182	, SS_AsiCtrReg('N2','strand_enable',SHARED,
183	[
184	('' , 0,63,RW,0)
185	])
186	, SS_AsiCtrReg('N2','strand_enable_status',SHARED,
187	[
188	('' , 0,63,RO,0)
189	])
190	, SS_AsiCtrReg('N2','strand_running',SHARED,
191	[
192	('' , 0,63,RW,0)
193	])
194	, SS_AsiCtrReg('N2','strand_running_status',SHARED,
195	[
196	('' , 0,63,RO,0)
197	])
198	, SS_AsiCtrReg('N2','xir_steering',SHARED,
199	[
200	('' , 0,63,RW,0)
201	])
202	, SS_AsiCtrReg('N2','tick_enable',SHARED,
203	[
204	('' , 0, 1,RW,0)
205	])
206	, SS_AsiCtrReg('N2','core_intr_id',PRIVATE,
207	[
208	('intr_id_lo' , 0, 5,RO,0),
209	('intr_id_hi' , 6,15,RO,0)
210	])
211	, SS_AsiCtrReg('N2','core_id',PRIVATE,
212	[
213	('core_id' , 0, 5,RO,0),
214	('max_core_id' ,16,21,RO,0x3f),
215	('max_strand_id' ,32,37,RO,7)
216	])
217	, SS_AsiCtrReg('N2','power_mgmt',SHARED,
218	[
219	('' , 0,15,RW,0)
220	])
221	, SS_AsiCtrReg('N2','cerer',SHARED,
222	[
223	('cwql2nd' , 0,0,RW,0),
224	('cwql2u' , 1,1,RW,0),
225	('cwql2c' , 2,2,RW,0),
226	('mal2nd' , 3,3,RW,0),
227	('mal2u' , 4,4,RW,0),
228	('mal2c' , 5,5,RW,0),
229	('tcud' , 6,6,RW,0),
230	('tccd' , 7,7,RW,0),
231	('mamu' , 8,8,RW,0),
232	('sbdpu_sbiou' , 9,9,RW,0),
233	('sbdpc' , 10,10,RW,0),
234	('dcdp' , 11,11,RW,0),
235	('dctm' , 12,12,RW,0),
236	('dctp' , 13,13,RW,0),
237	('dcvp' , 14,14,RW,0),
238	('icdp' , 15,15,RW,0),
239	('ictm' , 16,16,RW,0),
240	('ictp' , 17,17,RW,0),
241	('icvp' , 18,18,RW,0),
242	('l2nd' , 19,19,RW,0),
243	('l2u_socu' , 20,20,RW,0),
244	('l2c_socc' , 21,21,RW,0),
245	('rsvd0' , 22,22,RO,0),
246	('sbapp' , 23,23,RW,0),
247	('rsvd1' , 24,26,RO,0),
248	('tcup' , 27,27,RW,0),
249	('tccp' , 28,28,RW,0),
250	('scau' , 29,29,RW,0),
251	('scac' , 30,30,RW,0),
252	('tsau' , 31,31,RW,0),
253	('tsac' , 32,32,RW,0),
254	('mrau' , 33,33,RW,0),
255	('rsvd2' , 34,35,RO,0),
256	('sbdlu' , 36,36,RW,0),
257	('sbdlc' , 37,37,RW,0),
258	('dcl2nd' , 38,38,RW,0),
259	('dcl2u' , 39,39,RW,0),
260	('dcl2c' , 40,40,RW,0),
261	('rsvd3' , 41,45,RO,0),
262	('dtdp' , 46,46,RW,0),
263	('dttm' , 47,47,RW,0),
264	('dttp' , 48,48,RW,0),
265	('rsvd4' , 49,49,RO,0),
266	('frf' , 50,50,RW,0),
267	('rsvd5' , 51,51,RO,0),
268	('irf' , 52,52,RW,0),
269	('icl2nd' , 53,53,RW,0),
270	('icl2u' , 54,54,RW,0),
271	('icl2c' , 55,55,RW,0),
272	('rsvd6' , 56,57,RO,0),
273	('hwtwl2' , 58,58,RW,0),
274	('hwtwmu' , 59,59,RW,0),
275	('rsvd7' , 60,60,RO,0),
276	('ittm' , 61,61,RW,0),
277	('itdp' , 62,62,RW,0),
278	('ittp' , 63,63,RW,0),
279	])
280	, SS_AsiCtrReg('N2','seter',PRIVATE,
281	[
282	('rsvd0' , 0,59,RO,0),
283	('dhcce' , 60,60,RW,0),
284	('de' , 61,61,RW,0),
285	('pscce' , 62,62,RW,0),
286	('rsvd1' ,63,63,RO,0)
287	])
288	, SS_AsiCtrReg('N2','desr',PRIVATE,
289	[
290	('erraddr' , 0,10,RO,0),
291	('errtype' ,56,60,RO,0),
292	('s' ,61,61,RO,0),
293	('me' ,62,62,RO,0),
294	('f' ,63,63,RO,0)
295	],
296	[
297	'// N2 PRM Rev 1.1 Tbl 12-13\n'
298	' // DESR Correctable Error Codes\n'
299	' static const CE_ICVP = 1;\n'
300	' static const CE_ICTP = 2;\n'
301	' static const CE_ICTM = 3;\n'
302	' static const CE_ICDP = 4;\n'
303	' static const CE_DCVP = 5;\n'
304	' static const CE_DCTP = 6;\n'
305	' static const CE_DCTM = 7;\n'
306	' static const CE_DCDP = 8;\n'
307	' static const CE_L2C = 9;\n'
308	' static const CE_SBDPC = 10;\n'
309	' static const CE_SOCC = 11;\n'
310
311	' // DESR Recoverable Error Codes\n'
312	' static const RE_SBDPU = 6;\n'
313	' static const RE_TCCD = 14;\n'
314	' static const RE_TCUD = 15;\n'
315	' static const RE_MAMU = 7;\n'
316	' static const RE_MAL2C = 8;\n'
317	' static const RE_MAL2U = 9;\n'
318	' static const RE_MAL2ND = 10;\n'
319	' static const RE_CWQL2C = 11;\n'
320	' static const RE_CWQL2U = 12;\n'
321	' static const RE_CWQL2ND = 13;\n'
322	' static const RE_L2C = 20;\n'
323	' static const RE_L2U = 16;\n'
324	' static const RE_L2NC = 17;\n'
325	' static const RE_ITL2C = 1;\n'
326	' static const RE_ICL2C = 2;\n'
327	' static const RE_DTL2C = 3;\n'
328	' static const RE_DCL2C = 4;\n'
329	' static const RE_SOCU = 19;\n'
330	])
331	, SS_AsiCtrReg('N2','dfesr',SHARED,
332	[
333	('stbindex' ,55,57,RW,0),
334	('priv' ,58,59,RW,0),
335	('type' ,60,61,RW,0)
336	],
337	[
338	'const static uint_t USER_PRIV = 0;\n'
339	' const static uint_t PRIV_PRIV = 1;\n'
340	' const static uint_t HPRIV_PRIV = 2;\n'
341	' const static uint_t UNKNOWN_PRIV = 3;\n'
342	])
343	, SS_AsiCtrReg('N2','clesr',SHARED,
344	[
345	('t0' ,48,49,RW,0),
346	('t1' ,50,51,RW,0),
347	('t2' ,52,53,RW,0),
348	('t3' ,54,55,RW,0),
349	('t4' ,56,57,RW,0),
350	('t5' ,58,59,RW,0),
351	('t6' ,60,61,RW,0),
352	('t7' ,62,63,RW,0)
353	])
354	, SS_AsiCtrReg('N2','error_inject',SHARED,
355	[
356	('eccmask' , 0, 7,RW,0),
357	('stdu' ,17,17,RW,0),
358	('stau' ,19,19,RW,0),
359	('mrau' ,20,20,RW,0),
360	('tsau' ,21,21,RW,0),
361	('tccu' ,22,22,RW,0),
362	('scau' ,23,23,RW,0),
363	('frcu' ,24,24,RW,0),
364	('ircu' ,25,25,RW,0),
365	('dmtu' ,26,26,RW,0),
366	('dmdu' ,27,27,RW,0),
367	('imtu' ,28,28,RW,0),
368	('imdu' ,29,29,RW,0),
369	('ene' ,31,31,RW,0)
370	])
371	, SS_AsiCtrReg('N2','inst_mask',SHARED,
372	[
373	('iw' , 0,31,RW,0),
374	('en_rs2' ,32,32,RW,0),
375	('en_asi' ,33,33,RW,0),
376	('en_i' ,34,34,RW,0),
377	('en_rs1' ,35,35,RW,0),
378	('en_op3' ,36,36,RW,0),
379	('en_rd' ,37,37,RW,0),
380	('en_op' ,38,38,RW,0)
381	])
382	, SS_AsiCtrReg('N2','lsu_diag',SHARED,
383	[
384	('iassocdis' , 0, 0,RW,0),
385	('dassocdis' , 1, 1,RW,0)
386	])
387	, SS_AsiCtrReg('N2','decr',SHARED,
388	[
389	('df_de' ,48,49,RW,0),
390	('de_de' ,50,51,RW,0),
391	('pe_de' ,52,53,RW,0),
392	('tct_de' ,54,55,RW,0),
393	('dpa_de' ,56,57,RW,0),
394	('dva_de' ,58,59,RW,0),
395	('iva_de' ,60,61,RW,0),
396	('iwa_de' ,62,63,RW,0)
397	])
398	, SS_AsiCtrReg('N2','overlap_mode',SHARED,
399	[
400	('ovlp_0' , 0, 1,RW,0),
401	('ovlp_1' , 2, 3,RW,0),
402	('ovlp_2' , 4, 5,RW,0),
403	('ovlp_3' , 6, 7,RW,0),
404	('ovlp_4' , 8, 9,RW,0),
405	('ovlp_5' ,10,11,RW,0),
406	('ovlp_6' ,12,13,RW,0),
407	('ovlp_7' ,14,15,RW,0)
408	])
409	, SS_AsiCtrReg('N2','rst_vec_mask',SHARED,
410	[
411	('vec_mask' , 0, 0,RW,0)
412	])
413	, SS_AsiCtrReg('N2','intr_r',PRIVATE,
414	[
415	('vector' , 0, 5,RW,0)
416	])
417	, SS_AsiCtrReg('N2','intr_w',SHARED,
418	[
419	('vector' , 0, 5,RW,0),
420	('strand' , 8,13,RW,0)
421	])
422	, SS_AsiCtrReg('N2','intr_queue_ptr',PRIVATE,
423	[
424	('offset' , 6,17,RW,0)
425	])
426	, SS_AsiCtrReg('N2','tick_access',PRIVATE,
427	[
428	('index' , 3, 4,RW,0),
429	('data_np' , 5, 5,RW,0)
430	],
431	[
432	'enum TickAccessIndex\n'
433	' {\n'
434	' TICK_CMPR_INDX = 0,\n'
435	' STICK_CMPR_INDX = 1,\n'
436	' HSTICK_CMPR_INDX = 2,\n'
437	' TICK_ACCESS_MAX = 3\n'
438	' };\n'
439	])
440	, SS_CtrReg('N2','pcr','asr',16,RWRWRW,64,
441	[
442	('priv' , 0, 0,RW,0),
443	('st' , 1, 1,RW,0),
444	('ut' , 2, 2,RW,0),
445	('ht' , 3, 3,RW,0), # RO in user & priv
446	('toe' , 4, 5,RW,0),
447	('mask0' , 6,13,RW,0),
448	('sl0' ,14,17,RW,0),
449	('ov0' ,18,18,RW,0),
450	('mask1' ,19,26,RW,0),
451	('sl1' ,27,30,RW,0),
452	('ov1' ,31,31,RW,0),
453	('ov0wr' ,62,62,RW,0),
454	('ov1wr' ,63,63,RW,0)
455	])
456	, SS_CtrReg('N2','pic','asr',17,RWRWRW,64,
457	[
458	('l' , 0,31,RW,0),
459	('h' ,32,63,RW,0)
460	])
461	, SS_CtrReg('N2','tstate', 'prf', 2,RWRW__,64,
462	[
463	('cwp' , 0, 2, RW, 0),
464	('pstate' , 8,20, RO, 0),
465	('' , 9, 9, RW, X), # ie
466	('' ,10,10, RW, X), # priv
467	('' ,11,11, RW, X), # am
468	('' ,12,12, RW, X), # pef
469	('' ,16,16, RW, X), # tle
470	('' ,17,17, RW, X), # cle
471	('' ,20,20, RW, X), # tct
472	('asi' ,24,31, RW, 0),
473	('ccr' ,32,39, RW, 0),
474	('gl' ,40,41, RW, 0) # one bit less the SS
475	])
476	, SS_CtrReg('N2','tlb_data',0,0,0,64,
477	[
478	('size' , 0, 3,RW,0),
479	('w' , 6, 6,RW,0),
480	('p' , 8, 8,RW,0),
481	('cp' ,10,10,RW,0),
482	('e' ,11,11,RW,0),
483	('ie' ,12,12,RW,0),
484	('pa' ,13,39,RW,0),
485	('parity' ,61,61,RW,0),
486	('nfo' ,62,62,RW,0),
487	('v' ,63,63,RW,0)
488	])
489	, SS_CtrReg('N2','tag_read',0,0,0,64,
490	[
491	('context' , 0,12,RW,0),
492	('va_ra' ,13,47,RW,0),
493	('used' ,58,58,RW,0),
494	('parity' ,59,59,RW,0),
495	('real' ,60,60,RW,0),
496	('pid' ,61,63,RW,0)
497	])
498	, SS_CtrReg('N2','itlb_probe_addr',0,0,0,64,
499	[
500	('real' , 4, 4,RW,0),
501	('va' , 5,39,RW,0)
502	])
503	, SS_CtrReg('N2','itlb_probe_data',0,0,0,64,
504	[
505	('pa' ,13,39,RW,0),
506	('dp' ,60,60,RW,0),
507	('tp' ,61,61,RW,0),
508	('mh' ,62,62,RW,0),
509	('v' ,63,63,RW,0)
510	])
511	, SS_CtrReg('N2','tlb_index',0,0,0,64,
512	[
513	('index' , 3, 9,RW,0),
514	('flag' ,10,10,RW,0)
515	])
516	, SS_CtrReg('N2','tsb_tte_tag',0,0,0,64,
517	[
518	('va' , 0,41,RW,0),
519	('reserved0' ,42,47,RW,0),
520	('context' ,48,60,RW,0),
521	('reserved1' ,61,63,RW,0)
522	])
523	, SS_CtrReg('N2','tsb_tte_data',0,0,0,64,
524	[
525	('size' , 0, 3,RW,0),
526	('sw0' , 4, 5,RW,0),
527	('w' , 6, 6,RW,0),
528	('x' , 7, 7,RW,0),
529	('p' , 8, 8,RW,0),
530	('cv' , 9, 9,RW,0),
531	('cp' ,10,10,RW,0),
532	('e' ,11,11,RW,0),
533	('ie' ,12,12,RW,0),
534	('pa' ,13,55,RW,0),
535	('pa_zero_ext' ,40,55,RW,0),
536	('sw1' ,56,61,RW,0),
537	('nfo' ,62,62,RW,0),
538	('v' ,63,63,RW,0)
539	])
540	, SS_CtrReg('N2','scratchpad_access',0,0,0,64,
541	[
542	('index' , 3, 5,RW,0),
543	('data_np' , 6, 6,RW,0)
544	])
545	, SS_CtrReg('N2','gl' , 'prf',16,RWRW__, 8,
546	[
547	('', 0, 3, RW, 0)
548	])
549	]
550
551	h_file=open('%s' % sys.argv[2],'w')
552
553	h_base_name = sys.argv[2].split('/')[-1].split('.')[0]
554
555	h_file.write('#ifndef __'+h_base_name+'_h__\n')
556	h_file.write('#define __'+h_base_name+'_h__\n')
557	h_file.write('\n')
558	h_file.write('#include "SS_AsiCtrReg.h"\n')
559	h_file.write('\n')
560
561	for reg in n2_asi_regs:
562	reg.cpp(h_file)
563
564	h_file.write('\n')
565	h_file.write('#endif\n')
566	h_file.write('\n')
567
568	h_file.close()
569
570
571
572
573