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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / cpu / src / N2_Strand.h
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: N2_Strand.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23#ifndef __N2_Strand_h__
24#define __N2_Strand_h__
25
26#include "SS_Strand.h"
27#include "SS_Tsb.h"
28#include "N2_State.h"
29#include "N2_Fpu.h"
30#include "N2_StoreBuffer.h"
31
32class N2_Core;
33
34class N2_Strand : public SS_Strand
35{
36 public:
37 N2_Strand( N2_Core& core, const char* _name, uint_t sid );
38
39 static const char* n2_get_state_name( SS_Strand*, SS_Registers::Index index );
40
41 static SS_Registers::Error n2_get_state( SS_Strand*, SS_Registers::Index index, uint64_t* value );
42 static SS_Registers::Error n2_set_state( SS_Strand*, SS_Registers::Index index, uint64_t value );
43
44 void warm_reset(bool intp=true);
45
46 void snapshot( SS_SnapShot& ss );
47
48 N2_Core& core;
49
50 N2_Fpu fpu;
51 N2_Pcr pcr;
52 N2_Pic pic;
53 N2_CoreIntrId core_intr_id;
54 N2_CoreId core_id;
55 N2_Context primary_context[2];
56 N2_Context secondary_context[2];
57 N2_TagTarget inst_tag_target;
58 N2_TagAccess inst_tag_access;
59 N2_TagTarget data_tag_target;
60 N2_TagAccess data_tag_access;
61 N2_PartitionId partition_id;
62 N2_RealRange real_range[4];
63 N2_PhysicalOffset physical_offset[4];
64 N2_TsbConfig nucleus_tsb_config[4];
65 N2_TsbConfig non_nucleus_tsb_config[4];
66 N2_TsbPointer inst_tsb_pointer[4];
67 N2_TsbPointer data_tsb_pointer[4];
68 N2_HwtwConfig hwtw_config;
69 N2_TwControl tw_control;
70 N2_InstSfsr inst_sfsr;
71 N2_DataSfsr data_sfsr;
72 N2_DataSfar data_sfar;
73 N2_DataWp data_wp;
74 N2_IntrQueuePtr cpu_mondo_head;
75 N2_IntrQueuePtr cpu_mondo_tail;
76 N2_IntrQueuePtr dev_mondo_head;
77 N2_IntrQueuePtr dev_mondo_tail;
78 N2_IntrQueuePtr resumable_head;
79 N2_IntrQueuePtr resumable_tail;
80 N2_IntrQueuePtr non_resumable_head;
81 N2_IntrQueuePtr non_resumable_tail;
82 uint64_t intr_recv;
83 N2_IntrR intr_r;
84 N2_Seter seter;
85 N2_Desr desr;
86 uint64_t tw_status; // 1 when this strand is doing hwtw, 0 otherwise
87
88 BL_EccBits frf_ecc[64]; // Ecc values for FRF RAS
89 BL_EccBits sp_ecc[8]; // Ecc values for Scratchpad Registers
90 // Ecc values for Tick Compare Array 00-Tick Cmpr 01 - Stick Cmpr 10 - Hstick Cmpr
91 BL_EccBits tick_cmpr_array_ecc[N2_TickAccess::TICK_ACCESS_MAX];
92
93 void inst_tag_update( uint_t context, SS_Vaddr va );
94 void data_tag_update( uint_t context, SS_Vaddr va );
95
96 // Store Buffer RAS support
97 N2_StoreBuffer stb;
98 SS_Trap::Type fill_store_buffer_mem(const MemoryTransaction &memXact);
99 SS_Trap::Type fill_store_buffer_asi(uint64_t addr, uint8_t asi,uint64_t data);
100 SS_Trap::Type check_store_buffer_RAWtrap(const MemoryTransaction &memXact);
101 SS_Trap::Type flush_store_buffer();
102
103 protected:
104 static SS_AsiSpace::Error tsb_config_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
105 static SS_AsiSpace::Error tsb_ra2pa_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
106 static SS_AsiSpace::Error tag_access_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
107 static SS_AsiSpace::Error tlb_data_in_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
108 static SS_AsiSpace::Error tlb_data_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
109 static SS_AsiSpace::Error tlb_data_access_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
110 static SS_AsiSpace::Error tlb_tag_read_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
111 static SS_AsiSpace::Error inst_tlb_demap_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
112 static SS_AsiSpace::Error data_tlb_demap_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
113 static SS_AsiSpace::Error partition_id_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
114 static SS_AsiSpace::Error pri_ctx_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
115 static SS_AsiSpace::Error sec_ctx_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
116 static SS_AsiSpace::Error n2_lsu_ctr_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
117 static SS_AsiSpace::Error data_wp_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
118 static SS_AsiSpace::Error inst_tlb_probe_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
119 static SS_AsiSpace::Error intr_queue_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
120 static SS_AsiSpace::Error intr_queue_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
121 static SS_AsiSpace::Error intr_recv_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
122 static SS_AsiSpace::Error intr_recv_wr64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
123 static SS_AsiSpace::Error intr_recv_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
124 static SS_AsiSpace::Error intr_r_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
125 static SS_AsiSpace::Error desr_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
126 static SS_AsiSpace::Error stb_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
127 static SS_AsiSpace::Error irf_ecc_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
128 static SS_AsiSpace::Error frf_ecc_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
129 static SS_AsiSpace::Error tsa_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
130 static SS_AsiSpace::Error mra_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
131 static SS_AsiSpace::Error tick_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
132 static SS_AsiSpace::Error scratchpad_access_ld64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
133 static SS_AsiSpace::Error n2_scratchpad_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
134 static SS_AsiSpace::Error n2_scratchpad_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
135 static SS_AsiSpace::Error tw_control_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
136
137 static SS_Vaddr n2_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Trap::Type tt );
138 static SS_Vaddr n2_inst_mmu_va( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
139 static SS_Vaddr n2_inst_mmu_ra( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
140 static SS_Vaddr n2_inst_mmu_pa( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
141 static SS_Vaddr n2_data_mmu( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, uint_t mem );
142 static SS_Vaddr n2_inst_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, SS_Trap::Type tt );
143 static SS_Vaddr n2_data_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, SS_Trap::Type tt );
144 static SS_Vaddr n2_invalid_asi( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr );
145
146 static void n2_run_perf( SS_Strand* s, Sam::Vcpu::perfcntr which, int64_t incr );
147
148 static void n2_external_interrupt( SS_Strand*, uint64_t*, bool raise );
149 static void n2_internal_interrupt( SS_Strand*, uint_t vector, bool raise );
150
151 void intr_update();
152
153 SS_Tte* n2_inst_htw( SS_Vaddr va, SS_Context ctxt0, SS_Context ctxt1 );
154 SS_Tte* n2_data_htw( SS_Vaddr va, SS_Context ctxt0, SS_Context ctxt1 );
155
156 SS_TsbConfig tsb_config[8];
157 SS_TsbRaToPa tsb_ra2pa[4];
158 N2_TsbTteTag tsb_tte_tag;
159 N2_TsbTteData tsb_tte_data;
160 SS_Trap::Type trap_htw; // The trap htw caused if returned TTE == 0
161 SS_Trap::Type trap_dae_inv_asi; // When rd/wrasi causes a trap other then dae_inv_asi throw this.
162 int_t tlb_entry; // Pli command for HWTW and TLBWRITE forces TLB entry to be used
163
164 SS_Paddr data_wp_pa_mask;
165 SS_Paddr data_wp_pa_addr;
166 SS_Vaddr data_wp_va_mask;
167 SS_Vaddr data_wp_va_addr;
168 uint8_t data_wp_bytes; // Which bytes to check for match address
169 uint8_t data_wp_flags; // Read and/or write flags to check
170 uint8_t data_wp_check; // Set to non zero to disable TTE caching
171
172 bool va_watchpoint_hit( SS_Instr* i, SS_Vaddr va )
173 {
174 return ((va & data_wp_va_mask) == data_wp_va_addr) // Match address
175 && (((~uint64_t(0) >> (64 - i->len)) << (va & 7)) & data_wp_bytes) // Match byte mask
176 && (i->flg & data_wp_flags) // Match read or write
177 && (sim_state.priv() != SS_HPRV); // Only in user or priv mode
178 }
179
180 bool pa_watchpoint_hit( SS_Instr* i, SS_Paddr pa )
181 {
182 return ((pa & data_wp_pa_mask) == data_wp_pa_addr) // Match address
183 && (((~uint64_t(0) >> (64 - i->len)) << (pa & 7)) & data_wp_bytes) // Match byte mask
184 && (i->flg & data_wp_flags); // Match read or write
185 }
186
187 static Sam::Vcpu::TranslateError n2_cnv2pa( SS_Strand* s, Sam::Vcpu::TranslateMode, SS_Vaddr, uint64_t ctx, uint64_t pid, SS_Paddr* pa );
188
189 static SS_Execute v8_run_exe_table[];
190 static SS_Execute run_exe_table[];
191 static SS_Execute trc_exe_table[];
192
193 static SS_Memop mem_run_table[][4];
194 static SS_Memop mem_trc_table[][4];
195 static SS_Memop mem_ras_table[][4];
196
197 static SS_DecodeTable run_dec_xx_xxxxxx;
198
199 static void n2_ras_enable( SS_Strand*, char* );
200
201#ifdef COMPILE_FOR_COSIM
202 static SS_Trap::Type n2_inst_hwtw( SS_Strand* strand, SS_Vaddr va, int_t entry );
203 static SS_Trap::Type n2_data_hwtw( SS_Strand* strand, SS_Vaddr va, uint8_t asi, int_t entry );
204#endif
205};
206
207#endif
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.