Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / csr / src / N2_L2Csr.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: N2_L2Csr.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
/************************************************************************
**  
**  Copyright (C) 2004, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy.
**
*************************************************************************/
#include "N2_L2Csr.h"
#include "N2_Csr.h"

using namespace std;

#define N2_L2_L2_DIAG_DATA_A0 0xa000000000ULL
#define N2_L2_L2_DIAG_TAG_A4  0xa400000000ULL
#define N2_L2_L2_DIAG_VD_A6   0xa600400000ULL

#define Stringize( L ) #L

RegisterAttribute N2_L2Csr::attributeTable[] = {
    { N2_L2_L2_DIAG_DATA_A0,0xa0007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,Stringize(N2_L2_L2_DIAG_DATA_A0),"count 0x80000 step 8" }, 
    { 0xa100000000ULL,0xa1007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_A1","count 0x80000 step 8" },
    { 0xa200000000ULL,0xa2007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_A2","count 0x80000 step 8" },
    { 0xa300000000ULL,0xa3007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_A3","count 0x80000 step 8" },
    { 0xb000000000ULL,0xb0007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_B0","count 0x80000 step 8" },
    { 0xb100000000ULL,0xb1007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_B1","count 0x80000 step 8" },
    { 0xb200000000ULL,0xb2007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_B2","count 0x80000 step 8" },
    { 0xb300000000ULL,0xb3007ffff8ULL,0x8ULL,0x100000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_DATA_B3","count 0x80000 step 8" },
    { N2_L2_L2_DIAG_TAG_A4,0xa4003fffc0ULL,0x40ULL,0x10000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffc0000000ULL,0x0ULL,0x3fffffffULL,0x0ULL,0x0ULL,0x0ULL,Stringize(N2_L2_L2_DIAG_TAG_A4),"count 65536 step 64" },
    { 0xa500000000ULL,0xa5003fffc0ULL,0x40ULL,0x10000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffc0000000ULL,0x0ULL,0x3fffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_TAG_A5","count 0x10000 step 64" },
    { 0xb400000000ULL,0xb4003fffc0ULL,0x40ULL,0x10000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffc0000000ULL,0x0ULL,0x3fffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_TAG_B4","count 0x10000 step 64" },
    { 0xb500000000ULL,0xb5003fffc0ULL,0x40ULL,0x10000,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffc0000000ULL,0x0ULL,0x3fffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_TAG_B5","count 0x10000 step 64" },
    { N2_L2_L2_DIAG_VD_A6,0xa60043ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,Stringize(N2_L2_L2_DIAG_VD_A6),"count 4096 step 64" },
    { 0xa700400000ULL,0xa70043ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_VD_A7","count 4096 step 64" },
    { 0xb600400000ULL,0xb60043ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_VD_B6","count 4096 step 64" },
    { 0xb700400000ULL,0xb70043ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_VD_B7","count 4096 step 64" },
    { 0xa600000000ULL,0xa60003ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_UA_A6","count 4096 step 64" },
    { 0xa700000000ULL,0xa70003ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_UA_A7","count 4096 step 64" },
    { 0xb600000000ULL,0xb60003ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_UA_B6","count 4096 step 64" },
    { 0xb700000000ULL,0xb70003ffc0ULL,0x40ULL,4096,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff8000000000ULL,0x0ULL,0x7fffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_DIAG_UA_B7","count 4096 step 64" },
    { 0xa800000000ULL,0xa8000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RO,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_BIST_CONTROL_REG","" },
    { 0xb800000000ULL,0xb8000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RO,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_BIST_CONTROL_REG","" },
    { 0xa900000000ULL,0xa9000001c0ULL,0x40ULL,8,0x1ULL,0x1ULL,RegisterAttribute::RW,0xffffffffffe00000ULL,0x0ULL,0x1fffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_CONTROL_REG","" },
    { 0xb900000000ULL,0xb9000001c0ULL,0x40ULL,8,0x1ULL,0x1ULL,RegisterAttribute::RW,0xffffffffffe00000ULL,0x0ULL,0x1fffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_CONTROL_REG","" },
    { 0xaa00000000ULL,0xaa000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff8ULL,0x0ULL,0x7ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_EN_REG","" },
    { 0xba00000000ULL,0xba000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff8ULL,0x0ULL,0x7ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_EN_REG","" },
    { 0xab00000000ULL,0xab000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0x3f0000000ULL,0x0ULL,0xfffffffc0fffffffULL,0xc03ff7fc00000000ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_STATUS_REG","" },
    { 0xbb00000000ULL,0xbb000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0x3f0000000ULL,0x0ULL,0xfffffffc0fffffffULL,0xc03ff7fc00000000ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_STATUS_REG","" },
    { 0xac00000000ULL,0xac000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfULL,0x0ULL,0xfffffffffffffff0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_ADDRESS_REG","" },
    { 0xbc00000000ULL,0xbc000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfULL,0x0ULL,0xfffffffffffffff0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_ADDRESS_REG","" },
    { 0xad00000000ULL,0xad000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_INJECT_REG","" },
    { 0xbd00000000ULL,0xbd000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_L2_L2_ERROR_INJECT_REG","" },
    { 0xae00000000ULL,0xae000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfff0c0000000000fULL,0x0ULL,0xf3ffffffffff0ULL,0xb000000000000ULL,0x0ULL,0x0ULL,"N2_L2_L2_NOTDATA_ERROR_REG","" },
    { 0xbe00000000ULL,0xbe000001c0ULL,0x40ULL,8,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfff0c0000000000fULL,0x0ULL,0xf3ffffffffff0ULL,0xb000000000000ULL,0x0ULL,0x0ULL,"N2_L2_L2_NOTDATA_ERROR_REG","" }
};
const int N2_L2Csr::NUMBER_ENTRIES = sizeof(N2_L2Csr::attributeTable)/sizeof(N2_L2Csr::attributeTable[0]);

//=============================================================================
//=============================================================================
N2_L2Csr::N2_L2Csr( ) :
  SS_BaseCsr("N2_L2Csr", attributeTable, NUMBER_ENTRIES)
{
}

//=============================================================================
// register address range
//=============================================================================
void N2_L2Csr::regAddrSpace()
{ 
  const static std::string descr("N2_L2Csr address space");
  registerAddressSpace(attributeTable, NUMBER_ENTRIES, descr);
}


//======================================================================
//======================================================================
int
N2_L2Csr::read64( SS_Paddr paddr, uint64_t* data, int access, int sid )
{
  /* alias 0xBx xxxx xxxx to 0xAx xxxx xxxx */
  SS_Paddr aliased_paddr = paddr &((0xefULL << N2_Csr::IO_OFFSET) | ~(0x0ULL << (N2_Csr::IO_OFFSET - 1)));
  /*cerr << "Paddr: 0x" << std::hex << paddr << " aliased_paddr : 0x" << std::hex << aliased_paddr << endl;*/
  return SS_BaseCsr::read64(aliased_paddr, data, access, sid);
}

//======================================================================
//======================================================================
int
N2_L2Csr::write64( SS_Paddr paddr, uint64_t data, int access, int sid )
{
  /* alias 0xBx xxxx xxxx to 0xAx xxxx xxxx */
  SS_Paddr aliased_paddr = paddr &((0xefULL << N2_Csr::IO_OFFSET) | ~(0x0ULL << (N2_Csr::IO_OFFSET - 1)));
  /*cerr << " Write Paddr: 0x" << std::hex << paddr << " aliased_paddr : 0x" << std::hex << aliased_paddr << endl;*/
  return SS_BaseCsr::write64(aliased_paddr, data, access, sid);
}