Commit | Line | Data |
---|---|---|
920dae64 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: N2_NcuCsr.cc | |
4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
6 | // | |
7 | // The above named program is free software; you can redistribute it and/or | |
8 | // modify it under the terms of the GNU General Public | |
9 | // License version 2 as published by the Free Software Foundation. | |
10 | // | |
11 | // The above named program is distributed in the hope that it will be | |
12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | // General Public License for more details. | |
15 | // | |
16 | // You should have received a copy of the GNU General Public | |
17 | // License along with this work; if not, write to the Free Software | |
18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
19 | // | |
20 | // ========== Copyright Header End ============================================ | |
21 | /************************************************************************ | |
22 | ** | |
23 | ** Copyright (C) 2005, Sun Microsystems, Inc. | |
24 | ** | |
25 | ** Sun considers its source code as an unpublished, proprietary | |
26 | ** trade secret and it is available only under strict license provisions. | |
27 | ** This copyright notice is placed here only to protect Sun in the event | |
28 | ** the source is deemed a published work. Disassembly, decompilation, | |
29 | ** or other means of reducing the object code to human readable form | |
30 | ** is prohibited by the license agreement under which this code is | |
31 | ** provided to the user or company in possession of this copy. | |
32 | ** | |
33 | *************************************************************************/ | |
34 | #include "N2_NcuCsr.h" | |
35 | #include "N2_Strand.h" | |
36 | #include "N2_Csr.h" | |
37 | #include "N2_Model.h" | |
38 | ||
39 | using namespace std; | |
40 | ||
41 | const uint64_t N2_NcuCsr::NCU_ASI_COREAVAIL; | |
42 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_ENABLE_STATUS; | |
43 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_ENABLE; | |
44 | const uint64_t N2_NcuCsr::NCU_ASI_XIR_STEERING; | |
45 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_RUNNINGRW; | |
46 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_RUNNING_STATUS; | |
47 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_RUNNING_W1S; | |
48 | const uint64_t N2_NcuCsr::NCU_ASI_CORE_RUNNING_W1C; | |
49 | const uint64_t N2_NcuCsr::NCU_ASI_INTVECDISP; | |
50 | const uint64_t N2_NcuCsr::NCU_ASI_TICK_ENABLE; | |
51 | const uint64_t N2_NcuCsr::NCU_ASI_OVERLAP_MODE; | |
52 | const uint64_t N2_NcuCsr::NCU_ASI_WMR_VEC_MASK; | |
53 | ||
54 | RegisterAttribute N2_NcuCsr::attributeTable[] = { | |
55 | { 0x8000000000ULL,0x80000003f8ULL,0x8ULL,128,0x0ULL,0x0ULL,RegisterAttribute::RO,0xffffffffffffc0c0ULL,0x0ULL,0x3f3fULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_INTMAN","count 128 step 8" }, | |
56 | { 0x8000000a00ULL,0x8000000a00ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffc0ULL,0x0ULL,0x3fULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MONDOINVEC","" }, | |
57 | { 0x8000001000ULL,0x8000001000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_SERNUM","",true }, | |
58 | { 0x8000001008ULL,0x8000001008ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_FUSESTAT","" }, | |
59 | { 0x8000001010ULL,0x8000001010ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_COREAVAIL","" }, | |
60 | { 0x8000001018ULL,0x8000001018ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_BANKAVAIL","" }, | |
61 | { 0x8000001020ULL,0x8000001020ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_BANK_ENABLE","", true }, | |
62 | { 0x8000001028ULL,0x8000001028ULL,0x8ULL,1,0x1010ULL,0x1010ULL,RegisterAttribute::RO,0xffffffffffffe000ULL,0x0ULL,0x1fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_BANK_ENABLE_STATUS","see the explain at end re: warm",true }, | |
63 | { 0x8000001030ULL,0x8000001030ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_L2_IDX_HASH_EN","" }, | |
64 | { 0x8000001038ULL,0x8000001038ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_L2_IDX_HASH_STATUS","value of L2_IDX_HASH_EN for warm",true }, | |
65 | { 0x8000002000ULL,0x8000002000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7ffffff000ffffffULL,0x0ULL,0x8000000fff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MEM32_BASE","" }, | |
66 | { 0x8000002008ULL,0x8000002008ULL,0x8ULL,1,0xf000000000ULL,0xf000000000ULL,RegisterAttribute::RW,0xffffff0000ffffffULL,0xf000000000ULL,0xfff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MEM32_MASK","" }, | |
67 | { 0x8000002010ULL,0x8000002010ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7ffffff000ffffffULL,0x0ULL,0x8000000fff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MEM64_BASE","" }, | |
68 | { 0x8000002018ULL,0x8000002018ULL,0x8ULL,1,0xf000000000ULL,0xf000000000ULL,RegisterAttribute::RW,0xffffff0000ffffffULL,0xf000000000ULL,0xfff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MEM64_MASK","" }, | |
69 | { 0x8000002020ULL,0x8000002020ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7ffffff000ffffffULL,0x0ULL,0x8000000fff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_IOCON_BASE","" }, | |
70 | { 0x8000002028ULL,0x8000002028ULL,0x8ULL,1,0xf000000000ULL,0xf000000000ULL,RegisterAttribute::RW,0xffffff0000ffffffULL,0xf000000000ULL,0xfff000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_IOCON_MASK","" }, | |
71 | { 0x8000002030ULL,0x8000002030ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MMUFSH","" }, | |
72 | { 0x8000003000ULL,0x8000003000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7ffff89240000000ULL,0x0ULL,0x8000076dbfffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_ESR","" }, | |
73 | { 0x8000003008ULL,0x8000003008ULL,0x8ULL,1,0x7ffffffffffULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_ELE","" }, | |
74 | { 0x8000003010ULL,0x8000003010ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_EIE","" }, | |
75 | { 0x8000003018ULL,0x8000003018ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_SOC_EJR","",true }, | |
76 | { 0x8000003020ULL,0x8000003020ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_FEE","", true }, | |
77 | { 0x8000003028ULL,0x8000003028ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_PER","" }, | |
78 | { 0x8000003030ULL,0x8000003030ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7800000000000000ULL,0x0ULL,0x87ffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_SIISYN","" }, | |
79 | { 0x8000003038ULL,0x8000003038ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x300000000000000ULL,0x0ULL,0xfcffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_NCUSYN","this register have 2 format" }, | |
80 | { 0x8000040000ULL,0x8000040000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MDATA0","" }, | |
81 | { 0x8000040200ULL,0x8000040200ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MDATA1","" }, | |
82 | { 0x8000040400ULL,0x8000040400ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MDATA0_ALIAS","" }, | |
83 | { 0x8000040600ULL,0x8000040600ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MDATA1_ALIAS","" }, | |
84 | { 0x8000040800ULL,0x8000040800ULL,0x8ULL,1,0x40ULL,0x40ULL,RegisterAttribute::RW,0xffffffffffffffbfULL,0x0ULL,0x40ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MBUSY","" }, | |
85 | { 0x8000040a00ULL,0x8000040a00ULL,0x8ULL,1,0x40ULL,0x40ULL,RegisterAttribute::RW,0xffffffffffffffbfULL,0x0ULL,0x40ULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_CREG_MBUSY_ALIAS","" }, | |
86 | { 0x9001040000ULL,0x9001040000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_COREAVAIL","" }, | |
87 | { 0x9001040010ULL,0x9001040010ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_ENABLE_STATUS","value of CORE_ENABLE for warm" }, | |
88 | { 0x9001040020ULL,0x9001040020ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_ENABLE","" }, | |
89 | { 0x9001040030ULL,0x9001040030ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_XIR_STEERING","" }, | |
90 | { 0x9001040050ULL,0x9001040050ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RW,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_RUNNINGRW","" }, | |
91 | { 0x9001040058ULL,0x9001040058ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::RO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_RUNNING_STATUS","value of RUNNINGRW for warm" }, | |
92 | { 0x9001040060ULL,0x9001040060ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::WO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_RUNNING_W1S","" }, | |
93 | { 0x9001040068ULL,0x9001040068ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::WO,0x0ULL,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_CORE_RUNNING_W1C","" }, | |
94 | { 0x9001cc0000ULL,0x9001cc0000ULL,0x8ULL,1,0x0ULL,0x0ULL,RegisterAttribute::WO,0xfffffffffffc0000ULL,0x0ULL,0x3ffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_NCU_ASI_INTVECDISP","" } | |
95 | }; | |
96 | const int N2_NcuCsr::NUMBER_ENTRIES = sizeof(N2_NcuCsr::attributeTable)/sizeof(N2_NcuCsr::attributeTable[0]); | |
97 | ||
98 | //====================================================================== | |
99 | //====================================================================== | |
100 | N2_NcuCsr::N2_NcuCsr() : | |
101 | SS_BaseCsr("N2_NcuCsr", attributeTable, NUMBER_ENTRIES) | |
102 | { | |
103 | } | |
104 | ||
105 | //====================================================================== | |
106 | //====================================================================== | |
107 | int | |
108 | N2_NcuCsr::read64( SS_Paddr paddr, uint64_t* data, int access, int sid ) | |
109 | { | |
110 | SS_Paddr laddr; | |
111 | SS_Paddr gaddr; | |
112 | if (is_global_addr(paddr)) | |
113 | { | |
114 | laddr = global2local(paddr); | |
115 | gaddr = paddr; | |
116 | } | |
117 | else if (sid < 0) | |
118 | { | |
119 | // if it is not a global address, then we need a real strand-id to | |
120 | // convert the address to global address, otherwise it is an error. | |
121 | fprintf(stderr, "ERROR: N2_NcuCsr::read64( paddr=%#llx, sid=%d ): paddr not a global addr\n", paddr, sid); | |
122 | return 0x0; | |
123 | } | |
124 | else | |
125 | { | |
126 | laddr = paddr; | |
127 | gaddr = local2global(paddr, sid); | |
128 | } | |
129 | int nid = get_node_id(gaddr); | |
130 | ||
131 | list<FollowMeData>::iterator iter = followme_.begin(); | |
132 | for (; iter != followme_.end(); iter++) | |
133 | { | |
134 | if (((*iter).addr == gaddr) && (((*iter).sid == sid) || (sid < 0))) | |
135 | { | |
136 | *data = (*iter).data; | |
137 | followme_.erase(iter); | |
138 | return SS_Io::FOLLOWME; | |
139 | } | |
140 | } | |
141 | ||
142 | switch (paddr) | |
143 | { | |
144 | case NCU_ASI_COREAVAIL: | |
145 | case NCU_ASI_CORE_ENABLE_STATUS: | |
146 | case NCU_ASI_CORE_ENABLE: | |
147 | case NCU_ASI_XIR_STEERING: | |
148 | case NCU_ASI_CORE_RUNNINGRW: | |
149 | case NCU_ASI_CORE_RUNNING_STATUS: | |
150 | case NCU_ASI_CORE_RUNNING_W1S: | |
151 | case NCU_ASI_CORE_RUNNING_W1C: | |
152 | case NCU_ASI_INTVECDISP: | |
153 | case NCU_ASI_TICK_ENABLE: | |
154 | case NCU_ASI_OVERLAP_MODE: | |
155 | case NCU_ASI_WMR_VEC_MASK: | |
156 | *data = io2asiRead(paddr); | |
157 | return SS_Io::OK; | |
158 | break; | |
159 | ||
160 | default: | |
161 | return SS_BaseCsr::read64(paddr, data, access, sid); | |
162 | break; | |
163 | } | |
164 | } | |
165 | ||
166 | //====================================================================== | |
167 | //====================================================================== | |
168 | int | |
169 | N2_NcuCsr::write64( SS_Paddr paddr, uint64_t data, int access, int sid ) | |
170 | { | |
171 | SS_Paddr laddr; | |
172 | SS_Paddr gaddr; | |
173 | if (is_global_addr(paddr)) | |
174 | { | |
175 | laddr = global2local(paddr); | |
176 | gaddr = paddr; | |
177 | } | |
178 | else if (sid < 0) | |
179 | { | |
180 | // if it is not a global address, then we need a real strand-id to | |
181 | // convert the address to global address, otherwise it is an error. | |
182 | fprintf(stderr, "ERROR: Vf_CmpCsr::write64( paddr=%#llx, sid=%d ): paddr not a global addr\n", paddr, sid); | |
183 | return SS_Io::NOP; | |
184 | } | |
185 | else | |
186 | { | |
187 | laddr = paddr; | |
188 | gaddr = local2global(paddr, sid); | |
189 | } | |
190 | int nid = get_node_id(gaddr); | |
191 | ||
192 | if (access & MemoryTransaction::FOLLOW_ME) | |
193 | { | |
194 | // this is a follow-me write, keep the value in followme_ list | |
195 | FollowMeData fm(gaddr, data, sid); | |
196 | followme_.push_back(fm); | |
197 | return SS_Io::OK; | |
198 | } | |
199 | ||
200 | switch (paddr) | |
201 | { | |
202 | case NCU_ASI_COREAVAIL: | |
203 | case NCU_ASI_CORE_ENABLE_STATUS: | |
204 | case NCU_ASI_CORE_ENABLE: | |
205 | case NCU_ASI_XIR_STEERING: | |
206 | case NCU_ASI_CORE_RUNNINGRW: | |
207 | case NCU_ASI_CORE_RUNNING_STATUS: | |
208 | case NCU_ASI_CORE_RUNNING_W1S: | |
209 | case NCU_ASI_CORE_RUNNING_W1C: | |
210 | case NCU_ASI_INTVECDISP: | |
211 | case NCU_ASI_TICK_ENABLE: | |
212 | case NCU_ASI_OVERLAP_MODE: | |
213 | case NCU_ASI_WMR_VEC_MASK: | |
214 | io2asiWrite(paddr, data); | |
215 | return SS_Io::OK; | |
216 | break; | |
217 | ||
218 | default: | |
219 | return SS_BaseCsr::write64(paddr, data, access, sid); | |
220 | break; | |
221 | } | |
222 | } | |
223 | ||
224 | //============================================================================= | |
225 | //============================================================================= | |
226 | uint64_t | |
227 | N2_NcuCsr::io2asiRead(SS_Paddr paddr) | |
228 | { | |
229 | // PA[39:32] = 0x90 | |
230 | // PA[31:29] = core_id[2:0] (physical core id) | |
231 | // PA[28:26] = tid[2:0] (thread id) | |
232 | // PA[25:18] = asi[7:0] | |
233 | // PA[17:3] = VA[17:3] | |
234 | // PA[2:0] = 000 | |
235 | ||
236 | int strandid = (paddr >> 26) & 0x3f; | |
237 | int asi = (paddr >> 18) & 0xff; | |
238 | int va = ((paddr >> 3) & 0x7fff) << 3; | |
239 | ||
240 | N2_Strand* strand = N2_Csr::model->strand_ptr(strandid); | |
241 | uint64_t data; | |
242 | strand->asi_map.rd64(strand, asi, va, &data); | |
243 | return data; | |
244 | } | |
245 | ||
246 | //============================================================================= | |
247 | //============================================================================= | |
248 | void | |
249 | N2_NcuCsr::io2asiWrite(SS_Paddr paddr, uint64_t value) | |
250 | { | |
251 | // PA[39:32] = 0x90 | |
252 | // PA[31:29] = core_id[2:0] (physical core id) | |
253 | // PA[28:26] = tid[2:0] (thread id) | |
254 | // PA[25:18] = asi[7:0] | |
255 | // PA[17:3] = VA[17:3] | |
256 | // PA[2:0] = 000 | |
257 | ||
258 | int strandid = (paddr >> 26) & 0x3f; | |
259 | int asi = (paddr >> 18) & 0xff; | |
260 | int va = ((paddr >> 3) & 0x7fff) << 3; | |
261 | ||
262 | N2_Strand* strand = N2_Csr::model->strand_ptr(strandid); | |
263 | strand->asi_map.wr64(strand, asi, va, value); | |
264 | return; | |
265 | } | |
266 | ||
267 | //====================================================================== | |
268 | //====================================================================== | |
269 | void N2_NcuCsr::regAddrSpace() | |
270 | { | |
271 | const static std::string descr("N2_NcuCsr address space"); | |
272 | for (uint i = 0; i < NUMBER_ENTRIES; ++i) | |
273 | { | |
274 | if (attributeTable[i].ownAddressSpace) | |
275 | { | |
276 | registerAddressSpace(&attributeTable[i], 1, descr); | |
277 | } | |
278 | } | |
279 | } | |
280 |