projects / OpenSPARC-T2-SAM / blame
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|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: N2_NcuCsr.h | |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 7 | * | |
| 8 | * The above named program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public | |
| 10 | * License version 2 as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * The above named program is distributed in the hope that it will be | |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public | |
| 18 | * License along with this work; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 20 | * | |
| 21 | * ========== Copyright Header End ============================================ | |
| 22 | */ | |
| 23 | #ifndef N2_NCU_CSR_H | |
| 24 | #define N2_NCU_CSR_H | |
| 25 | /************************************************************************ | |
| 26 | ** | |
| 27 | ** Copyright (C) 2005, Sun Microsystems, Inc. | |
| 28 | ** | |
| 29 | ** Sun considers its source code as an unpublished, proprietary | |
| 30 | ** trade secret and it is available only under strict license provisions. | |
| 31 | ** This copyright notice is placed here only to protect Sun in the event | |
| 32 | ** the source is deemed a published work. Disassembly, decompilation, | |
| 33 | ** or other means of reducing the object code to human readable form | |
| 34 | ** is prohibited by the license agreement under which this code is | |
| 35 | ** provided to the user or company in possession of this copy." | |
| 36 | ** | |
| 37 | *************************************************************************/ | |
| 38 | #include "SS_BaseCsr.h" | |
| 39 | ||
| 40 | class N2_NcuCsr : public SS_BaseCsr | |
| 41 | { | |
| 42 | public: | |
| 43 | static const int NUMBER_ENTRIES; | |
| 44 | static RegisterAttribute attributeTable[]; | |
| 45 | ||
| 46 | static const uint64_t NCU_ASI_COREAVAIL = 0x9001040000; | |
| 47 | static const uint64_t NCU_ASI_CORE_ENABLE_STATUS = 0x9001040010; | |
| 48 | static const uint64_t NCU_ASI_CORE_ENABLE = 0x9001040020; | |
| 49 | static const uint64_t NCU_ASI_XIR_STEERING = 0x9001040030; | |
| 50 | static const uint64_t NCU_ASI_CORE_RUNNINGRW = 0x9001040050; | |
| 51 | static const uint64_t NCU_ASI_CORE_RUNNING_STATUS = 0x9001040058; | |
| 52 | static const uint64_t NCU_ASI_CORE_RUNNING_W1S = 0x9001040060; | |
| 53 | static const uint64_t NCU_ASI_CORE_RUNNING_W1C = 0x9001040068; | |
| 54 | static const uint64_t NCU_ASI_INTVECDISP = 0x9001cc0000; | |
| 55 | static const uint64_t NCU_ASI_TICK_ENABLE = 0x9001040038; | |
| 56 | static const uint64_t NCU_ASI_OVERLAP_MODE = 0x9001140010; | |
| 57 | static const uint64_t NCU_ASI_WMR_VEC_MASK = 0x9001140018; | |
| 58 | ||
| 59 | public: | |
| 60 | N2_NcuCsr(); | |
| 61 | ~N2_NcuCsr() { } | |
| 62 | ||
| 63 | int read64( SS_Paddr addr, | |
| 64 | uint64_t* data, | |
| 65 | int access=MemoryTransaction::READ, | |
| 66 | int sid=-1 ); | |
| 67 | ||
| 68 | int write64( SS_Paddr addr, | |
| 69 | uint64_t data, | |
| 70 | int access=MemoryTransaction::WRITE, | |
| 71 | int sid=-1 ); | |
| 72 | ||
| 73 | uint64_t io2asiRead(SS_Paddr paddr); | |
| 74 | void io2asiWrite(SS_Paddr paddr, uint64_t value); | |
| 75 | ||
| 76 | void warmReset() { SS_BaseCsr::warmReset(values_, NUMBER_ENTRIES); } | |
| 77 | void regAddrSpace(); | |
| 78 | }; | |
| 79 | ||
| 80 | #endif // N2_NCU_CSR_H |