Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_DramErrorCounterMem.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="DRAM_ERROR_COUNTER_REG (DRAM_ERROR_COUNTER_REG)">
    <class_name>N2_DramErrorCounterMem</class_name>
    <submodule>N2</submodule>
    <comment>
DRAM Error Counter Register. Each DRAM channel has an error counter register for use in counting DRAM errors and generating an interrupt when the counter decrements to 0 and both the ENB and VALID bits are set. Each 16B chunk with an error will cause the COUNT field to decrement by one. When the COUNT reaches zero, and ENB and VALID are set, an error interrupt is issued via INT_MAN[1] / INT_CTL[1] TABLE 12-35 shows the format of the DRAM Error Counter Register. TABLE 12-35 Register64 DRAM Error Counter Register - DRAM_ERROR_COUNTER_REG (0x84-0000-0298) (Count 4 Step 4096)
    </comment>
    <base_address>0x8400000298ULL</base_address>
    <count>4</count>
    <stride>4096</stride>
    <priv>yes</priv>
    <field name="COUNT">
        <start_offset>0</start_offset>
        <end_offset>15</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Counter that decrements with each error when the valid bit is set.
        </comment>
        <format type="hex"/>
    </field>
    <field name="VALID">
        <start_offset>16</start_offset>
        <end_offset>16</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Valid bit for counter value. This bit is reset when count decrements to zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="ENB">
        <start_offset>17</start_offset>
        <end_offset>17</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Enables interrupt generation when the counter reaches 0.
        </comment>
        <format type="hex"/>
    </field>
    <field name="RSVD0">
        <start_offset>18</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved.
        </comment>
    </field>
</register>
</register_list>