Commit | Line | Data |
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920dae64 AT |
1 | <!-- interpreter=xml2reg args='-t' --> |
2 | <register_list> | |
3 | <register name="L2_CACHE_FLUSHING_ADDRESSING_FIELDS (L2_CACHE_FLUSHING_ADDRESSING_FIELDS)"> | |
4 | <class_name>N2_L2CacheFlushAddrFields</class_name> | |
5 | <submodule>N2</submodule> | |
6 | <comment> | |
7 | This class is based on N2 PRM 1.1 Table 28-41 and splits a virtual | |
8 | address into the bit fields needed for the prefetchICE instruction. This class | |
9 | assumes 8 L2 banks. | |
10 | </comment> | |
11 | <priv>yes</priv> | |
12 | <public> | |
13 | bool checkKey() { return getKEY() == 0x3; } | |
14 | </public> | |
15 | <field name="RSVD2"> | |
16 | <start_offset>0</start_offset> | |
17 | <end_offset>5</end_offset> | |
18 | <initial_value>0</initial_value> | |
19 | <protection>RO</protection> | |
20 | <field_type>ZERO</field_type> | |
21 | <comment> | |
22 | All zero for 64-bit access. | |
23 | </comment> | |
24 | <format type="hex"/> | |
25 | </field> | |
26 | <field name="BANK"> | |
27 | <start_offset>6</start_offset> | |
28 | <end_offset>8</end_offset> | |
29 | <initial_value>0</initial_value> | |
30 | <protection>RW</protection> | |
31 | <field_type>NORMAL</field_type> | |
32 | <comment> | |
33 | Selects bank containing the cache line. | |
34 | </comment> | |
35 | <format type="hex"/> | |
36 | </field> | |
37 | <field name="SET"> | |
38 | <start_offset>9</start_offset> | |
39 | <end_offset>17</end_offset> | |
40 | <initial_value>0</initial_value> | |
41 | <protection>RW</protection> | |
42 | <field_type>NORMAL</field_type> | |
43 | <comment> | |
44 | Selects cache set containing the cache line. Assumes L2 cache | |
45 | hashing is disabled. | |
46 | </comment> | |
47 | </field> | |
48 | <field name="WAY"> | |
49 | <start_offset>18</start_offset> | |
50 | <end_offset>21</end_offset> | |
51 | <initial_value>0</initial_value> | |
52 | <protection>RW</protection> | |
53 | <field_type>NORMAL</field_type> | |
54 | <comment> | |
55 | Selects way in cache set. | |
56 | </comment> | |
57 | </field> | |
58 | <field name="RSVD1"> | |
59 | <start_offset>22</start_offset> | |
60 | <end_offset>36</end_offset> | |
61 | <initial_value>0</initial_value> | |
62 | <protection>RO</protection> | |
63 | <field_type>ZERO</field_type> | |
64 | <comment> | |
65 | Reserved. | |
66 | </comment> | |
67 | </field> | |
68 | <field name="KEY"> | |
69 | <start_offset>37</start_offset> | |
70 | <end_offset>39</end_offset> | |
71 | <initial_value>0x3</initial_value> | |
72 | <protection>RW</protection> | |
73 | <field_type>NORMAL</field_type> | |
74 | <comment> | |
75 | Must be 011, i.e. 0x3. Use of any other value places Niagara II in an | |
76 | undefined state. | |
77 | </comment> | |
78 | </field> | |
79 | <field name="RSVD0"> | |
80 | <start_offset>40</start_offset> | |
81 | <end_offset>63</end_offset> | |
82 | <initial_value>0</initial_value> | |
83 | <protection>RO</protection> | |
84 | <field_type>ZERO</field_type> | |
85 | <comment> | |
86 | Reserved. | |
87 | </comment> | |
88 | </field> | |
89 | </register> | |
90 | </register_list> |