Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocErrorReg.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="SOC_ERROR_REG (SOC_ERROR_REG)">
    <class_name>N2_SocErrorReg</class_name>
    <submodule>N2</submodule>
    <comment>
Parent for SOC Error Register classes.
    </comment>
    <priv>yes</priv>
    <public>
    typedef uint64_t (N2_SocErrorReg::*SocErrRegBitGetFn)(void) const;
    typedef void (N2_SocErrorReg::*SocErrRegBitSetFn)(uint64_t);

    static SocErrRegBitGetFn getSocErrRegMCUECC(uint_t mcuID) {
	switch (mcuID) {
	case 0: return getMCU0ECC;
	case 1: return getMCU1ECC;
	case 2: return getMCU2ECC;
	case 3: return getMCU3ECC;
	default: return 0;
	}
    }

    static SocErrRegBitSetFn setSocErrRegMCUECC(uint_t mcuID) {
	switch (mcuID) {
	case 0: return setMCU0ECC;
	case 1: return setMCU1ECC;
	case 2: return setMCU2ECC;
	case 3: return setMCU3ECC;
	default: return 0;
	}
    }

    static SocErrRegBitGetFn getSocErrRegMCUFBR(uint_t mcuID) {
	switch (mcuID) {
	case 0: return getMCU0FBR;
	case 1: return getMCU1FBR;
	case 2: return getMCU2FBR;
	case 3: return getMCU3FBR;
	default: return 0;
	}
    }

    static SocErrRegBitSetFn setSocErrRegMCUFBR(uint_t mcuID) {
	switch (mcuID) {
	case 0: return setMCU0FBR;
	case 1: return setMCU1FBR;
	case 2: return setMCU2FBR;
	case 3: return setMCU3FBR;
	default: return 0;
	}
    }

    </public>
    <field name="SPARE4">
        <start_offset>43</start_offset>
        <end_offset>62</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="NCUDMUCREDIT">
        <start_offset>42</start_offset>
        <end_offset>42</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if an uncorrectable parity error is detectd on the credit
token bus to NCU for DMU PIO write credits.
        </comment>
        <format type="hex"/>
    </field>
    <field name="MCU3ECC">
        <start_offset>41</start_offset>
        <end_offset>41</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 3 detected a correctable DRAM ECC error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="MCU3FBR">
        <start_offset>40</start_offset>
        <end_offset>40</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 3 detected a FBDIMM recoverable error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="SPARE3">
        <start_offset>39</start_offset>
        <end_offset>39</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="MCU2ECC">
        <start_offset>38</start_offset>
        <end_offset>38</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 2 detected a correctable DRAM ECC error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="MCU2FBR">
        <start_offset>37</start_offset>
        <end_offset>37</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 2 detected a FBDIMM recoverable error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="SPARE2">
        <start_offset>36</start_offset>
        <end_offset>36</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="MCU1ECC">
        <start_offset>35</start_offset>
        <end_offset>35</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 1 detected a correctable DRAM ECC error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="MCU1FBR">
        <start_offset>34</start_offset>
        <end_offset>34</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 1 detected a FBDIMM recoverable error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="SPARE1">
        <start_offset>33</start_offset>
        <end_offset>33</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="MCU0ECC">
        <start_offset>32</start_offset>
        <end_offset>32</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 0 detected a correctable DRAM ECC error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="MCU0FBR">
        <start_offset>31</start_offset>
        <end_offset>31</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Set to 1 if MCU 0 detected a FBDIMM recoverable error with its DRAM
Recoverable Link Error count reaching zero.
        </comment>
        <format type="hex"/>
    </field>
    <field name="SPARE0">
        <start_offset>30</start_offset>
        <end_offset>30</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
<!-- Lots more fields left to the imagination.  For details, see -->
<!-- Table 12-50.  These are covered by DUMMY. -->
    <field name="DUMMY">
        <start_offset>0</start_offset>
        <end_offset>29</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
</register>
</register_list>