Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocErrorSteeringReg.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="SOC_ERROR_STEERING_REG (SOC_ERROR_STEERING_REG)">
    <class_name>N2_SocErrorSteeringReg</class_name>
    <submodule>N2</submodule>
    <comment>
SOC Error Steering Register. This register controls which virtual core
will be sent SOC error interrupts.  TABLE 12-53 shows the format of
the SOC Error Steering Register. TABLE 12-53  SOC Error Steering Register - SOC_ERROR_STEERING_REG (0x90-0104-1000)
    </comment>
    <base_address>0x9001041000ULL</base_address>
    <count>1</count>
    <stride>8</stride>
    <priv>yes</priv>
    <field name="RSVD">
        <start_offset>6</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="VCID">
        <start_offset>0</start_offset>
        <end_offset>5</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
ID of virtual core that will be the target of SOC error interrupts.
        </comment>
        <format type="hex"/>
    </field>
</register>
</register_list>