Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocFatalErrorEnableReg.xml

<!-- interpreter=xml2reg args='-t'-->
<register_list>
<register name="SOC_ERROR_INTERRUPT_ENABLE_REG (SOC_ERROR_INTERRUPT_ENABLE_REG)">
    <class_name>N2_SocFatalErrorEnableReg</class_name>
    <submodule>N2</submodule>
    <comment>
SOC Fatal Error Enable Register.  This register controls  which
errors will generate a fatal error, resetting the Niagara 2.
TABLE 12-54 shows the format of the SOC Fatal Error Enable Register. TABLE 12-54
SOC Fatal Error Enable Register - SOC_FATAL_ERROR_ENABLE_REG (0x80-0000-3020)
    </comment>
    <inherits>n2/lib/ras/xml/N2_SocErrorReg.xml</inherits>
    <base_address>0x8000003020ULL</base_address>
    <count>1</count>
    <stride>8</stride>
    <priv>yes</priv>
    <field name="DUMMY1">
        <start_offset>63</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Unused.
        </comment>
        <format type="hex"/>
    </field>
</register>
</register_list>