Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocPendingErrStatusReg.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="SOC_PENDING_ERROR_STATUS_REG (SOC_PENDING_ERROR_STATUS_REG)">
    <class_name>N2_SocPendingErrStatusReg</class_name>
    <submodule>N2</submodule>
    <comment>
SOC Pending Error Status Register. This register contains the state of
the SOC_ERROR_STATUS_REG when the disrupting trap was generated as a
result of an SOC error logged that had its corresponding bit set in
teh SOC_ERROR_INTERRUPT_ENABLE_REG.  The valid bit of this register
prevent further disrupting traps from being generated by the SOC.  
This register is not cleared on warm reset so
software can examine its contents after a warm reset. TABLE
12-55 shows the format of the SOC Pending Error Status Register. TABLE 12-55
SOC Pending Error Status Register - SOC_PENDING_ERROR_STATUS_REG (0x80-0000-3028)
    </comment>
    <inherits>n2/lib/ras/xml/N2_SocErrorReg.xml</inherits>
    <base_address>0x8000003028ULL</base_address>
    <count>1</count>
    <stride>8</stride>
    <priv>yes</priv>
    <field name="V">
        <start_offset>63</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Multiple uncorrected errors, one or more uncorrected errors were not logged.
        </comment>
        <format type="hex"/>
    </field>
</register>
</register_list>