Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / memsync / src / MemoryAccessEntry.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: MemoryAccessEntry.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include "MemoryAccessEntry.h"
#include <sstream>

using namespace std;

////////////////////////////////////////////////

uint64_t MemoryAccessEntry::maeid = 0;

MemoryAccessEntry::MemoryAccessEntry() :
    dmaStore(false),
    tsize(0),
    writeBack(false),
    invSet(false)
{
  valid_ = true;
  vlink_ = false;
  acked_ = false;
  vlink2_ = false;

  id_ = MemoryAccessEntry::maeid++;
}

MemoryAccessEntry::MemoryAccessEntry(LoadStoreCmd& cmd) :
    dmaStore(false),
    tsize(cmd.getTsize()),
    writeBack(false),
    invSet(false)
{
  addr_ = cmd.getAddr();
  data_ = cmd.getData();
  tid_ = cmd.getThrdId(); 
  cid_ = cmd.getCoreId(); 
  inv_ = cmd.getInv(); 
  etype_ = cmd.getCmd(); 
  itype_ = cmd.getItype(); 
  dsrc_ = cmd.getDsrc(); 
  vbyte_ = cmd.getVbyte();
  cacheL1_ = cmd.isCacheL1(); 
  srcBank_ = cmd.getSrcBank(); 
  way_     = cmd.getWay(); 
  set_     = cmd.getSet(); 
  switchData_ = cmd.isSwitchData(); 
  cycle_ = cmd.getCycle();
  executed_ = false;
  valid_ = true;
  vlink_ = false;
  vlink2_ = false;
  cinv_ = 0;
  acked_ = false;
  id_ = MemoryAccessEntry::maeid++;
  dsrcMid_ = id_; 
  global_ = id_; 
  iseq_    = 0; 
  popped_ = false;
}
////////////////////////////////////////////////

MemoryAccessEntry::MemoryAccessEntry( const MemoryAccessEntry & orig )
{
    link_     = orig.link_;
    addr_     = orig.addr_;
    data_     = orig.data_;
    tid_      = orig.tid_;
    cid_      = orig.cid_;
    inv_      = orig.inv_;
    cinv_     = orig.cinv_;
    srcBank_  = orig.srcBank_;
    way_      = orig.way_;
    set_      = orig.set_;
    etype_    = orig.etype_;
    itype_    = orig.itype_;
    dsrc_     = orig.dsrc_;
    vbyte_    = orig.vbyte_;
    cacheL1_  = orig.cacheL1_;
    executed_ = orig.executed_;    
    valid_    = orig.valid_;
    vlink_    = orig.vlink_;
    id_       = orig.id_;
    acked_    = orig.acked_;
    link2_    = orig.link2_;
    vlink2_   = orig.vlink2_;
    dsrcMid_  = orig.dsrcMid_; 
    global_  = orig.global_; 
    iseq_     = orig.iseq_; 
    switchData_ = orig.switchData_; 
    popped_ = orig.popped_;
    cycle_ = orig.cycle_;
    merged_ = orig.merged_;
    origData_ = orig.origData_;
    origVbyte_ = orig.origVbyte_;
    dmaStore = orig.dmaStore;
    tsize = orig.tsize;
    writeBack = orig.writeBack;
    invSet = orig.invSet;
}

////////////////////////////////////////////////

MemoryAccessEntry::~MemoryAccessEntry()
{
}

////////////////////////////////////////////////

const MemoryAccessEntry &
MemoryAccessEntry::operator=( const MemoryAccessEntry & rhs )
{
    // Replace the following line with your function body.
  // RIESLING_THROW_DOMAIN_ERROR( "Unimplemented function." );

    return *this;
}

////////////////////////////////////////////////

bool
MemoryAccessEntry::operator==( const MemoryAccessEntry & rhs ) const
{ 
    // Replace the following line with your function body.
  // RIESLING_THROW_DOMAIN_ERROR( "Unimplemented function." );
    return false;
}

////////////////////////////////////////////////

string
MemoryAccessEntry::toString() const
{
    ostringstream os;
    os << "MAE ";
    os << "(";
    os << "id="     << dec << id_; 
    os << " v="      << (int) valid_;
    os << " e="     << mmcmd[etype_];
    os << " i="     << mmitype[itype_];
    os << " dsrc="  << mmdsrc[dsrc_];
    os << " cid="   << dec << cid_;
    os << " tid="   << dec << tid_;
    os << " inv=0x" << hex << inv_;
    os << " cinv=0x" << hex << cinv_;
    os << " bank="  << dec << srcBank_;
    os << " s="     << dec << set_;
    os << " w="     << dec << way_;
    os << " ack="   << (int) acked_;
    os << " a=0x"   << hex << addr_;
    os << " d=0x"   << hex << data_;
    os << " vb=0x"  << hex << (int) vbyte_;
    os << " cas="   << dec << (int) switchData_; 
    os << " exe="   << dec << (int) executed_;
    os << " $="     << dec << (int) cacheL1_;
    os << " ds="    << dec << dsrcMid_;
    os << " di="    << dec << global_; 
    os << " iseq="  << dec << iseq_; 
    os << " pop="   << dec << (int) popped_;
    os << " dmaSt=" << dmaStore;
    os << " invSet=" << invSet;
    os << " tsize=" << dec << tsize;
//     if (vlink_) {
//       os << " l:id=" << dec << link_->getId(); 
//       os << " l:e=" << mmcmd[link_->getEntryType()]; 
//       os << " l:tid="  << link_->getThrdId();
//       os << " l:a=0x"  << hex << link_->getAddr();
//       os << " l:d=0x"  << hex << link_->getData(); 
//     }
    os << " cycle=" << dec << cycle_;
    os << ")";
    os << endl;

    return os.str();
}