Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / memsync / src / MemorySyncDefs.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: MemorySyncDefs.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef _MEMORYMODELDEFS_H
#define _MEMORYMODELDEFS_H
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include "RieslingInterface.h"

#define MAX_STRANDS        RieslingInterface::max_strands 
#define NSTRANDS_PER_CORE  RieslingInterface::strands_per_core 

#define ICACHE_LINE_SIZE   32
#define DCACHE_LINE_SIZE   16
#define L2CACHE_LINE_SIZE  64

#define N_IFBUF_ENTRIES    16
#define N_LDBUF_ENTRIES    16
#define N_STBUF_ENTRIES    64

#ifdef PROC_KT
#define IO_ADDR_BIT_MASK   0x80000000000ull // bit 43
#else // PROC_KT
#define IO_ADDR_BIT_MASK   0x8000000000ull // bit 39
#endif // PROC_KT
#define L2_BANK_ADDR_BITS  0x1c0ull        // bits 8:6
#define L2_BANK_ADDR_SFT   6               // begins at bit 6

#define DATA_SIZE          8
#define ADDR_MASK          0xfffffffffffffff8ull
#define FULL_ADDR_MASK     0xffffffffffffffffull
#define BLK_ADDR_MASK      0xfffffffffffffff8ull
#define QUAD_OP_ADDR_MASK  0xfffffffffffffff0ull
#define BLK_OP_ADDR_MASK   0xffffffffffffffc0ull
#ifdef PROC_KT
#define L2_CACHE_LINE_MASK  0x00000ffffffffff0ull   // PA[43:4]
#else // PROC_KT
#define L2_CACHE_LINE_MASK  0x000000fffffffff0ull   // PA[39:4]
#endif // PROC_KT
#define L1_CACHE_INDEX_MASK 0x00000000000007f0ull   // PA[10:4]
#define INV_VEC_SIZE       16

/*   typedef uint64_t cycle_t; */
/*   typedef uint64_t addr_t; */
/*   typedef uint64_t data_t; */
/*   typedef uint8_t  size_t;   */

  enum INSTR_TYPE {ITYPE_NONE = 0, ITYPE_LOAD, ITYPE_BLOCK_LOAD, ITYPE_DOUBLE_LOAD, ITYPE_QUAD_LOAD, 
		   ITYPE_PREFETCH, ITYPE_STORE, ITYPE_BLOCK_STORE, ITYPE_ATOMIC, ITYPE_STORE_INIT, 
		   ITYPE_FETCH};
  
  static char* mmitype[] = {(char*) "NA", (char*) "ld", (char*) "bl", (char*) "dl", (char*) "ql", 
			    (char*) "pf", (char*) "st", (char*) "bs", (char*) "at",
			    (char*) "si", (char*) "if"};

  /* Memory Operation Type */
  enum MEM_CMD {MEM_LOAD_ISSUE = 0, MEM_LOAD_DATA, MEM_LOAD_FILL, MEM_STORE_ISSUE, 
		MEM_STORE_COMMIT, MEM_STORE_INV, MEM_STORE_UPDATE, MEM_STORE_ACK, 
		MEM_EVICT, MEM_EVICT_INV, MEM_FETCH_ISSUE, MEM_FETCH_DATA, MEM_FETCH_FILL, 
		MEM_DMA_STORE, MEM_DMA_STORE_START, MAX_MEM_CMDS};
  
  static char* mmcmd[] = {(char*) "LI", (char*) "LD", (char*) "LF", (char*) "SI", (char*) "SC", 
			  (char*) "SV", (char*) "SU", (char*) "SA", (char*) "EV", (char*) "EI",
			  (char*) "FI", (char*) "FD", (char*) "FF", (char*) "DS",  (char*) "DSS", 
                          (char*) "NA"};

  /* Load Data Sourece */
  enum DATA_SRC {DSRC_NONE = 0, DSRC_STB, DSRC_L1, DSRC_L2_MEMORY, DSRC_IO};

  static char* mmdsrc[] = {(char*) "NA", (char*) "SB", (char*) "L1", (char*) "L2", (char*) "IO"};
  
  /* buffer state */
  enum LS_ENTRY_STATE {LS_NEW = 0, LS_TDATA, LS_RDATA, LS_ISSUE, LS_ACK, LS_UPDATE, 
		       LS_INV, LS_RETIRE};
  
  static char* lstate[] = {(char*) "NEW", (char*) "TDT", (char*) "RDT",
			   (char*) "ISS", (char*) "ACK", (char*) "UPD",
			   (char*) "INV", (char*) "RET"};

  /* DMA_STORE flags */
  enum DMA_STORE_ACT { DMA_STORE = 0, DMA_EVICT, DMA_EVICT_INV };

  extern uint64_t rtlCycle;

#endif /* _MEMORYMODELDEFS_H */