Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / memsync / src / TsoCheckerCmd.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: TsoCheckerCmd.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef _TSOCHECKERCMD_H
#define _TSOCHECKERCMD_H
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include <iostream>

#include "MemorySyncDefs.h"
#include "TsoCheckerDefs.h"

namespace Tso {
  
  
  class TsoCheckerCmd {
    
  public:
    /**
     * Default constructor
     */
    TsoCheckerCmd();
    
    /**
     * Copy constructor
     * 
     * @param orig The TsoCheckerCmd object to copy.
     */
    TsoCheckerCmd( const TsoCheckerCmd &orig );
    
    /**
     * Destructor
     */
    virtual ~TsoCheckerCmd();
    
    /**
     * Equality operator
     * 
     * @param rhs The right hand side of the equality operator
     * @return Return true if this objec and rhs are equal, 
     * otherwise return false
     */
    bool operator==( const TsoCheckerCmd &rhs ) const;
    
    /**
     * Assignment operator
     * 
     * @param rhs The right hand side of the assignment operator.
     * @return The lvalue of the assignment.
     */
    const TsoCheckerCmd & operator=( const TsoCheckerCmd &rhs );
    
    /**
     * Return a string representation of this TsoCheckerCmd object. 
     */
    std::string toString() const;

    /**
     * Check to see if the node coresponds to a store instruction
     * Note that atomic is also counted as a store instruction.
     * @return a boolean to relect this check
     */
    isStore() { return (itype_ == ITYPE_STORE ||
			itype_ == ITYPE_BLOCK_STORE || 
			itype_ == ITYPE_STORE_INIT  ||
			itype_ == ITYPE_ATOMIC); }

    /**
     * Check to see if the node coresponds to a load instruction
     * Note that atomic is also counted as a load instruction.
     * @return a boolean to relect this check
     */
    isLoad() { return (itype_ == ITYPE_LOAD ||
		       itype_ == ITYPE_BLOCK_LOAD ||
		       itype_ == ITYPE_QUAD_LOAD  ||
		       itype_ == ITYPE_DOUBLE_LOAD ||
		       itype_ == ITYPE_ATOMIC); }

    /**
     * Check to see if the node coresponds to an atomic instruction
     * @return a boolean to relect this check
     */    
    isAtomic() { return (itype_ == ITYPE_ATOMIC); }

    /**
     * Check to see if the node's addres is in I/O range
     * @return a boolean to relect this check
     */
    isIO() { return ((addr_ & IO_ADDR_BIT_MASK) != 0); }

    /**
     * Check to see if the node coresponds to a RMO store instruction
     * @return a boolean to relect this check
     */    
    isRmoStore() { return (itype_ == ITYPE_BLOCK_STORE || itype_ == ITYPE_STORE_INIT); }

    /**
     * Check to see if the node coresponds to a RMO instruction
     * @return a boolean to relect this check
     */    
    isRMO() { return (itype_ == ITYPE_BLOCK_STORE || 
		      itype_ == ITYPE_STORE_INIT  ||
		      itype_ == ITYPE_BLOCK_LOAD); } 

    /**
     * Check to see if the node corresponds to a TSO load instruction
     * A TSO load is defined as a load whose address is not in I/O space
     * and is not a RMO load
     * @return a boolean
     */
    isTsoLoad()  { return (isLoad() && !isRMO() && !isIO()); }

    /**
     * Check to see if the node corresponds to a TSO store instruction
     * A TSO store is defined as a store whose address is not in I/O space
     * and is not a RMO store
     * @return a boolean
     */
    isTsoStore() { return (isStore() && !isRMO() && !isIO()); }

    /**
     * Check to see if the node corresponds to a TSO instruction
     * A TSO instruciton is defined as an instruction whose address is not 
     * in I/O space and is not a RMO instruction
     * @return a boolean
     */    
    isTSO() { return (isTsoLoad() || isTsoStore()); }

    /**
     * Check the if the node is MEM_STORE_COMMIT
     * @return a bollena
     */
    isStoreCommit() { return (cmd_ == MEM_STORE_COMMIT); }

    /**
     * Check the if the node is MEM_LOAD_DATA
     * @return a bollena
     */
    isLoadData() { return (cmd_ == MEM_LOAD_DATA); }

    /******************************************************************
     * Private variable get/set methods
     ******************************************************************/  
    void setTime (uint64_t time) { time_ = time; }
    void setIseq (uint64_t iseq) { iseq_ = iseq; }     
    void setMacc (uint64_t macc) { macc_ = macc; } 
    void setGobs (uint64_t gobs) { gobs_ = gobs; } 
    void setAddr (uint64_t addr) { addr_ = addr; } 
    void setThrdId (uint32_t tid) { tid_ = tid; }      
    void setItype (enum INSTR_TYPE itype) { itype_ = itype; } 
    void setCmd (enum MEM_CMD cmd) { cmd_ = cmd; }   
    void setDsrc (enum DATA_SRC dsrc) { dsrc_ = dsrc; }  
    void setSizeV (uint8_t sizeV) { sizeV_ = sizeV; }   
    void setData  (uint64_t data) { data_ = data; }

    uint64_t getTime() const { return time_; }
    uint64_t getIseq() const { return iseq_; }     
    uint64_t getMacc() const { return macc_; } 
    uint64_t getGobs() const { return gobs_; }  
    uint64_t getAddr() const { return addr_; }    
    uint64_t getData() const { return data_; }
    uint32_t getThrdId() const { return tid_; }     
    enum INSTR_TYPE getItype() const { return itype_; } 
    enum MEM_CMD    getCmd()   const { return cmd_; }   
    enum DATA_SRC   getDsrc()  const { return dsrc_; }  
    uint8_t         getSizeV() const { return sizeV_; }   

    
  protected:

  private:
    /**
     * iseq_ is the load/store instruction sequence, must consecutive 
     * but can be out-of-order
     */
    uint64_t iseq_;  

    /**
     * time_ is when the access happens
     */
    uint64_t time_;

    /**
     * macc_ has different definitions for store and load. <br>
     * <p>
     * For store it is the time when a store commits (for N2, 
     * it is the time when the data is written into L2 and can be seen 
     * by other L2 access). <br>
     * <p>
     * For load, it is any time in the duration when the whole data can
     * be seen in an L2 access. Note the source of a load may come from 
     * several stores.
     */
    uint64_t macc_;  

    /**
     * gobs_ is the global observed time of a store. Note that a store
     * may have stale data in L1 caches of other cores, or caches of 
     * other chips. Before a store data can be globally observed, all
     * those stale data must be either invalidated or be updated. <br>
     * <p>
     * The gobs_ must be no earlier than its L2 commit time, macc_.
     */
    uint64_t gobs_;  // global observed time
    
    /**
     * addr_ is the physical address.
     */
    uint64_t addr_;  // address
    
    /**
     * data_ is either the load data or store data.
     */
    uint64_t data_; 

    /**
     * tid_ is a flat thread ID; each thread must have a unique ID.
     */
    uint32_t tid_;   // thread ID

    /**
     * itype_ is the instruction type, such as load, store, block load/store, 
     * etc, whose definition is in 
     * @see MemorySyncDefs.h
     */
    enum INSTR_TYPE itype_; // instruction type

    /**
     * cmd_ is the entry type, such as StoreCommit and LoadData, whose 
     * defintion is in
     * @see MemorySyncDefs.h
     */
    enum MEM_CMD    cmd_;   // command 
 
    /**
     * dsrc_ is the source of a load data, which could be L1, STB, or
     * L2/Memory.
     * @see MemorySyncDefs.h
     */
    enum DATA_SRC   dsrc_;  // data source

    /**
     * The data format is as follows: (Big Edian)
     * 
     *       bit  63                                    0 
     *           +--------+--------+------------+--------+ <br>
     * data      | byte 0 | byte 1 |    ---     | byte 7 | <br>   
     * (64 bits) +--------+--------+------------+--------+ <br>
     *
     * sizeV_:      bit 7   bit  6                 bit 0   <br>
     * (8 bits) <br>
     *
     * sizeV_ is to indicates which byte is valid: bit 0 for data_[7:0],
     * bit 1 for data_[15:8], and so on.
     */
    uint8_t         sizeV_; // size vector: 1-> valid byte
};

} /* namespace Tso */

#endif /* _TSOCHECKERCMD_H */