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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / pfe / bin / SS_Model.py
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AT		 1# ========== Copyright Header Begin ==========================================
2#
3# OpenSPARC T2 Processor File: SS_Model.py
4# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6#
7# The above named program is free software; you can redistribute it and/or
8# modify it under the terms of the GNU General Public
9# License version 2 as published by the Free Software Foundation.
10#
11# The above named program is distributed in the hope that it will be
12# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14# General Public License for more details.
15#
16# You should have received a copy of the GNU General Public
17# License along with this work; if not, write to the Free Software
18# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19#
20# ========== Copyright Header End ============================================
21
22### @-ARCH-@_Model.py is automatically generated from
23### ss/api/pfe/bin/Bl_Model.py, do not modify @-ARCH-@_Model.py,
24### make necessary changes in ss/api/pfe/bin/Bl_Model.py instead.
25
26import Pfe_Tlb
27import Pfe_Model
28
29from SS_Break import *
30from Pfe_Tlb import Tte
31from Pfe_Conversion import *
32from Pfe_Assembler import asm
33
34import @-ARCH-@_Python
35import SS_Strand
36from SS_Strand import AsiState
37
38dis = @-ARCH-@_Python.dis
39
40SS_Strand.__asi_va__ = {}
41for i in range(0,8):
42 SS_Strand.__asi_va__['scratch'+chr(i+ord('0'))] = AsiState(0x20,i*8)
43 SS_Strand.__asi_va__['hscratch'+chr(i+ord('0'))] = AsiState(0x4f,i*8)
44
45SS_Strand.__asi_va__['strand_available'] = AsiState(0x41,0x00)
46SS_Strand.__asi_va__['strand_enable_status'] = AsiState(0x41,0x10)
47SS_Strand.__asi_va__['strand_enable'] = AsiState(0x41,0x20)
48SS_Strand.__asi_va__['strand_running'] = AsiState(0x41,0x50)
49SS_Strand.__asi_va__['strand_running_status'] = AsiState(0x41,0x58)
50SS_Strand.__asi_va__['strand_running_w1s'] = AsiState(0x41,0x60)
51SS_Strand.__asi_va__['strand_running_w1c'] = AsiState(0x41,0x68)
52SS_Strand.__asi_va__['xir_steering'] = AsiState(0x41,0x30)
53SS_Strand.__asi_va__['tick_enable'] = AsiState(0x41,0x38)
54
55SS_Strand.__asi_va__['intr_w'] = AsiState(0x73,0x0)
56
57SS_Strand.__asi_va__['pri_ctx0'] = AsiState(0x21,0x008)
58SS_Strand.__asi_va__['pri_ctx1'] = AsiState(0x21,0x010)
59SS_Strand.__asi_va__['sec_ctx0'] = AsiState(0x21,0x108)
60SS_Strand.__asi_va__['sec_ctx1'] = AsiState(0x21,0x110)
61
62SS_Strand.__asi_va__['lsu_ctr'] = AsiState(0x45,0x0)
63
64SS_Strand.__asi_va__['inst_tag_target'] = AsiState(0x50,0x00)
65SS_Strand.__asi_va__['inst_sfsr'] = AsiState(0x50,0x18)
66SS_Strand.__asi_va__['inst_tag_access'] = AsiState(0x50,0x30)
67SS_Strand.__asi_va__['inst_tlb_data_in_v'] = AsiState(0x54,0x000)
68SS_Strand.__asi_va__['inst_tlb_data_in_r'] = AsiState(0x54,0x400)
69
70SS_Strand.__asi_va__['data_tag_target'] = AsiState(0x58,0x00)
71SS_Strand.__asi_va__['data_sfsr'] = AsiState(0x58,0x18)
72SS_Strand.__asi_va__['data_sfar'] = AsiState(0x58,0x20)
73SS_Strand.__asi_va__['data_tag_access'] = AsiState(0x58,0x30)
74SS_Strand.__asi_va__['data_tlb_data_in_v'] = AsiState(0x5c,0x000)
75SS_Strand.__asi_va__['data_tlb_data_in_r'] = AsiState(0x5c,0x400)
76
77SS_Strand.__asi_va__['partition_id'] = AsiState(0x58,0x80)
78
79SS_Strand.__asi_va__['real_range0'] = AsiState(0x52,0x108)
80SS_Strand.__asi_va__['real_range1'] = AsiState(0x52,0x110)
81SS_Strand.__asi_va__['real_range2'] = AsiState(0x52,0x118)
82SS_Strand.__asi_va__['real_range3'] = AsiState(0x52,0x120)
83
84SS_Strand.__asi_va__['phys_offset0'] = AsiState(0x52,0x208)
85SS_Strand.__asi_va__['phys_offset1'] = AsiState(0x52,0x210)
86SS_Strand.__asi_va__['phys_offset2'] = AsiState(0x52,0x218)
87SS_Strand.__asi_va__['phys_offset3'] = AsiState(0x52,0x220)
88
89SS_Strand.__asi_va__['nuc_tsb_cfg0'] = AsiState(0x54,0x010)
90SS_Strand.__asi_va__['nuc_tsb_cfg1'] = AsiState(0x54,0x018)
91SS_Strand.__asi_va__['nuc_tsb_cfg2'] = AsiState(0x54,0x020)
92SS_Strand.__asi_va__['nuc_tsb_cfg3'] = AsiState(0x54,0x028)
93
94SS_Strand.__asi_va__['non_nuc_tsb_cfg0'] = AsiState(0x54,0x030)
95SS_Strand.__asi_va__['non_nuc_tsb_cfg1'] = AsiState(0x54,0x038)
96SS_Strand.__asi_va__['non_nuc_tsb_cfg2'] = AsiState(0x54,0x040)
97SS_Strand.__asi_va__['non_nuc_tsb_cfg3'] = AsiState(0x54,0x048)
98
99SS_Strand.__asi_va__['inst_tsb_ptr0'] = AsiState(0x54,0x050)
100SS_Strand.__asi_va__['inst_tsb_ptr1'] = AsiState(0x54,0x058)
101SS_Strand.__asi_va__['inst_tsb_ptr2'] = AsiState(0x54,0x060)
102SS_Strand.__asi_va__['inst_tsb_ptr3'] = AsiState(0x54,0x068)
103
104SS_Strand.__asi_va__['data_tsb_ptr0'] = AsiState(0x54,0x070)
105SS_Strand.__asi_va__['data_tsb_ptr1'] = AsiState(0x54,0x078)
106SS_Strand.__asi_va__['data_tsb_ptr2'] = AsiState(0x54,0x080)
107SS_Strand.__asi_va__['data_tsb_ptr3'] = AsiState(0x54,0x088)
108
109
110def __tte_getvalid__(tte): return bool(tte.valid_bit())
111def __tte_setvalid__(tte,val): tte.valid_bit(val)
112def __tte_getreal__(tte): return bool(tte.real_bit())
113def __tte_setreal__(tte,val): tte.real_bit(val)
114def __tte_getpid__(tte): return tte.pid()
115def __tte_setpid__(tte,val): tte.pid(val)
116def __tte_getctx__(tte): return tte.context()
117def __tte_setctx__(tte,val): tte.context(val)
118def __tte_gettag__(tte): return tte.tag()
119def __tte_settag__(tte,val): tte.tag(val)
120def __tte_getsize__(tte): return tte.page_size()
121def __tte_setsize__(tte,val): tte.page_size(val)
122def __tte_getnfo__(tte): return bool(tte.nfo())
123def __tte_setnfo__(tte,val): tte.nfo(val)
124def __tte_getie__(tte): return bool(tte.ie())
125def __tte_setie__(tte,val): tte.ie(val)
126def __tte_getw__(tte): return bool(tte.w())
127def __tte_setw__(tte,val): tte.w(val)
128def __tte_getx__(tte): return bool(tte.x())
129def __tte_setx__(tte,val): tte.x(val)
130def __tte_getp__(tte): return bool(tte.p())
131def __tte_setp__(tte,val): tte.p(val)
132def __tte_gete__(tte): return bool(tte.e())
133def __tte_sete__(tte,val): tte.e(val)
134def __tte_getaddr__(tte): return tte.taddr()
135def __tte_setaddr__(tte,val): tte.taddr(val)
136
137# for unused fields in the TTE
138
139def __tte_getfalse__(tte): return False
140def __tte_setpass__(tte,val): pass
141
142class __tte_xlate__:
143 def __init__(self,tte):
144 self.tte = tte
145 def __call__(self,addr):
146 return self.tte.trans(addr)
147
148class __tte_match__:
149 def __init__(self,tte):
150 self.tte = tte
151 def __call__(self,addr,ctx=0,pid=0,real=False,page_size_mask=0xff):
152 if real:
153 self.tte.match_real(addr,pid,page_size_mask)
154 else:
155 self.tte.match_virt(addr,ctx,pid,page_size_mask)
156
157Pfe_Tlb.TlbTte.__getfun__['xlate'] = __tte_xlate__
158Pfe_Tlb.TlbTte.__getfun__['match'] = __tte_match__
159
160Pfe_Tlb.TlbTte.__getfun__['valid'] = __tte_getvalid__
161Pfe_Tlb.TlbTte.__setfun__['valid'] = __tte_setvalid__
162Pfe_Tlb.TlbTte.__getfun__['real'] = __tte_getreal__
163Pfe_Tlb.TlbTte.__setfun__['real'] = __tte_setreal__
164Pfe_Tlb.TlbTte.__getfun__['pid'] = __tte_getpid__
165Pfe_Tlb.TlbTte.__setfun__['pid'] = __tte_setpid__
166Pfe_Tlb.TlbTte.__getfun__['ctx'] = __tte_getctx__
167Pfe_Tlb.TlbTte.__setfun__['ctx'] = __tte_setctx__
168Pfe_Tlb.TlbTte.__getfun__['size'] = __tte_getsize__
169Pfe_Tlb.TlbTte.__setfun__['size'] = __tte_setsize__
170Pfe_Tlb.TlbTte.__getfun__['tag'] = __tte_gettag__
171Pfe_Tlb.TlbTte.__setfun__['tag'] = __tte_settag__
172Pfe_Tlb.TlbTte.__getfun__['ie'] = __tte_getie__
173Pfe_Tlb.TlbTte.__setfun__['ie'] = __tte_setie__
174Pfe_Tlb.TlbTte.__getfun__['nfo'] = __tte_getnfo__
175Pfe_Tlb.TlbTte.__setfun__['nfo'] = __tte_setnfo__
176Pfe_Tlb.TlbTte.__getfun__['x'] = __tte_getx__
177Pfe_Tlb.TlbTte.__setfun__['x'] = __tte_setx__
178Pfe_Tlb.TlbTte.__getfun__['p'] = __tte_getp__
179Pfe_Tlb.TlbTte.__setfun__['p'] = __tte_setp__
180Pfe_Tlb.TlbTte.__getfun__['w'] = __tte_getw__
181Pfe_Tlb.TlbTte.__setfun__['w'] = __tte_setw__
182Pfe_Tlb.TlbTte.__getfun__['e'] = __tte_gete__
183Pfe_Tlb.TlbTte.__setfun__['e'] = __tte_sete__
184Pfe_Tlb.TlbTte.__getfun__['addr'] = __tte_getaddr__
185Pfe_Tlb.TlbTte.__setfun__['addr'] = __tte_setaddr__
186
187Pfe_Tlb.TlbTte.__getfun__['cv'] = __tte_getfalse__
188Pfe_Tlb.TlbTte.__setfun__['cv'] = __tte_setpass__
189Pfe_Tlb.TlbTte.__getfun__['cp'] = __tte_getfalse__
190Pfe_Tlb.TlbTte.__setfun__['cp'] = __tte_setpass__
191Pfe_Tlb.TlbTte.__getfun__['lock'] = __tte_getfalse__
192Pfe_Tlb.TlbTte.__setfun__['lock'] = __tte_setpass__
193
194
195class Tlb(Pfe_Tlb.Tlb):
196 def __init__(self,tlb):
197 Pfe_Tlb.Tlb.__init__(self,tlb)
198
199 def size(self):
200 return self.__tlb__.size()
201
202 def index(self,index):
203 if index < 0 or index >= self.size():
204 raise IndexError
205 else:
206 return self.__tlb__.get(index)
207
208 def insert(self,tte):
209 if isinstance(tte,Tte):
210 ss_tte = @-ARCH-@_Python.SS_Tte()
211 __tte_setr__(ss_tte,tte.r)
212 __tte_setvalid__(ss_tte,tte.valid)
213 __tte_setctx__(ss_tte,tte.ctx)
214 __tte_setpid__(ss_tte,tte.pid)
215 __tte_settag__(ss_tte,tte.tag)
216 __tte_setsize__(ss_tte,tte.size)
217 __tte_setie__(ss_tte,tte.ie)
218 __tte_setnfo__(ss_tte,tte.nfo)
219 __tte_setx__(ss_tte,tte.x)
220 __tte_setp__(ss_tte,tte.p)
221 __tte_setw__(ss_tte,tte.w)
222 __tte_setaddr__(ss_tte,tte.addr)
223 self.__tlb__.insert(ss_tte)
224 else:
225 raise TypeError
226
227
228class Core(Pfe_Model.Core):
229 def __init__(self,core,ref):
230 Pfe_Model.Core.__init__(self)
231 self.inst_tlb = Tlb(core.inst_tlb)
232 self.data_tlb = Tlb(core.data_tlb)
233 for i in range(0,core.strand_cnt()):
234 strand_ref = 's'+str(i)
235 strand_ptr = core.strand_ptr(i)
236 strand = SS_Strand.Strand(strand_ptr,ref+'.'+strand_ref,@-ARCH-@_Python)
237 self.__dict__[strand_ref] = strand
238 self.s.append(strand)
239 strand.__dict__['inst_tlb'] = self.inst_tlb
240 strand.__dict__['data_tlb'] = self.data_tlb
241
242
243class Cpu(Pfe_Model.Cpu):
244 def __init__(self,cpu,ref):
245 Pfe_Model.Cpu.__init__(self)
246 self.hard_reset = cpu.hard_reset
247 for i in range(0,cpu.core_cnt()):
248 core_ref = 'c'+str(i)
249 core_ptr = cpu.core_ptr(i)
250 core = Core(core_ptr,ref+'.'+core_ref)
251 self.__dict__[core_ref] = core
252 self.c.append(core)
253
254
255class Model(Pfe_Model.Model):
256 def __init__(self,mem,io,model=None):
257 Pfe_Model.Model.__init__(self)
258 self.mem = mem
259 self.io = io
260 self.__model__ = model
261 mem.__flush__ = model.flush
262 if model:
263 for i in range(0,model.cpu_cnt()):
264 cpu_ref = 'p'+str(i)
265 cpu_ptr = model.cpu_ptr(i)
266 cpu = Cpu(cpu_ptr,cpu_ref)
267 self.p.append(cpu)
268 self.__dict__[cpu_ref] = cpu
269 self.__populate__()
270
271 def __create_cpu__(self,count,cpu_lst=[]):
272 for i in range(0,count):
273 cpu_ref = 'p'+str(i)
274 if i < len(cpu_lst):
275 cpu_ptr = cpu_lst[i]
276 else:
277 cpu_ptr = @-ARCH-@_Python.@-ARCH-VF-@_Cpu(cpu_ref)
278 cpu = Cpu(cpu_ptr,cpu_ref)
279 self.p.append(cpu)
280 self.__dict__[cpu_ref] = cpu
281 self.__populate__()
282 return True
283
284 def ras_enable(self,cmd=''):
285 return self.__model__.ras_enable(cmd)
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.