projects / OpenSPARC-T2-SAM / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / pli / bin / SS_RegCompare.cc
CommitLineData
920dae64
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: SS_RegCompare.cc
4// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6//
7// The above named program is free software; you can redistribute it and/or
8// modify it under the terms of the GNU General Public
9// License version 2 as published by the Free Software Foundation.
10//
11// The above named program is distributed in the hope that it will be
12// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14// General Public License for more details.
15//
16// You should have received a copy of the GNU General Public
17// License along with this work; if not, write to the Free Software
18// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19//
20// ========== Copyright Header End ============================================
21//
22// @-ARCH-@_RegCompare.cc is automatically generated from
23// ss/api/pli/bin/Bl_RegCompare.cc, do not modify @-ARCH-@_RegCompare.cc
24// make necessary changes in ss/api/pli/bin/Bl_RegCompare.cc instead.
25//
26#include "@-ARCH-@_RegCompare.h"
27
28using namespace std;
29
30@-ARCH-@_RegCompare::@-ARCH-@_RegCompare( @-ARCH-VF-@_Strand* _strand, SS_PliSocket* _socket )/*{{{*/
31 :
32 SS_RegCompare(_strand,_socket),
33 strand(_strand)
34{}
35/*}}}*/
36
37void @-ARCH-@_RegCompare::initialise()/*{{{*/
38{
39 uint_t id = strand->strand_id();
40
41 SS_RegCompare::initialise();
42
43 for (RegId* c = reg_list; *c; c++)
44 {
45 RegId ci = *c;
46 uint64_t new_val = get(ci);
47
48 if (ci == CTR_FSR)
49 new_val &= ~uint64_t(0x2000);
50 else if (ci == CTR_HPSTATE)
51 new_val &= ~uint64_t(0x800);
52
53 ctr[ci] = new_val;
54 }
55}
56/*}}}*/
57void @-ARCH-@_RegCompare::compare( uint32_t opc )/*{{{*/
58{
59 char cmp[64];
60 uint_t id = strand->strand_id();
61
62 SS_RegCompare::compare();
63
64 for (RegId* c = reg_list; *c; c++)
65 {
66 RegId ci = *c;
67 uint64_t old_val = ctr[ci];
68 uint64_t new_val = get(ci);
69
70 if (ci == CTR_FSR)
71 new_val &= ~uint64_t(0x2000);
72 else if (ci == CTR_HPSTATE)
73 new_val &= ~uint64_t(0x800);
74
75 if (new_val != old_val)
76 {
77 if (cmpr_list[ci])
78 {
79 new_delta = true;
80 sprintf(cmp,"STEP: %d C %d %016llx ",id,ci,new_val);
81 socket->write(cmp);
82 }
83 ctr[ci] = new_val;
84 }
85 }
86
87 if (cmpr_list[SS_RegCompare::CTR_OPCODE])
88 {
89 new_delta = true;
90 sprintf(cmp,"STEP: %d C 255 %08x ",id,opc);
91 socket->write(cmp);
92 }
93 if (new_delta)
94 {
95 sprintf(cmp,"\n");
96 socket->write(cmp);
97 socket->flush();
98 }
99}
100/*}}}*/
101
102void @-ARCH-@_RegCompare::dump_regs()/*{{{*/
103{
104 SS_RegCompare::dump_regs();
105
106 int dumplist[] =
107 {
108 CTR_PC, CTR_NPC, CTR_CWP, CTR_CCR,
109 CTR_FPRS, CTR_FSR, CTR_PSTATE, CTR_HPSTATE,
110 CTR_ASI, CTR_TICK, CTR_TL, CTR_PIL,
111 CTR_CANSAVE, CTR_CANRESTORE, CTR_CLEANWIN, CTR_OTHERWIN,
112 CTR_HVER, CTR_WSTATE, CTR_GL, CTR_TBA,
113 CTR_HTBA, CTR_TICK_CMPR, CTR_STICK_CMPR, CTR_HSTICK_CMPR,
114 CTR_HINTP, CTR_SOFTINT, CTR_GSR, CTR_INTR_RECV,
115 CTR_TPC1, CTR_TNPC1, CTR_TSTATE1, CTR_TT1,
116 CTR_TPC2, CTR_TNPC2, CTR_TSTATE2, CTR_TT2,
117 CTR_TPC3, CTR_TNPC3, CTR_TSTATE3, CTR_TT3,
118 CTR_TPC4, CTR_TNPC4, CTR_TSTATE4, CTR_TT4,
119 CTR_TPC5, CTR_TNPC5, CTR_TSTATE5, CTR_TT5,
120 CTR_TPC6, CTR_TNPC6, CTR_TSTATE6, CTR_TT6,
121 CTR_HTSTATE1, CTR_HTSTATE2, CTR_HTSTATE3, CTR_HTSTATE4,
122 CTR_HTSTATE5, CTR_HTSTATE6, CTR_LSU_CONTROL, CTR_DWATCHPOINT_ADDR,
123 CTR_CTXT_PRIM_0, CTR_CTXT_SEC_0, CTR_CTXT_PRIM_1, CTR_CTXT_SEC_1,
124 CTR_I_TAG_ACC, CTR_D_TAG_ACC, CTR_D_SFAR, CTR_CTXT_Z_TSB_CFG0,
125 CTR_CTXT_Z_TSB_CFG1, CTR_CTXT_Z_TSB_CFG2, CTR_CTXT_Z_TSB_CFG3, CTR_CTXT_NZ_TSB_CFG0,
126 CTR_CTXT_NZ_TSB_CFG1, CTR_CTXT_NZ_TSB_CFG2, CTR_CTXT_NZ_TSB_CFG3
127 };
128 int size = sizeof(dumplist)/sizeof(dumplist[0]);
129
130 int i = 0;
131 while (i < size)
132 {
133 // title
134 int ii = i;
135 fprintf(stdout, " ");
136 for (int j = 0; j < 4 && ii < size; j++)
137 {
138 fprintf(stdout, " %16s", reg_name[dumplist[ii]]);
139 ii++;
140 }
141 fprintf(stdout, "\n");
142 // value
143 ii = i;
144 fprintf(stdout, " ");
145 for (int j = 0; j < 4 && ii < size; j++)
146 {
147 fprintf(stdout, " %016llx", get((RegId)dumplist[ii]));
148 ii++;
149 }
150 fprintf(stdout, "\n");
151 i = ii;
152 }
153}
154/*}}}*/
155
156uint64_t @-ARCH-@_RegCompare::get( RegId id )/*{{{*/
157{
158 // Internal we keep the pc, npc, tpc, and tnpc values
159 // at 64 bits for detecting cases where we fall into the va-hole.
160 // However, @-ARCH-@ "externally" only implements 48 bits (well 46)
161 // of the address, so when we read those pc values we sign extend
162 // the 48 bit value to 64 bit.
163
164 uint_t sft;
165 uint64_t value = 0;
166
167 switch (id)
168 {
169 case CTR_PC:
170 sft = 64 - strand->va_bits();
171 value = (SS_Vaddr(strand->pc()) << sft) >> sft;
172 break;
173 case CTR_NPC:
174 sft = 64 - strand->va_bits();
175 value = (SS_Vaddr(strand->npc()) << sft) >> sft;
176 break;
177 case CTR_Y:
178 value = strand->y();
179 break;
180 case CTR_CCR:
181 value = strand->ccr();
182 break;
183 case CTR_FPRS:
184 value = strand->fprs();
185 break;
186 case CTR_FSR:
187 strand->get_fsr();
188 value = strand->fsr();
189 break;
190 case CTR_ASI:
191 value = strand->asi();
192 break;
193 case CTR_GSR:
194 value = strand->gsr();
195 break;
196 case CTR_TICK_CMPR:
197 value = strand->tick_cmpr();
198 break;
199 case CTR_STICK_CMPR:
200 value = strand->stick_cmpr();
201 break;
202 case CTR_PSTATE:
203 value = strand->pstate();
204 break;
205 case CTR_TL:
206 value = strand->tl();
207 break;
208 case CTR_PIL:
209 value = strand->pil();
210 break;
211 case CTR_TPC1:
212 sft = 64 - strand->va_bits();
213 value = (SS_Vaddr(strand->trap_state[1].pc) << sft) >> sft;
214 break;
215 case CTR_TPC2:
216 sft = 64 - strand->va_bits();
217 value = (SS_Vaddr(strand->trap_state[2].pc) << sft) >> sft;
218 break;
219 case CTR_TPC3:
220 sft = 64 - strand->va_bits();
221 value = (SS_Vaddr(strand->trap_state[3].pc) << sft) >> sft;
222 break;
223 case CTR_TPC4:
224 sft = 64 - strand->va_bits();
225 value = (SS_Vaddr(strand->trap_state[4].pc) << sft) >> sft;
226 break;
227 case CTR_TPC5:
228 sft = 64 - strand->va_bits();
229 value = (SS_Vaddr(strand->trap_state[5].pc) << sft) >> sft;
230 break;
231 case CTR_TPC6:
232 sft = 64 - strand->va_bits();
233 value = (SS_Vaddr(strand->trap_state[6].pc) << sft) >> sft;
234 break;
235 case CTR_TNPC1:
236 sft = 64 - strand->va_bits();
237 value = (SS_Vaddr(strand->trap_state[1].npc) << sft) >> sft;
238 break;
239 case CTR_TNPC2:
240 sft = 64 - strand->va_bits();
241 value = (SS_Vaddr(strand->trap_state[2].npc) << sft) >> sft;
242 break;
243 case CTR_TNPC3:
244 sft = 64 - strand->va_bits();
245 value = (SS_Vaddr(strand->trap_state[3].npc) << sft) >> sft;
246 break;
247 case CTR_TNPC4:
248 sft = 64 - strand->va_bits();
249 value = (SS_Vaddr(strand->trap_state[4].npc) << sft) >> sft;
250 break;
251 case CTR_TNPC5:
252 sft = 64 - strand->va_bits();
253 value = (SS_Vaddr(strand->trap_state[5].npc) << sft) >> sft;
254 break;
255 case CTR_TNPC6:
256 sft = 64 - strand->va_bits();
257 value = (SS_Vaddr(strand->trap_state[6].npc) << sft) >> sft;
258 break;
259 case CTR_TSTATE1:
260 value = strand->trap_state[1].tstate;
261 break;
262 case CTR_TSTATE2:
263 value = strand->trap_state[2].tstate;
264 break;
265 case CTR_TSTATE3:
266 value = strand->trap_state[3].tstate;
267 break;
268 case CTR_TSTATE4:
269 value = strand->trap_state[4].tstate;
270 break;
271 case CTR_TSTATE5:
272 value = strand->trap_state[5].tstate;
273 break;
274 case CTR_TSTATE6:
275 value = strand->trap_state[6].tstate;
276 break;
277 case CTR_TT1:
278 value = strand->trap_state[1].tt;
279 break;
280 case CTR_TT2:
281 value = strand->trap_state[2].tt;
282 break;
283 case CTR_TT3:
284 value = strand->trap_state[3].tt;
285 break;
286 case CTR_TT4:
287 value = strand->trap_state[4].tt;
288 break;
289 case CTR_TT5:
290 value = strand->trap_state[5].tt;
291 break;
292 case CTR_TT6:
293 value = strand->trap_state[6].tt;
294 break;
295 case CTR_TBA:
296 value = strand->tba();
297 break;
298 case CTR_HVER:
299 value = strand->hver();
300 break;
301 case CTR_CWP:
302 value = strand->cwp();
303 break;
304 case CTR_CANSAVE:
305 value = strand->cansave();
306 break;
307 case CTR_CANRESTORE:
308 value = strand->canrestore();
309 break;
310 case CTR_OTHERWIN:
311 value = strand->otherwin();
312 break;
313 case CTR_WSTATE:
314 value = strand->wstate();
315 break;
316 case CTR_CLEANWIN:
317 value = strand->cleanwin();
318 break;
319 case CTR_SOFTINT:
320 value = strand->softint();
321 break;
322 case CTR_INTR_RECV:
323 value = strand->intr_recv;
324 break;
325 case CTR_GL:
326 value = strand->gl();
327 break;
328 case CTR_HPSTATE:
329 value = strand->hpstate();
330 break;
331 case CTR_HTSTATE1:
332 value = strand->trap_state[1].htstate;
333 break;
334 case CTR_HTSTATE2:
335 value = strand->trap_state[2].htstate;
336 break;
337 case CTR_HTSTATE3:
338 value = strand->trap_state[3].htstate;
339 break;
340 case CTR_HTSTATE4:
341 value = strand->trap_state[4].htstate;
342 break;
343 case CTR_HTSTATE5:
344 value = strand->trap_state[5].htstate;
345 break;
346 case CTR_HTSTATE6:
347 value = strand->trap_state[6].htstate;
348 break;
349 case CTR_HTBA:
350 value = strand->htba();
351 break;
352 case CTR_HINTP:
353 value = strand->hintp();
354 break;
355 case CTR_HSTICK_CMPR:
356 value = strand->hstick_cmpr();
357 break;
358 case CTR_D_SFAR:
359 value = strand->data_sfar();
360 break;
361 case CTR_CTXT_PRIM_0:
362 value = strand->primary_context[0]();
363 break;
364 case CTR_CTXT_SEC_0:
365 value = strand->secondary_context[0]();
366 break;
367 case CTR_CTXT_PRIM_1:
368 value = strand->primary_context[1]();
369 break;
370 case CTR_CTXT_SEC_1:
371 value = strand->secondary_context[1]();
372 break;
373 case CTR_LSU_CONTROL:
374 value = strand->lsu_ctr();
375 break;
376 case CTR_I_TAG_ACC:
377 value = strand->inst_tag_access();
378 break;
379 case CTR_CTXT_Z_TSB_CFG0:
380 value = strand->nucleus_tsb_config[0]();
381 break;
382 case CTR_CTXT_Z_TSB_CFG1:
383 value = strand->nucleus_tsb_config[1]();
384 break;
385 case CTR_CTXT_Z_TSB_CFG2:
386 value = strand->nucleus_tsb_config[2]();
387 break;
388 case CTR_CTXT_Z_TSB_CFG3:
389 value = strand->nucleus_tsb_config[3]();
390 break;
391 case CTR_CTXT_NZ_TSB_CFG0:
392 value = strand->non_nucleus_tsb_config[0]();
393 break;
394 case CTR_CTXT_NZ_TSB_CFG1:
395 value = strand->non_nucleus_tsb_config[1]();
396 break;
397 case CTR_CTXT_NZ_TSB_CFG2:
398 value = strand->non_nucleus_tsb_config[2]();
399 break;
400 case CTR_CTXT_NZ_TSB_CFG3:
401 value = strand->non_nucleus_tsb_config[3]();
402 break;
403 case CTR_D_TAG_ACC:
404 value = strand->data_tag_access();
405 break;
406 case CTR_DWATCHPOINT_ADDR:
407 value = strand->data_wp();
408 break;
409 default:
410 value = 0;
411 break;
412 }
413
414 return value;
415}
416/*}}}*/
417
418int @-ARCH-@_RegCompare::name_2_index( string name )/*{{{*/
419{
420 if (name == "G")
421 return SS_RegCompare::CTR_G;
422 else if (name == "W")
423 return SS_RegCompare::CTR_W;
424 else if (name == "F")
425 return SS_RegCompare::CTR_F;
426 else if (name == "INSTR")
427 return SS_RegCompare::CTR_INSTR;
428 else if (name == "OPCODE")
429 return SS_RegCompare::CTR_OPCODE;
430 else
431 {
432 int ii = -1;
433 for (int i = CTR_PC; i < CTR_TOTAL; i++)
434 if (reg_name[i] == name)
435 return i;
436 // no match, this is an error
437 fprintf(stdout, "ERROR: name_2_index(): no match for %s\n", name.c_str());
438 return -1;
439 }
440}
441/*}}}*/
442
443@-ARCH-@_RegCompare::RegId @-ARCH-@_RegCompare::reg_list[] =/*{{{*/
444{
445 @-ARCH-@_RegCompare::CTR_PC
446, @-ARCH-@_RegCompare::CTR_NPC
447, @-ARCH-@_RegCompare::CTR_Y
448, @-ARCH-@_RegCompare::CTR_CCR
449, @-ARCH-@_RegCompare::CTR_FPRS
450, @-ARCH-@_RegCompare::CTR_FSR
451, @-ARCH-@_RegCompare::CTR_ASI
452, @-ARCH-@_RegCompare::CTR_GSR
453, @-ARCH-@_RegCompare::CTR_TICK_CMPR
454, @-ARCH-@_RegCompare::CTR_STICK_CMPR
455, @-ARCH-@_RegCompare::CTR_PSTATE
456, @-ARCH-@_RegCompare::CTR_TL
457, @-ARCH-@_RegCompare::CTR_PIL
458, @-ARCH-@_RegCompare::CTR_TPC1
459, @-ARCH-@_RegCompare::CTR_TPC2
460, @-ARCH-@_RegCompare::CTR_TPC3
461, @-ARCH-@_RegCompare::CTR_TPC4
462, @-ARCH-@_RegCompare::CTR_TPC5
463, @-ARCH-@_RegCompare::CTR_TPC6
464, @-ARCH-@_RegCompare::CTR_TNPC1
465, @-ARCH-@_RegCompare::CTR_TNPC2
466, @-ARCH-@_RegCompare::CTR_TNPC3
467, @-ARCH-@_RegCompare::CTR_TNPC4
468, @-ARCH-@_RegCompare::CTR_TNPC5
469, @-ARCH-@_RegCompare::CTR_TNPC6
470, @-ARCH-@_RegCompare::CTR_TSTATE1
471, @-ARCH-@_RegCompare::CTR_TSTATE2
472, @-ARCH-@_RegCompare::CTR_TSTATE3
473, @-ARCH-@_RegCompare::CTR_TSTATE4
474, @-ARCH-@_RegCompare::CTR_TSTATE5
475, @-ARCH-@_RegCompare::CTR_TSTATE6
476, @-ARCH-@_RegCompare::CTR_TT1
477, @-ARCH-@_RegCompare::CTR_TT2
478, @-ARCH-@_RegCompare::CTR_TT3
479, @-ARCH-@_RegCompare::CTR_TT4
480, @-ARCH-@_RegCompare::CTR_TT5
481, @-ARCH-@_RegCompare::CTR_TT6
482, @-ARCH-@_RegCompare::CTR_TBA
483, @-ARCH-@_RegCompare::CTR_HVER
484, @-ARCH-@_RegCompare::CTR_CWP
485, @-ARCH-@_RegCompare::CTR_CANSAVE
486, @-ARCH-@_RegCompare::CTR_CANRESTORE
487, @-ARCH-@_RegCompare::CTR_OTHERWIN
488, @-ARCH-@_RegCompare::CTR_WSTATE
489, @-ARCH-@_RegCompare::CTR_CLEANWIN
490, @-ARCH-@_RegCompare::CTR_SOFTINT
491, @-ARCH-@_RegCompare::CTR_INTR_RECV
492, @-ARCH-@_RegCompare::CTR_GL
493, @-ARCH-@_RegCompare::CTR_HPSTATE
494, @-ARCH-@_RegCompare::CTR_HTSTATE1
495, @-ARCH-@_RegCompare::CTR_HTSTATE2
496, @-ARCH-@_RegCompare::CTR_HTSTATE3
497, @-ARCH-@_RegCompare::CTR_HTSTATE4
498, @-ARCH-@_RegCompare::CTR_HTSTATE5
499, @-ARCH-@_RegCompare::CTR_HTSTATE6
500, @-ARCH-@_RegCompare::CTR_HTBA
501, @-ARCH-@_RegCompare::CTR_HINTP
502, @-ARCH-@_RegCompare::CTR_HSTICK_CMPR
503, @-ARCH-@_RegCompare::CTR_D_SFAR // ToDo is this used or not?
504, @-ARCH-@_RegCompare::CTR_CTXT_PRIM_0
505, @-ARCH-@_RegCompare::CTR_CTXT_SEC_0
506, @-ARCH-@_RegCompare::CTR_CTXT_PRIM_1
507, @-ARCH-@_RegCompare::CTR_CTXT_SEC_1
508, @-ARCH-@_RegCompare::CTR_LSU_CONTROL
509, @-ARCH-@_RegCompare::CTR_I_TAG_ACC
510, @-ARCH-@_RegCompare::CTR_CTXT_Z_TSB_CFG0
511, @-ARCH-@_RegCompare::CTR_CTXT_Z_TSB_CFG1
512, @-ARCH-@_RegCompare::CTR_CTXT_Z_TSB_CFG2
513, @-ARCH-@_RegCompare::CTR_CTXT_Z_TSB_CFG3
514, @-ARCH-@_RegCompare::CTR_CTXT_NZ_TSB_CFG0
515, @-ARCH-@_RegCompare::CTR_CTXT_NZ_TSB_CFG1
516, @-ARCH-@_RegCompare::CTR_CTXT_NZ_TSB_CFG2
517, @-ARCH-@_RegCompare::CTR_CTXT_NZ_TSB_CFG3
518, @-ARCH-@_RegCompare::CTR_D_TAG_ACC
519, @-ARCH-@_RegCompare::CTR_DWATCHPOINT_ADDR
520, @-ARCH-@_RegCompare::RegId(0)
521};
522/*}}}*/
523
524const char* @-ARCH-@_RegCompare::reg_name[] = /*{{{*/
525{
526 "G0", // 0
527 "G1", // 1
528 "G2", // 2
529 "G3", // 3
530 "G4", // 4
531 "G5", // 5
532 "G6", // 6
533 "G7", // 7
534 "O0", // 8
535 "O1", // 9
536 "O2", // 10
537 "O3", // 11
538 "O4", // 12
539 "O5", // 13
540 "O6", // 14
541 "O7", // 15
542 "L0", // 16
543 "L1", // 17
544 "L2", // 18
545 "L3", // 19
546 "L4", // 20
547 "L5", // 21
548 "L6", // 22
549 "L7", // 23
550 "I0", // 24
551 "I1", // 25
552 "I2", // 26
553 "I3", // 27
554 "I4", // 28
555 "I5", // 29
556 "I6", // 30
557 "I7", // 31
558 "PC", // 32
559 "NPC", // 33
560 "Y", // 34
561 "CCR", // 35
562 "FPRS", // 36
563 "FSR", // 37
564 "ASI", // 38
565 "TICK", // 39
566 "GSR", // 40
567 "TICK_CMPR", // 41
568 "STICK", // 42
569 "STICK_CMPR", // 43
570 "PSTATE", // 44
571 "TL", // 45
572 "PIL", // 46
573 "TPC1", // 47
574 "TPC2", // 48
575 "TPC3", // 49
576 "TPC4", // 50
577 "TPC5", // 51
578 "TPC6", // 52
579 "?TPC7?", // 53
580 "?TPC8?", // 54
581 "?TPC9?", // 55
582 "?TPC10?", // 56
583 "TNPC1", // 57
584 "TNPC2", // 58
585 "TNPC3", // 59
586 "TNPC4", // 60
587 "TNPC5", // 61
588 "TNPC6", // 62
589 "?TNPC7?", // 63
590 "?TNPC8?", // 64
591 "?TNPC9?", // 65
592 "?TNPC10?", // 66
593 "TSTATE1", // 67
594 "TSTATE2", // 68
595 "TSTATE3", // 69
596 "TSTATE4", // 70
597 "TSTATE5", // 71
598 "TSTATE6", // 72
599 "?TSTATE7?", // 73
600 "?TSTATE8?", // 74
601 "?TSTATE9?", // 75
602 "?TSTATE10?", // 76
603 "TT1", // 77
604 "TT2", // 78
605 "TT3", // 79
606 "TT4", // 80
607 "TT5", // 81
608 "TT6", // 82
609 "?TT7?", // 83
610 "?TT8?", // 84
611 "?TT9?", // 85
612 "?TT10?", // 86
613 "TBA", // 87
614 "VER", // 88
615 "CWP", // 89
616 "CANSAVE", // 90
617 "CANRESTORE", // 91
618 "OTHERWIN", // 92
619 "WSTATE", // 93
620 "CLEANWIN", // 94
621 "SOFTINT", // 95
622 "ECACHE_error_ENABLE", // 96
623 "ASYNCHRONOUS_FAULT_STATUS", // 97
624 "ASYNCHRONOUS_FAULT_ADDRESS", // 98
625 "OUT_INTR_DATA0", // 99
626 "OUT_INTR_DATA1", // 100
627 "OUT_INTR_DATA2", // 101
628 "INTR_DISPATCH_STATUS", // 102
629 "IN_INTR_DATA0", // 103
630 "IN_INTR_DATA1", // 104
631 "IN_INTR_DATA2", // 105
632 "INTR_RECV", // 106
633 "GL", // 107
634 "HPSTATE", // 108
635 "HTSTATE1", // 109
636 "HTSTATE2", // 110
637 "HTSTATE3", // 111
638 "HTSTATE4", // 112
639 "HTSTATE5", // 113
640 "HTSTATE6", // 114
641 "HTSTATE7", // 115
642 "HTSTATE8", // 116
643 "HTSTATE9", // 117
644 "HTSTATE10", // 118
645 "HTBA", // 119
646 "HINTP", // 120
647 "HSTICK_CMPR", // 121
648 "MID", // 122
649 "I_SFSR", // 123
650 "D_SFSR", // 124
651 "D_SFAR", // 125
652 "CTXT_PRIM_0", // 126
653 "CTXT_SEC_0", // 127
654 "CTXT_PRIM_1", // 128
655 "CTXT_SEC_1", // 129
656 "LSU_CONTROL", // 130
657 "I_TAG_ACC", // 131
658 "CTXT_Z_TSB_CFG0", // 132
659 "CTXT_Z_TSB_CFG1", // 133
660 "CTXT_Z_TSB_CFG2", // 134
661 "CTXT_Z_TSB_CFG3", // 135
662 "CTXT_NZ_TSB_CFG0", // 136
663 "CTXT_NZ_TSB_CFG1", // 137
664 "CTXT_NZ_TSB_CFG2", // 138
665 "CTXT_NZ_TSB_CFG3", // 139
666 "I_DATA_IN", // 140
667 "D_TAG_ACC", // 141
668 "DWATCHPOINT_ADDR", // 142
669 "D_DATA_IN", // 143
670 "I_TAG_TARGET", // 144
671 "D_TAG_TARGET", // 145
672 "I_TSB_PTR0", // 146
673 "I_TSB_PTR1", // 147
674 "I_TSB_PTR2", // 148
675 "I_TSB_PTR3", // 149
676 "D_TSB_PTR0", // 150
677 "D_TSB_PTR1", // 151
678 "D_TSB_PTR2", // 152
679 "D_TSB_PTR3", // 153
680 "I_MASK_0", // 154
681 "I_MASK_1", // 155
682 "I_WATCHPOINT_0", // 156
683 "I_WATCHPOINT_1", // 157
684 "SPU_CWQ_CSR", // 158
685 "SPU_CWQ_SYNC", // 159
686};
687/*}}}*/
688
689
690
691
692
693
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.