Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / pli / src / SS_ValSync.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: SS_ValSync.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================

#include "SS_ValSync.h"

SS_ValSync::SS_ValSync( SS_Strand* _strand )/*{{{*/
 : 
  strand(_strand)
{
  strand->asi_map.set_asi_read(&asi_rd);
  strand->ctr_sync = &ctr_rd;
  for (int i = 0; i < SS_Asi::MAX; i++)
    multi_entry[i] = false;
}
/*}}}*/

void SS_ValSync::ctr_read( SS_Registers::Index idx, uint64_t data )/*{{{*/
{
  // We only allow a subset of registers to have "follow me" value syncing
  assert(SS_Registers::is_asr(idx) || SS_Registers::is_pr(idx) || SS_Registers::is_hpr(idx));
  ctr_rd[idx] = data;
}
/*}}}*/
void SS_ValSync::ctr_write( SS_Registers::Index idx, uint64_t data )/*{{{*/
{
  // We only allow a subset of registers to have "follow me" value syncing
  assert(SS_Registers::is_asr(idx) || SS_Registers::is_pr(idx) || SS_Registers::is_hpr(idx));
  (strand->set_state)(strand,idx,data);
}
/*}}}*/

void SS_ValSync::asi_read( uint8_t asi, SS_Vaddr va, uint64_t data )/*{{{*/
{
  // Mask va into the valid range so we can actually find value sync info.
  va &= strand->asi_map[asi].get_mask();
  std::map<SS_Vaddr,std::list<uint64_t>*>::iterator i = asi_rd[asi].find(va);
  if (i == asi_rd[asi].end()) 
  {
    // no list is created to this asi/va yet, do that first
    asi_rd[asi][va] = new std::list<uint64_t>;
  }
  if (multi_entry[asi])
  {
    // these asi's need multi-entry support, so just add the new follow-me
    // value to the end of the queue, they will be used in FIFO order.
    asi_rd[asi][va]->push_back(data);
  }
  else
  {
    // other asi's use single-entry, so make sure there will be only one entry
    // in the queue.
    asi_rd[asi][va]->clear();
    asi_rd[asi][va]->push_back(data);
  }
}
/*}}}*/
void SS_ValSync::asi_write( uint8_t asi, SS_Vaddr va, uint64_t data )/*{{{*/
{
  // Mask va into the valid range so we can actually find value sync info.
  va &= strand->asi_map[asi].get_mask();
  strand->asi_map.wr64(strand,asi,va,data);
}
/*}}}*/

void SS_ValSync::csr_read( SS_Paddr pa, uint64_t data, bool little_endian )/*{{{*/
{
  csr_rd[pa] = data;
}
/*}}}*/
void SS_ValSync::csr_write( SS_Paddr pa, uint64_t data, bool little_endian )/*{{{*/
{
}
/*}}}*/