[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / pli / tst / diag.conf

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: diag.conf
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: diag.conf
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
OBJECT sim TYPE sim {
        cpu_switch_time: 1
        time_model: "on"
        continue_disabled: 0

        instruction_profile_mode: instruction-cache-access-trace
        instruction_profile_line_size: 4

}
OBJECT memory_ciop TYPE ram {
        image: memory_ciop_image
}
OBJECT memory_ciop_image TYPE image {
        size: 0x7f00000000
        queue: th00
}
OBJECT swvmem0 TYPE swerver-memory {

        irq: irq0


        snoop: 0


        tso_checker: 1
        debug_level: 0

        queue: th00
}


OBJECT irqbus0 TYPE sparc-irq-bus {
}


OBJECT irq0 TYPE swerver-interrupt {
        thread_base: 0
        need_ssi: 1
        queue: th00
}


OBJECT swvp0 TYPE swerver-processor {
        thread0: th00
        thread1: th01
        thread2: th02
        thread3: th03
        thread4: th04
        thread5: th05
        thread6: th06
        thread7: th07
        mmu:swmmu0
}
OBJECT swmmu0 TYPE swerver-proc-mmu {
}

OBJECT th00 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu00
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 0))
        irq_bus: irqbus0
        thread_id: 0
        other_threads: (th01, th02, th03, th04, th05, th06, th07)
        queue: th00

        extra_irq_enable: 0

}

OBJECT stmmu00 TYPE swerver-thread-mmu {
        thread-status: 1
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        intr_trap_type: 0x60
        stream_cmpl_trap_type: 0x70
        ma_cmpl_trap_type: 0x74
        model-real-sfar: 1


        ignore_asi_0x73: 1
        match_rtl: 1


}

OBJECT th01 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu01
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 1))
        irq_bus: irqbus0
        queue: th01
        thread_id: 1
        other_threads: (
                        th00,
                        th02,
                        th03,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu01 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th02 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu02
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 2))
        irq_bus: irqbus0
        queue: th02
        thread_id: 2
        other_threads: (
                        th00,
                        th01,
                        th03,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu02 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th03 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu03
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 3))
        irq_bus: irqbus0
        queue: th03
        thread_id: 3
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu03 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th04 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu04
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 4))
        irq_bus: irqbus0
        queue: th04
        thread_id: 4
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu04 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th05 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu05
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 5))
        irq_bus: irqbus0
        queue: th05
        thread_id: 5
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu05 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th06 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu06
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 6))
        irq_bus: irqbus0
        queue: th06
        thread_id: 6
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th05,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu06 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th07 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu07
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 7))
        irq_bus: irqbus0
        queue: th07
        thread_id: 7
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th05,
                        th06
                       )

        extra_irq_enable: 0

}

OBJECT stmmu07 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT phys_mem0 TYPE memory-space {
        map: (
              (0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
              (0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),

              (0x0ff00000000, memory0, 0x0, 0, 0x100000000))


        timing_model: swvmem0
        snoop_device: swvmem0

}

OBJECT memory0 TYPE ram {
        image: memory0_image
}

OBJECT memory0_image TYPE image {
        size: 0x100000000
        queue: th00
}

OBJECT memory_cache TYPE ram {
        image: memory_cache_image
}

OBJECT memory_cache_image TYPE image {
        size: 0x2000000000
        queue: th00
}


OBJECT socket0 TYPE pli-socket {

        force_pc: 1


        int_model: 1


        mem_model: 1


        cmd_intf: 1


        replay_log: 0
        socket: 13028
        open: 1


        close: 0
        test: 0


        pli_log: 0


        reg_cmp: 1


        debug_level: 1


        tlb_sync: 1


        tlb_debug: 0
        show_trap: 0


        enable_ras: 0

}
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: diag.conf
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	// ========== Copyright Header Begin ==========================================
	24	//
	25	// OpenSPARC T2 Processor File: diag.conf
	26	// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	27	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	28	//
	29	// The above named program is free software; you can redistribute it and/or
	30	// modify it under the terms of the GNU General Public
	31	// License version 2 as published by the Free Software Foundation.
	32	//
	33	// The above named program is distributed in the hope that it will be
	34	// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	35	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	36	// General Public License for more details.
	37	//
	38	// You should have received a copy of the GNU General Public
	39	// License along with this work; if not, write to the Free Software
	40	// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	41	//
	42	// ========== Copyright Header End ============================================
	43	OBJECT sim TYPE sim {
	44	cpu_switch_time: 1
	45	time_model: "on"
	46	continue_disabled: 0
	47
	48	instruction_profile_mode: instruction-cache-access-trace
	49	instruction_profile_line_size: 4
	50
	51	}
	52	OBJECT memory_ciop TYPE ram {
	53	image: memory_ciop_image
	54	}
	55	OBJECT memory_ciop_image TYPE image {
	56	size: 0x7f00000000
	57	queue: th00
	58	}
	59	OBJECT swvmem0 TYPE swerver-memory {
	60
	61	irq: irq0
	62
	63
	64	snoop: 0
65
66
67
68
69	tso_checker: 1
70	debug_level: 0
71
72	queue: th00
73	}
74
75
76
77
78
79	OBJECT irqbus0 TYPE sparc-irq-bus {
80	}
81
82
83	OBJECT irq0 TYPE swerver-interrupt {
84	thread_base: 0
85	need_ssi: 1
86	queue: th00
87	}
88
89
90
91	OBJECT swvp0 TYPE swerver-processor {
92	thread0: th00
93	thread1: th01
94	thread2: th02
95	thread3: th03
96	thread4: th04
97	thread5: th05
98	thread6: th06
99	thread7: th07
100	mmu:swmmu0
101	}
102	OBJECT swmmu0 TYPE swerver-proc-mmu {
103	}
104
105	OBJECT th00 TYPE niagara2 {
106	freq_mhz: 800
107	mmu: stmmu00
108	max-trap-levels: 6
109	va_bits: 48
110	physical_memory: phys_mem0
111	control_registers: (("mid", 0))
112	irq_bus: irqbus0
113	thread_id: 0
114	other_threads: (th01, th02, th03, th04, th05, th06, th07)
115	queue: th00
116
117	extra_irq_enable: 0
118
119	}
120
121	OBJECT stmmu00 TYPE swerver-thread-mmu {
122	thread-status: 1
123	full-swerver-decode: 1
124	niagara-mmu: 1
125	disable-sun4u-interrupts: 1
126	intr_trap_type: 0x60
127	stream_cmpl_trap_type: 0x70
128	ma_cmpl_trap_type: 0x74
129	model-real-sfar: 1
130
131
132
133
134	ignore_asi_0x73: 1
135	match_rtl: 1
136
137
138
139
140	}
141
142	OBJECT th01 TYPE niagara2 {
143	freq_mhz: 800
144	mmu: stmmu01
145	max-trap-levels: 6
146	va_bits: 48
147	physical_memory: phys_mem0
148	control_registers: (("mid", 1))
149	irq_bus: irqbus0
150	queue: th01
151	thread_id: 1
152	other_threads: (
153	th00,
154	th02,
155	th03,
156	th04,
157	th05,
158	th06,
159	th07
160	)
161
162	extra_irq_enable: 0
163
164	}
165
166	OBJECT stmmu01 TYPE swerver-thread-mmu {
167	full-swerver-decode: 1
168	niagara-mmu: 1
169	disable-sun4u-interrupts: 1
170	model-real-sfar: 1
171	}
172
173	OBJECT th02 TYPE niagara2 {
174	freq_mhz: 800
175	mmu: stmmu02
176	max-trap-levels: 6
177	va_bits: 48
178	physical_memory: phys_mem0
179	control_registers: (("mid", 2))
180	irq_bus: irqbus0
181	queue: th02
182	thread_id: 2
183	other_threads: (
184	th00,
185	th01,
186	th03,
187	th04,
188	th05,
189	th06,
190	th07
191	)
192
193	extra_irq_enable: 0
194
195	}
196
197	OBJECT stmmu02 TYPE swerver-thread-mmu {
198	full-swerver-decode: 1
199	niagara-mmu: 1
200	disable-sun4u-interrupts: 1
201	model-real-sfar: 1
202	}
203
204	OBJECT th03 TYPE niagara2 {
205	freq_mhz: 800
206	mmu: stmmu03
207	max-trap-levels: 6
208	va_bits: 48
209	physical_memory: phys_mem0
210	control_registers: (("mid", 3))
211	irq_bus: irqbus0
212	queue: th03
213	thread_id: 3
214	other_threads: (
215	th00,
216	th01,
217	th02,
218	th04,
219	th05,
220	th06,
221	th07
222	)
223
224	extra_irq_enable: 0
225
226	}
227
228	OBJECT stmmu03 TYPE swerver-thread-mmu {
229	full-swerver-decode: 1
230	niagara-mmu: 1
231	disable-sun4u-interrupts: 1
232	model-real-sfar: 1
233	}
234
235	OBJECT th04 TYPE niagara2 {
236	freq_mhz: 800
237	mmu: stmmu04
238	max-trap-levels: 6
239	va_bits: 48
240	physical_memory: phys_mem0
241	control_registers: (("mid", 4))
242	irq_bus: irqbus0
243	queue: th04
244	thread_id: 4
245	other_threads: (
246	th00,
247	th01,
248	th02,
249	th03,
250	th05,
251	th06,
252	th07
253	)
254
255	extra_irq_enable: 0
256
257	}
258
259	OBJECT stmmu04 TYPE swerver-thread-mmu {
260	full-swerver-decode: 1
261	niagara-mmu: 1
262	disable-sun4u-interrupts: 1
263	model-real-sfar: 1
264	}
265
266	OBJECT th05 TYPE niagara2 {
267	freq_mhz: 800
268	mmu: stmmu05
269	max-trap-levels: 6
270	va_bits: 48
271	physical_memory: phys_mem0
272	control_registers: (("mid", 5))
273	irq_bus: irqbus0
274	queue: th05
275	thread_id: 5
276	other_threads: (
277	th00,
278	th01,
279	th02,
280	th03,
281	th04,
282	th06,
283	th07
284	)
285
286	extra_irq_enable: 0
287
288	}
289
290	OBJECT stmmu05 TYPE swerver-thread-mmu {
291	full-swerver-decode: 1
292	niagara-mmu: 1
293	disable-sun4u-interrupts: 1
294	model-real-sfar: 1
295	}
296
297	OBJECT th06 TYPE niagara2 {
298	freq_mhz: 800
299	mmu: stmmu06
300	max-trap-levels: 6
301	va_bits: 48
302	physical_memory: phys_mem0
303	control_registers: (("mid", 6))
304	irq_bus: irqbus0
305	queue: th06
306	thread_id: 6
307	other_threads: (
308	th00,
309	th01,
310	th02,
311	th03,
312	th04,
313	th05,
314	th07
315	)
316
317	extra_irq_enable: 0
318
319	}
320
321	OBJECT stmmu06 TYPE swerver-thread-mmu {
322	full-swerver-decode: 1
323	niagara-mmu: 1
324	disable-sun4u-interrupts: 1
325	model-real-sfar: 1
326	}
327
328	OBJECT th07 TYPE niagara2 {
329	freq_mhz: 800
330	mmu: stmmu07
331	max-trap-levels: 6
332	va_bits: 48
333	physical_memory: phys_mem0
334	control_registers: (("mid", 7))
335	irq_bus: irqbus0
336	queue: th07
337	thread_id: 7
338	other_threads: (
339	th00,
340	th01,
341	th02,
342	th03,
343	th04,
344	th05,
345	th06
346	)
347
348	extra_irq_enable: 0
349
350	}
351
352	OBJECT stmmu07 TYPE swerver-thread-mmu {
353	full-swerver-decode: 1
354	niagara-mmu: 1
355	disable-sun4u-interrupts: 1
356	model-real-sfar: 1
357	}
358
359	OBJECT phys_mem0 TYPE memory-space {
360	map: (
361	(0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
362	(0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),
363
364	(0x0ff00000000, memory0, 0x0, 0, 0x100000000))
365
366
367
368
369	timing_model: swvmem0
370	snoop_device: swvmem0
371
372	}
373
374	OBJECT memory0 TYPE ram {
375	image: memory0_image
376	}
377
378	OBJECT memory0_image TYPE image {
379	size: 0x100000000
380	queue: th00
381	}
382
383	OBJECT memory_cache TYPE ram {
384	image: memory_cache_image
385	}
386
387	OBJECT memory_cache_image TYPE image {
388	size: 0x2000000000
389	queue: th00
390	}
391
392
393	OBJECT socket0 TYPE pli-socket {
394
395	force_pc: 1
396
397
398
399
400
401	int_model: 1
402
403
404
405
406
407	mem_model: 1
408
409
410
411
412
413
414	cmd_intf: 1
415
416
417
418
419
420
421	replay_log: 0
422	socket: 13028
423	open: 1
424
425
426
427
428
429	close: 0
430	test: 0
431
432
433
434	pli_log: 0
435
436
437
438
439	reg_cmp: 1
440
441
442
443
444
445
446	debug_level: 1
447
448
449	tlb_sync: 1
450
451
452
453
454
455
456	tlb_debug: 0
457	show_trap: 0
458
459
460
461
462	enable_ras: 0
463
464	}