projects / OpenSPARC-T2-SAM / blame
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| 920dae64 AT |
1 | # ========== Copyright Header Begin ========================================== |
| 2 | # | |
| 3 | # OpenSPARC T2 Processor File: SS_Access.py | |
| 4 | # Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 5 | # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 6 | # | |
| 7 | # The above named program is free software; you can redistribute it and/or | |
| 8 | # modify it under the terms of the GNU General Public | |
| 9 | # License version 2 as published by the Free Software Foundation. | |
| 10 | # | |
| 11 | # The above named program is distributed in the hope that it will be | |
| 12 | # useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | # General Public License for more details. | |
| 15 | # | |
| 16 | # You should have received a copy of the GNU General Public | |
| 17 | # License along with this work; if not, write to the Free Software | |
| 18 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 19 | # | |
| 20 | # ========== Copyright Header End ============================================ | |
| 21 | ||
| 22 | ||
| 23 | class SS_Access: | |
| 24 | def __init__(self,mode): | |
| 25 | self.mode = mode | |
| 26 | ||
| 27 | ILL_INST = 'i' # Read or write causes ILLEGAL_INSTRUCTION trap | |
| 28 | PRIV_OPC = 'p' # Read or write causes PRIVILEGED_OPCODE trap | |
| 29 | OK = '-' # Read or write is OK | |
| 30 | ||
| 31 | USER_WRITE = 5 | |
| 32 | USER_READ = 4 | |
| 33 | PRIV_WRITE = 3 | |
| 34 | PRIV_READ = 2 | |
| 35 | HPRV_WRITE = 1 | |
| 36 | HPRV_READ = 0 | |
| 37 | ||
| 38 | def user_read_ill_inst(self): | |
| 39 | return self.mode[self.USER_READ] == self.ILL_INST | |
| 40 | def user_read_priv_opc(self): | |
| 41 | return self.mode[self.USER_READ] == self.PRIV_OPC | |
| 42 | def user_write_ill_inst(self): | |
| 43 | return self.mode[self.USER_WRITE] == self.ILL_INST | |
| 44 | def user_write_priv_opc(self): | |
| 45 | return self.mode[self.USER_WRITE] == self.PRIV_OPC | |
| 46 | ||
| 47 | def priv_read_ill_inst(self): | |
| 48 | return self.mode[self.PRIV_READ] == self.ILL_INST | |
| 49 | def priv_read_priv_opc(self): | |
| 50 | return self.mode[self.PRIV_READ] == self.PRIV_OPC | |
| 51 | def priv_write_ill_inst(self): | |
| 52 | return self.mode[self.PRIV_WRITE] == self.ILL_INST | |
| 53 | def priv_write_priv_opc(self): | |
| 54 | return self.mode[self.PRIV_WRITE] == self.PRIV_OPC | |
| 55 | ||
| 56 | def hprv_read_ill_inst(self): | |
| 57 | return self.mode[self.HPRV_READ] == self.ILL_INST | |
| 58 | def hprv_read_priv_opc(self): | |
| 59 | return self.mode[self.HPRV_READ] == self.PRIV_OPC | |
| 60 | def hprv_write_ill_inst(self): | |
| 61 | return self.mode[self.HPRV_WRITE] == self.ILL_INST | |
| 62 | def hprv_write_priv_opc(self): | |
| 63 | return self.mode[self.HPRV_WRITE] == self.PRIV_OPC | |
| 64 | ||
| 65 | def is_ro(self): | |
| 66 | return self.user_write_ill_inst() \ | |
| 67 | and self.priv_write_ill_inst() \ | |
| 68 | and self.hprv_write_ill_inst() | |
| 69 | ||
| 70 | def is_wo(self): | |
| 71 | return self.user_read_ill_inst() \ | |
| 72 | and self.priv_read_ill_inst() \ | |
| 73 | and self.hprv_read_ill_inst() | |
| 74 | ||
| 75 | WO____ = SS_Access('i-iiii') | |
| 76 | RO____ = SS_Access('-iiiii') | |
| 77 | RW____ = SS_Access('--iiii') | |
| 78 | ||
| 79 | WOWO__ = SS_Access('i-i-ip') # asr softint_set and asr softint_clr | |
| 80 | RORO__ = SS_Access('-i-ipi') | |
| 81 | RWRO__ = SS_Access('---ipp') # prf tick | |
| 82 | RWRW__ = SS_Access('----pp') # asr softint and all rw prf | |
| 83 | ||
| 84 | WOWOWO = SS_Access('i-i-i-') | |
| 85 | RORORO = SS_Access('-i-i-i') # asr pc and asr tick | |
| 86 | RWRORO = SS_Access('---i-i') # asr stick | |
| 87 | RWRWRW = SS_Access('------') | |
| 88 | ||
| 89 | OOOOOO = SS_Access('iiiiii') # can't use ______ :-(, this is used for simulator specifics | |
| 90 | ||
| 91 | ||
| 92 | ||
| 93 | ||
| 94 |