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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_InstrFpu.py
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920dae64
AT		 1# ========== Copyright Header Begin ==========================================
2#
3# OpenSPARC T2 Processor File: SS_InstrFpu.py
4# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6#
7# The above named program is free software; you can redistribute it and/or
8# modify it under the terms of the GNU General Public
9# License version 2 as published by the Free Software Foundation.
10#
11# The above named program is distributed in the hope that it will be
12# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14# General Public License for more details.
15#
16# You should have received a copy of the GNU General Public
17# License along with this work; if not, write to the Free Software
18# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19#
20# ========== Copyright Header End ============================================
21from SS_Instr import *
22from SS_InstrFpop import *
23
24# Todo:
25#
26# @ fabs, fneg, fmov can be implemented more efficiently
27# @ n2 fpop do unfinished traps .... need to implement that
28# @ fp disabled should be a separate flag so we don;t have to do andcc
29# @ check fsr gsr restore
30#
31
32#============================================================================
33# SS_fmovcc(opc,cc,ccr)
34#
35# ToDo: movn & mova can be optimised
36#============================================================================
37
38class SS_fmovcc(SS_fpop):
39 def __init__(self,opc,cc,ccr):
40 SS_InstrAsm.__init__(self,opc+cc+'_'+ccr)
41 self.opc = opc
42 self.cc = cc
43 self.ccr = ccr
44
45 def gen_exe_tbl(self,file,mode):
46 file.write(' %s_exe_%s,\n' % (mode,self.name))
47
48 def run_exe_s(self,file):
49 self.fpop_init(file)
50 self.ld_rs2(file,'%g2')
51 self.ld_rd(file,'%g3')
52 if self.ccr[:3] != 'fcc':
53 self.ld_ccr(file,'%g1')
54 if self.opc[-1] == 's':
55 self.ld_frf(file,'%g2','%f0')
56 else:
57 self.ld_drf(file,'%g2','%f0')
58 if self.opc[-1] == 's':
59 self.ld_frf(file,'%g3','%f8')
60 else:
61 self.ld_drf(file,'%g3','%f8')
62 if self.ccr[:3] != 'fcc':
63 self.wr_ccr(file,'%g1')
64 self.opr(file,self.opc+self.cc,'%'+self.ccr,'%f0','%f8')
65 if self.opc[-1] == 's':
66 self.fpop_fini_cc_f(file,self.cc,self.ccr)
67 else:
68 self.fpop_fini_cc_d(file,self.cc,self.ccr)
69
70 def run_exe_c(self,file):
71 file.write('#if defined(ARCH_X64)\n')
72 self.c_code_beg(file,'run_exe_')
73 file.write(' if (s->sim_state.fp_disabled())\n')
74 file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')
75 if (self.ccr[:3] == 'fcc'):
76 self.test_fcc(file,' ')
77 file.write(' {\n')
78 else:
79 self.test_icc(file,' ')
80 file.write(' {\n')
81 if (self.opc[-1] == 's'):
82 file.write(' s->get_frf(i->rd) = s->get_frf(i->rs2);\n')
83 else:
84 file.write(' s->get_drf(i->rd) = s->get_drf(i->rs2);\n')
85 file.write(' s->set_fprs(i->rd);\n')
86 file.write(' }\n')
87 file.write(' s->fsr_run.ftt(0);\n')
88 file.write(' s->fsr_exc.cexc(0);\n')
89 file.write(' s->npc = npc+4;\n')
90 file.write(' return npc;\n')
91 self.c_code_end(file)
92 file.write('#else\n')
93 file.write('extern "C" SS_Vaddr run_exe_%s( SS_Vaddr, SS_Vaddr, SS_Strand*, SS_Instr* );\n' % (self.name))
94 file.write('#endif\n')
95
96 def run_dec_c(self,file):
97 self.c_code_dec_beg(file,'run_dec_')
98 file.write(' i->flg = SS_Instr::NON_LSU;\n')
99 self.ill_ibe(file)
100 if self.opc[-1] == 's':
101 self.dec_f0f(file,' ','idx_exe_'+self.name)
102 else:
103 self.dec_d0d(file,' ','idx_exe_'+self.name)
104 self.c_code_end(file)
105
106 def gen_exe_tbl(self,file,mode):
107 if mode == 'trc':
108 if self.opc[-1] == 's':
109 file.write(' trc_exe_f0f, /* '+self.name+' */\n')
110 else:
111 file.write(' trc_exe_d0d, /* '+self.name+' */\n')
112 elif mode == 'v8_run':
113 file.write(' run_exe_v8plus_to_v9, /* run_exe_'+self.name+' */\n')
114 else:
115 SS_Instr.gen_exe_tbl(self,file,mode)
116
117#============================================================================
118# SS_fmovr(opc,cc)
119#
120# ToDo fmovr does not have to use floating point at all.
121#============================================================================
122
123class SS_fmovr(SS_fpop):
124 def __init__(self,opc,cc):
125 SS_InstrAsm.__init__(self,opc+cc)
126 self.opc = opc
127 self.cc = cc
128
129 def gen_exe_tbl(self,file,mode):
130 file.write(' %s_exe_%s,\n' % (mode,self.name))
131
132 def run_exe_s(self,file):
133 self.fpop_init(file)
134 self.ld_rs1(file,'%g1')
135 self.ld_rs2(file,'%g2')
136 self.ld_rd(file,'%g3')
137 self.ld_irf(file,'%g1','%g1')
138 if self.opc[-1] == 's':
139 self.ld_frf(file,'%g2','%f0')
140 self.ld_frf(file,'%g3','%f8')
141 else:
142 self.ld_drf(file,'%g2','%f0')
143 self.ld_drf(file,'%g3','%f8')
144 self.opr(file,self.opc+self.cc,'%g1','%f0','%f8')
145 if self.opc[-1] == 's':
146 self.fpop_fini_cc_f(file,'r'+self.cc,'g1')
147 else:
148 self.fpop_fini_cc_d(file,'r'+self.cc,'g1')
149
150 def run_exe_c(self,file):
151 file.write('#if defined(ARCH_X64)\n')
152 self.c_code_beg(file,'run_exe_')
153 file.write(' if (s->sim_state.fp_disabled())\n')
154 file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')
155 self.test_r(file,' ')
156 file.write(' {\n')
157 if (self.opc[-1] == 's'):
158 file.write(' s->get_frf(i->rd) = s->get_frf(i->rs2);\n')
159 else:
160 file.write(' s->get_drf(i->rd) = s->get_drf(i->rs2);\n')
161 file.write(' s->set_fprs(i->rd);\n')
162 file.write(' }\n')
163 file.write(' s->fsr_run.ftt(0);\n')
164 file.write(' s->fsr_exc.cexc(0);\n')
165 file.write(' s->npc = npc+4;\n')
166 file.write(' return npc;\n')
167 self.c_code_end(file)
168 file.write('#else\n')
169 file.write('extern "C" SS_Vaddr run_exe_%s( SS_Vaddr, SS_Vaddr, SS_Strand*, SS_Instr* );\n' % (self.name))
170 file.write('#endif\n')
171
172 def run_dec_c(self,file):
173 self.c_code_dec_beg(file,'run_dec_')
174 file.write(' i->flg = SS_Instr::NON_LSU;\n')
175 self.ill_ibe(file)
176 if self.opc[-1] == 's':
177 self.dec_frf(file,' ','idx_exe_'+self.name)
178 else:
179 self.dec_drd(file,' ','idx_exe_'+self.name)
180 self.c_code_end(file)
181
182 def gen_exe_tbl(self,file,mode):
183 if mode == 'trc':
184 if self.opc[-1] == 's':
185 file.write(' trc_exe_frf, /* '+self.name+' */\n')
186 else:
187 file.write(' trc_exe_drd, /* '+self.name+' */\n')
188 elif mode == 'v8_run':
189 file.write(' run_exe_v8plus_to_v9, /* run_exe_'+self.name+' */\n')
190 else:
191 SS_Instr.gen_exe_tbl(self,file,mode)
192
193#============================================================================
194# SS_fcmp
195#============================================================================
196
197class SS_fcmp(SS_fpop):
198 def __init__(self,opc):
199 SS_fpop.__init__(self,opc)
200
201 def run_exe_c(self,file,product='run'):
202 SS_fpop.run_exe_c(self,file,setup.product.lower())
203
204 def run_dec_c(self,file):
205 self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
206 file.write(' i->flg = SS_Instr::NON_LSU;\n')
207 file.write(' if (o.get_rd() < 4)\n')
208 file.write(' {\n')
209 self.ill_ibe(file)
210 if self.opc[-1] == 's':
211 self.dec_nff(file,' ','idx_exe_'+self.opc)
212 else:
213 self.dec_ndd(file,' ','idx_exe_'+self.opc)
214 file.write(' }\n')
215 file.write(' else\n')
216 file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
217 self.c_code_end(file)
218
219 def gen_exe_tbl(self,file,mode):
220 if mode == 'v8_run':
221 mode = 'run'
222 if mode == 'trc':
223 if self.opc[-1] == 's':
224 file.write(' trc_exe_0ff, /* '+self.name+' */\n')
225 else:
226 file.write(' trc_exe_0dd, /* '+self.name+' */\n')
227 else:
228 SS_fpop.gen_exe_tbl(self,file,mode)
229
230#============================================================================
231# fpop1
232#============================================================================
233
234ss_fpop1 = SS_InstrGroup('10_110100_fpop1',5,0x1ff)
235
236ss_fpop1.append(SS_ill())
237ss_fpop1.append(SS_fp_f0f('fmovs'))
238ss_fpop1.append(SS_fp_d0d('fmovd'))
239ss_fpop1.append(SS_ill())
240ss_fpop1.append(SS_ill())
241ss_fpop1.append(SS_fp_f0f('fnegs'))
242ss_fpop1.append(SS_fp_d0d('fnegd'))
243ss_fpop1.append(SS_ill())
244ss_fpop1.append(SS_ill())
245ss_fpop1.append(SS_fp_f0f('fabss'))
246ss_fpop1.append(SS_fp_d0d('fabsd'))
247ss_fpop1.append(SS_ill())
248ss_fpop1.append(SS_ill())
249ss_fpop1.append(SS_ill())
250ss_fpop1.append(SS_ill())
251ss_fpop1.append(SS_ill())
252
253for i in range(0,16):
254 ss_fpop1.append(SS_ill())
255
256ss_fpop1.append(SS_ill())
257ss_fpop1.append(SS_ill())
258ss_fpop1.append(SS_ill())
259ss_fpop1.append(SS_ill())
260ss_fpop1.append(SS_ill())
261ss_fpop1.append(SS_ill())
262ss_fpop1.append(SS_ill())
263ss_fpop1.append(SS_ill())
264ss_fpop1.append(SS_ill())
265ss_fpop1.append(SS_fp_f0f('fsqrts'))
266ss_fpop1.append(SS_fp_d0d('fsqrtd'))
267ss_fpop1.append(SS_ill())
268ss_fpop1.append(SS_ill())
269if setup.product == 'N2':
270 ss_fpop1.append(SS_ill())
271 ss_fpop1.append(SS_ill())
272ss_fpop1.append(SS_ill())
273
274for i in range(0,16):
275 ss_fpop1.append(SS_ill())
276
277ss_fpop1.append(SS_ill())
278ss_fpop1.append(SS_fp_fff('fadds'))
279ss_fpop1.append(SS_fp_ddd('faddd'))
280ss_fpop1.append(SS_ill())
281ss_fpop1.append(SS_ill())
282ss_fpop1.append(SS_fp_fff('fsubs'))
283ss_fpop1.append(SS_fp_ddd('fsubd'))
284ss_fpop1.append(SS_ill())
285ss_fpop1.append(SS_ill())
286ss_fpop1.append(SS_fp_fff('fmuls'))
287ss_fpop1.append(SS_fp_ddd('fmuld'))
288ss_fpop1.append(SS_ill())
289ss_fpop1.append(SS_ill())
290ss_fpop1.append(SS_fp_fff('fdivs'))
291ss_fpop1.append(SS_fp_ddd('fdivd'))
292ss_fpop1.append(SS_ill())
293
294if setup.product in ['N2']:
295 for i in range(0,16):
296 ss_fpop1.append(SS_ill())
297
298ss_fpop1.append(SS_ill())
299if setup.product in ['N2']:
300 ss_fpop1.append(SS_ill())
301 ss_fpop1.append(SS_ill())
302ss_fpop1.append(SS_ill())
303ss_fpop1.append(SS_ill())
304if setup.product in ['N2']:
305 ss_fpop1.append(SS_ill())
306 ss_fpop1.append(SS_ill())
307ss_fpop1.append(SS_ill())
308ss_fpop1.append(SS_ill())
309ss_fpop1.append(SS_fp_dff('fsmuld'))
310ss_fpop1.append(SS_ill())
311ss_fpop1.append(SS_ill())
312ss_fpop1.append(SS_ill())
313ss_fpop1.append(SS_ill())
314ss_fpop1.append(SS_ill())
315ss_fpop1.append(SS_ill())
316
317if setup.product in ['N2']:
318 for i in range(0,16):
319 ss_fpop1.append(SS_ill())
320
321ss_fpop1.append(SS_ill())
322ss_fpop1.append(SS_fp_d0f('fstox'))
323ss_fpop1.append(SS_fp_d0d('fdtox'))
324ss_fpop1.append(SS_ill())
325ss_fpop1.append(SS_fp_f0d('fxtos'))
326ss_fpop1.append(SS_ill())
327ss_fpop1.append(SS_ill())
328ss_fpop1.append(SS_ill())
329ss_fpop1.append(SS_fp_d0d('fxtod'))
330ss_fpop1.append(SS_ill())
331ss_fpop1.append(SS_ill())
332ss_fpop1.append(SS_ill())
333ss_fpop1.append(SS_ill())
334ss_fpop1.append(SS_ill())
335ss_fpop1.append(SS_ill())
336ss_fpop1.append(SS_ill())
337
338for i in range(0,48):
339 ss_fpop1.append(SS_ill())
340
341ss_fpop1.append(SS_ill())
342ss_fpop1.append(SS_ill())
343ss_fpop1.append(SS_ill())
344ss_fpop1.append(SS_ill())
345ss_fpop1.append(SS_fp_f0f('fitos'))
346ss_fpop1.append(SS_ill())
347ss_fpop1.append(SS_fp_f0d('fdtos'))
348ss_fpop1.append(SS_ill())
349ss_fpop1.append(SS_fp_d0f('fitod'))
350ss_fpop1.append(SS_fp_d0f('fstod'))
351ss_fpop1.append(SS_ill())
352ss_fpop1.append(SS_ill())
353ss_fpop1.append(SS_ill())
354ss_fpop1.append(SS_ill())
355ss_fpop1.append(SS_ill())
356ss_fpop1.append(SS_ill())
357
358ss_fpop1.append(SS_ill())
359ss_fpop1.append(SS_fp_f0f('fstoi'))
360ss_fpop1.append(SS_fp_f0d('fdtoi'))
361ss_fpop1.append(SS_ill())
362ss_fpop1.append(SS_ill())
363ss_fpop1.append(SS_ill())
364ss_fpop1.append(SS_ill())
365ss_fpop1.append(SS_ill())
366ss_fpop1.append(SS_ill())
367ss_fpop1.append(SS_ill())
368ss_fpop1.append(SS_ill())
369ss_fpop1.append(SS_ill())
370ss_fpop1.append(SS_ill())
371ss_fpop1.append(SS_ill())
372ss_fpop1.append(SS_ill())
373ss_fpop1.append(SS_ill())
374
375for i in range(0,32):
376 ss_fpop1.append(SS_ill())
377
378for i in range(0,256):
379 ss_fpop1.append(SS_ill())
380
381#============================================================================
382# fpop2
383#============================================================================
384
385ss_fmovsfcc0 = SS_InstrGroup('10_110101_000000001_fmovsfcc0',14,0x1f)
386ss_fmovsfcc1 = SS_InstrGroup('10_110101_001000001_fmovsfcc1',14,0x1f)
387ss_fmovsfcc2 = SS_InstrGroup('10_110101_010000001_fmovsfcc2',14,0x1f)
388ss_fmovsfcc3 = SS_InstrGroup('10_110101_011000001_fmovsfcc3',14,0x1f)
389ss_fmovsicc = SS_InstrGroup('10_110101_100000001_fmovsicc',14,0x1f)
390ss_fmovsxcc = SS_InstrGroup('10_110101_110000001_fmovsxcc',14,0x1f)
391
392ss_fmovdfcc0 = SS_InstrGroup('10_110101_000000010_fmovsfcc0',14,0x1f)
393ss_fmovdfcc1 = SS_InstrGroup('10_110101_001000010_fmovsfcc1',14,0x1f)
394ss_fmovdfcc2 = SS_InstrGroup('10_110101_010000010_fmovsfcc2',14,0x1f)
395ss_fmovdfcc3 = SS_InstrGroup('10_110101_011000010_fmovsfcc3',14,0x1f)
396ss_fmovdicc = SS_InstrGroup('10_110101_100000010_fmovsicc',14,0x1f)
397ss_fmovdxcc = SS_InstrGroup('10_110101_110000010_fmovsxcc',14,0x1f)
398
399for cc,x in fcond:
400 ss_fmovsfcc0.append(SS_fmovcc('fmovs',cc,'fcc0'))
401 ss_fmovsfcc1.append(SS_fmovcc('fmovs',cc,'fcc1'))
402 ss_fmovsfcc2.append(SS_fmovcc('fmovs',cc,'fcc2'))
403 ss_fmovsfcc3.append(SS_fmovcc('fmovs',cc,'fcc3'))
404 ss_fmovdfcc0.append(SS_fmovcc('fmovd',cc,'fcc0'))
405 ss_fmovdfcc1.append(SS_fmovcc('fmovd',cc,'fcc1'))
406 ss_fmovdfcc2.append(SS_fmovcc('fmovd',cc,'fcc2'))
407 ss_fmovdfcc3.append(SS_fmovcc('fmovd',cc,'fcc3'))
408
409for cc,x in cond:
410 ss_fmovsicc.append(SS_fmovcc('fmovs',cc,'icc'))
411 ss_fmovdicc.append(SS_fmovcc('fmovd',cc,'icc'))
412 ss_fmovsxcc.append(SS_fmovcc('fmovs',cc,'xcc'))
413 ss_fmovdxcc.append(SS_fmovcc('fmovd',cc,'xcc'))
414
415for i in range(0,16):
416 ss_fmovsfcc0.append(SS_ill())
417 ss_fmovsfcc1.append(SS_ill())
418 ss_fmovsfcc2.append(SS_ill())
419 ss_fmovsfcc3.append(SS_ill())
420 ss_fmovdfcc0.append(SS_ill())
421 ss_fmovdfcc1.append(SS_ill())
422 ss_fmovdfcc2.append(SS_ill())
423 ss_fmovdfcc3.append(SS_ill())
424 ss_fmovsicc.append(SS_ill())
425 ss_fmovdicc.append(SS_ill())
426 ss_fmovsxcc.append(SS_ill())
427 ss_fmovdxcc.append(SS_ill())
428
429ss_fpop2 = SS_InstrGroup('10_110101_fpop2',5,0x1ff)
430
431# 0 0000 0000
432ss_fpop2.append(SS_ill())
433ss_fpop2.append(ss_fmovsfcc0)
434ss_fpop2.append(ss_fmovdfcc0)
435ss_fpop2.append(SS_ill())
436ss_fpop2.append(SS_ill())
437ss_fpop2.append(SS_ill())
438ss_fpop2.append(SS_ill())
439ss_fpop2.append(SS_ill())
440ss_fpop2.append(SS_ill())
441ss_fpop2.append(SS_ill())
442ss_fpop2.append(SS_ill())
443ss_fpop2.append(SS_ill())
444ss_fpop2.append(SS_ill())
445ss_fpop2.append(SS_ill())
446ss_fpop2.append(SS_ill())
447ss_fpop2.append(SS_ill())
448
449# 0 0001 0000
450for i in range(0,16):
451 ss_fpop2.append(SS_ill())
452
453# 0 0010 0000
454ss_fpop2.append(SS_ill())
455ss_fpop2.append(SS_ill())
456ss_fpop2.append(SS_ill())
457ss_fpop2.append(SS_ill())
458ss_fpop2.append(SS_ill())
459ss_fpop2.append(SS_fmovr('fmovrs','z'))
460ss_fpop2.append(SS_fmovr('fmovrd','z'))
461ss_fpop2.append(SS_ill())
462ss_fpop2.append(SS_ill())
463ss_fpop2.append(SS_ill())
464ss_fpop2.append(SS_ill())
465ss_fpop2.append(SS_ill())
466ss_fpop2.append(SS_ill())
467ss_fpop2.append(SS_ill())
468ss_fpop2.append(SS_ill())
469ss_fpop2.append(SS_ill())
470
471# 0 0011 0000
472for i in range(0,16):
473 ss_fpop2.append(SS_ill())
474
475# 0 0100 0000
476ss_fpop2.append(SS_ill())
477ss_fpop2.append(ss_fmovsfcc1)
478ss_fpop2.append(ss_fmovdfcc1)
479ss_fpop2.append(SS_ill())
480ss_fpop2.append(SS_ill())
481ss_fpop2.append(SS_fmovr('fmovrs','lez'))
482ss_fpop2.append(SS_fmovr('fmovrd','lez'))
483ss_fpop2.append(SS_ill())
484ss_fpop2.append(SS_ill())
485ss_fpop2.append(SS_ill())
486ss_fpop2.append(SS_ill())
487ss_fpop2.append(SS_ill())
488ss_fpop2.append(SS_ill())
489ss_fpop2.append(SS_ill())
490ss_fpop2.append(SS_ill())
491ss_fpop2.append(SS_ill())
492
493# 0 0101 0000
494ss_fpop2.append(SS_ill())
495ss_fpop2.append(SS_fcmp('fcmps'))
496ss_fpop2.append(SS_fcmp('fcmpd'))
497ss_fpop2.append(SS_ill())
498ss_fpop2.append(SS_ill())
499ss_fpop2.append(SS_fcmp('fcmpes'))
500ss_fpop2.append(SS_fcmp('fcmped'))
501ss_fpop2.append(SS_ill())
502ss_fpop2.append(SS_ill())
503ss_fpop2.append(SS_ill())
504ss_fpop2.append(SS_ill())
505ss_fpop2.append(SS_ill())
506ss_fpop2.append(SS_ill())
507ss_fpop2.append(SS_ill())
508ss_fpop2.append(SS_ill())
509ss_fpop2.append(SS_ill())
510
511# 0 0110 0000
512ss_fpop2.append(SS_ill())
513ss_fpop2.append(SS_ill())
514ss_fpop2.append(SS_ill())
515ss_fpop2.append(SS_ill())
516ss_fpop2.append(SS_ill())
517ss_fpop2.append(SS_fmovr('fmovrs','lz'))
518ss_fpop2.append(SS_fmovr('fmovrd','lz'))
519ss_fpop2.append(SS_ill())
520ss_fpop2.append(SS_ill())
521ss_fpop2.append(SS_ill())
522ss_fpop2.append(SS_ill())
523ss_fpop2.append(SS_ill())
524ss_fpop2.append(SS_ill())
525ss_fpop2.append(SS_ill())
526ss_fpop2.append(SS_ill())
527ss_fpop2.append(SS_ill())
528
529# 0 0111 0000
530for i in range(0,16):
531 ss_fpop2.append(SS_ill())
532
533# 0 1000 0000
534ss_fpop2.append(SS_ill())
535ss_fpop2.append(ss_fmovsfcc2)
536ss_fpop2.append(ss_fmovdfcc2)
537ss_fpop2.append(SS_ill())
538ss_fpop2.append(SS_ill())
539ss_fpop2.append(SS_ill())
540ss_fpop2.append(SS_ill())
541ss_fpop2.append(SS_ill())
542ss_fpop2.append(SS_ill())
543ss_fpop2.append(SS_ill())
544ss_fpop2.append(SS_ill())
545ss_fpop2.append(SS_ill())
546ss_fpop2.append(SS_ill())
547ss_fpop2.append(SS_ill())
548ss_fpop2.append(SS_ill())
549ss_fpop2.append(SS_ill())
550
551# 0 1001 0000
552for i in range(0,16):
553 ss_fpop2.append(SS_ill())
554
555# 0 1010 0000
556ss_fpop2.append(SS_ill())
557ss_fpop2.append(SS_ill())
558ss_fpop2.append(SS_ill())
559ss_fpop2.append(SS_ill())
560ss_fpop2.append(SS_ill())
561ss_fpop2.append(SS_fmovr('fmovrs','nz'))
562ss_fpop2.append(SS_fmovr('fmovrd','nz'))
563ss_fpop2.append(SS_ill())
564ss_fpop2.append(SS_ill())
565ss_fpop2.append(SS_ill())
566ss_fpop2.append(SS_ill())
567ss_fpop2.append(SS_ill())
568ss_fpop2.append(SS_ill())
569ss_fpop2.append(SS_ill())
570ss_fpop2.append(SS_ill())
571ss_fpop2.append(SS_ill())
572
573# 0 1011 0000
574for i in range(0,16):
575 ss_fpop2.append(SS_ill())
576
577# 0 1100 0000
578ss_fpop2.append(SS_ill())
579ss_fpop2.append(ss_fmovsfcc3)
580ss_fpop2.append(ss_fmovdfcc3)
581ss_fpop2.append(SS_ill())
582ss_fpop2.append(SS_ill())
583ss_fpop2.append(SS_fmovr('fmovrs','gz'))
584ss_fpop2.append(SS_fmovr('fmovrd','gz'))
585ss_fpop2.append(SS_ill())
586ss_fpop2.append(SS_ill())
587ss_fpop2.append(SS_ill())
588ss_fpop2.append(SS_ill())
589ss_fpop2.append(SS_ill())
590ss_fpop2.append(SS_ill())
591ss_fpop2.append(SS_ill())
592ss_fpop2.append(SS_ill())
593ss_fpop2.append(SS_ill())
594
595# 0 1101 0000
596for i in range(0,16):
597 ss_fpop2.append(SS_ill())
598
599# 0 1110 0000
600ss_fpop2.append(SS_ill())
601ss_fpop2.append(SS_ill())
602ss_fpop2.append(SS_ill())
603ss_fpop2.append(SS_ill())
604ss_fpop2.append(SS_ill())
605ss_fpop2.append(SS_fmovr('fmovrs','gez'))
606ss_fpop2.append(SS_fmovr('fmovrd','gez'))
607ss_fpop2.append(SS_ill())
608ss_fpop2.append(SS_ill())
609ss_fpop2.append(SS_ill())
610ss_fpop2.append(SS_ill())
611ss_fpop2.append(SS_ill())
612ss_fpop2.append(SS_ill())
613ss_fpop2.append(SS_ill())
614ss_fpop2.append(SS_ill())
615ss_fpop2.append(SS_ill())
616
617# 0 1111 0000
618for i in range(0,16):
619 ss_fpop2.append(SS_ill())
620
621ss_fpop2.append(SS_ill())
622ss_fpop2.append(ss_fmovsicc)
623ss_fpop2.append(ss_fmovdicc)
624ss_fpop2.append(SS_ill())
625ss_fpop2.append(SS_ill())
626ss_fpop2.append(SS_ill())
627ss_fpop2.append(SS_ill())
628ss_fpop2.append(SS_ill())
629ss_fpop2.append(SS_ill())
630ss_fpop2.append(SS_ill())
631ss_fpop2.append(SS_ill())
632ss_fpop2.append(SS_ill())
633ss_fpop2.append(SS_ill())
634ss_fpop2.append(SS_ill())
635ss_fpop2.append(SS_ill())
636ss_fpop2.append(SS_ill())
637
638for i in range(0,48):
639 ss_fpop2.append(SS_ill())
640
641for i in range(0,64):
642 ss_fpop2.append(SS_ill())
643
644ss_fpop2.append(SS_ill())
645ss_fpop2.append(ss_fmovsxcc)
646ss_fpop2.append(ss_fmovdxcc)
647ss_fpop2.append(SS_ill())
648ss_fpop2.append(SS_ill())
649ss_fpop2.append(SS_ill())
650ss_fpop2.append(SS_ill())
651ss_fpop2.append(SS_ill())
652ss_fpop2.append(SS_ill())
653ss_fpop2.append(SS_ill())
654ss_fpop2.append(SS_ill())
655ss_fpop2.append(SS_ill())
656ss_fpop2.append(SS_ill())
657ss_fpop2.append(SS_ill())
658ss_fpop2.append(SS_ill())
659ss_fpop2.append(SS_ill())
660
661for i in range(0,48):
662 ss_fpop2.append(SS_ill())
663
664for i in range(0,64):
665 ss_fpop2.append(SS_ill())
666
667#============================================================================
668# fma
669#============================================================================
670
671ss_fmaf = SS_InstrGroup('10_110111_fmaf',5,0xf)
672ss_fmau = SS_InstrGroup('10_111111_fmau',5,0xf)
673
674if setup.product in ['N2']:
675 for i in range(0,16):
676 ss_fmaf.append(SS_ill())
677
678if setup.product in ['N2']:
679 for i in range(0,16):
680 ss_fmau.append(SS_ill())
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.