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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_InstrRun.py
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920dae64
AT		 1# ========== Copyright Header Begin ==========================================
2#
3# OpenSPARC T2 Processor File: SS_InstrRun.py
4# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6#
7# The above named program is free software; you can redistribute it and/or
8# modify it under the terms of the GNU General Public
9# License version 2 as published by the Free Software Foundation.
10#
11# The above named program is distributed in the hope that it will be
12# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14# General Public License for more details.
15#
16# You should have received a copy of the GNU General Public
17# License along with this work; if not, write to the Free Software
18# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19#
20# ========== Copyright Header End ============================================
21
22from SS_Setup import *
23from SS_InstrSim import *
24from SS_InstrAlu import *
25from SS_InstrCtr import *
26from SS_InstrCti import *
27from SS_InstrLsu import *
28from SS_InstrFpu import *
29from SS_InstrVis import *
30
31setup = setups[sys.argv[1]]
32
33mem = []
34exe = SS_InstrTable(setup, 'xx_xxxxxx')
35
36# 00_xxxxxx
37
38exe.append(SS_illtrap())
39exe.append(ss_bp_icc)
40exe.append(ss_bp_c01)
41exe.append(ss_bp_xcc)
42exe.append(ss_bp_c11)
43exe.append(ss_bi)
44exe.append(ss_br)
45exe.append(SS_nop())
46exe.append(SS_sethi())
47exe.append(ss_fbp_fcc0)
48exe.append(ss_fbp_fcc1)
49exe.append(ss_fbp_fcc2)
50exe.append(ss_fbp_fcc3)
51exe.append(ss_fbi)
52for i in range(0,8):
53 exe.append(SS_ill())
54
55# 01_xxxxxx
56
57exe.append(SS_call())
58
59# 10_000xxx add .... xnor,
60# 10_001xxx addc mulx umul smul subc udivx udiv sdiv
61# 10_010xxx addcc .... xnorcc,
62# 10_011xxx addccc - umulcc smulcc subccc - udivcc sdivcc
63# 10_100xxx taddcc tsubcc taddcctv tsubcctv mulscc sll srl sra
64# 10_101xxx rdasr rdhrf rdprf flushw movcc sdivx popc movr
65# 10_110xxx wrasr saved/restored wrprf wrhrf fpop1 fpop2 vis fmaf
66# 10_111xxx jmpl return tcc flush(a) save restore done/retry fmau
67
68for i in ['add','and','or','xor','sub','andn','orn','xnor']:
69 exe.append(SS_alu(i))
70for i in ['addc','mulx','umul','smul','subc','udivx','udiv','sdiv']:
71 exe.append(SS_alu(i))
72for i in ['addcc','andcc','orcc','xorcc','subcc','andncc','orncc','xnorcc']:
73 exe.append(SS_alu(i))
74for i in ['addccc','-','umulcc','smulcc','subccc','-','udivcc','sdivcc']:
75 if i == '-':
76 exe.append(SS_ill())
77 else:
78 exe.append(SS_alu(i))
79
80exe.append(SS_tagged_alu('taddcc'))
81exe.append(SS_tagged_alu('tsubcc'))
82exe.append(SS_tagged_alu('taddcctv'))
83exe.append(SS_tagged_alu('tsubcctv'))
84if setup.product == 'N2':
85 exe.append(SS_alu('mulscc'))
86exe.append(ss_sll)
87exe.append(ss_srl)
88exe.append(ss_sra)
89
90exe.append(ss_rdasr)
91exe.append(ss_rdhrf)
92exe.append(ss_rdprf)
93exe.append(SS_flushw())
94exe.append(ss_movcc)
95exe.append(SS_alu('sdivx'))
96exe.append(SS_popc())
97exe.append(ss_movr)
98
99exe.append(ss_wrasr)
100exe.append(ss_saved)
101exe.append(ss_wrprf)
102exe.append(ss_wrhrf)
103exe.append(ss_fpop1)
104exe.append(ss_fpop2)
105exe.append(ss_vis)
106exe.append(ss_fmaf)
107
108exe.append(SS_jmpl())
109exe.append(SS_return())
110exe.append(ss_tcc)
111exe.append(ss_flush)
112exe.append(SS_save())
113exe.append(SS_restore())
114exe.append(ss_done)
115exe.append(ss_fmau)
116
117for i in ['lduw', 'ldub', 'lduh', 'ldd', 'stw', 'stb', 'sth', 'std', # 11_000xxx
118 'ldsw', 'ldsb', 'ldsh', 'ldx', '-', 'ldstub', 'stx', 'swap', # 11_001xxx
119 'lduwa','lduba', 'lduha','ldda', 'stwa','stba', 'stha', 'stda', # 11_010xxx
120 'ldswa','ldsba', 'ldsha','ldxa', '-', 'ldstuba', 'stxa', 'swapa', # 11_011xxx
121 'ldf', 'ldxfsr','-', 'lddf', 'stf', 'stxfsr', '-', 'stdf', # 11_100xxx
122 '-', '-', '-', '-', '-', 'prefetch', '-', '-', # 11_101xxx
123 'ldfa', '-', '-', 'lddfa','stfa','-', '-', 'stdfa', # 11_110xxx
124 '-', '-', '-', '-', 'casa','prefetcha','casxa','-' ]: # 11_111xxx
125 if i == '-':
126 exe.append(SS_ill())
127 elif i == 'ldxfsr':
128 exe.append(ss_ldxfsr)
129 elif i == 'stxfsr':
130 exe.append(ss_stxfsr)
131 elif i == 'prefetch':
132 exe.append(ss_prefetch)
133 elif i == 'prefetcha':
134 exe.append(ss_prefetcha)
135 else:
136 exe.append(SS_lsu_dec(i))
137
138
139for i in ['lduw','ldub','lduh','ldd','ldsw','ldsb','ldsh','ldx','ldtd',
140 'stw','stb','sth','std','stx','stfsr','stxfsr',
141 'ldf','lddf','ldshortf8','ldshortf16','ldblockf','ldfsr','ldxfsr',
142 'stf','stdf','stshortf8','stshortf16','stpartial8','stpartial16','stpartial32','stblockf',
143 'ldstub','swap','cas','casx','prefetch','flush']:
144 exe.append(SS_lsu_exe(i))
145
146exe.append(SS_rdasi('i0','rd'))
147exe.append(SS_rdasi('i0','g0'))
148exe.append(SS_rdasi('i1','rd'))
149exe.append(SS_rdasi('i1','g0'))
150exe.append(SS_wrasi('i0','rd'))
151exe.append(SS_wrasi('i0','g0'))
152exe.append(SS_wrasi('i1','rd'))
153exe.append(SS_wrasi('i1','g0'))
154
155for i in ['lduw','ldub','lduh','ldd','ldsw','ldsb','ldsh','ldx','ldtd']:
156 mem.append(SS_ld_mem(i,'rd'))
157 mem.append(SS_ld_mem(i,'g0'))
158for i in ['prefetch']:
159 mem.append(SS_ld_mem(i,'fn'))
160for i in ['ldf','lddf','ldshortf8','ldshortf16','ldblockf','ldfsr','ldxfsr']:
161 mem.append(SS_ld_mem(i,'fp'))
162for i in ['stw','stb','sth','std','stx']:
163 mem.append(SS_st_mem(i,'rd'))
164 mem.append(SS_st_mem(i,'g0'))
165for i in ['stf','stdf','stshortf8','stshortf16','stpartial8','stpartial16','stpartial32','stblockf','stfsr','stxfsr']:
166 mem.append(SS_st_mem(i,'fp'))
167
168mem.append(SS_ldstub_mem('ldstub','rd'))
169mem.append(SS_ldstub_mem('ldstub','g0'))
170mem.append(SS_swap_mem('swap','rd'))
171mem.append(SS_swap_mem('swap','g0'))
172mem.append(SS_cas_mem('cas','rd'))
173mem.append(SS_cas_mem('cas','g0'))
174mem.append(SS_cas_mem('casx','rd'))
175mem.append(SS_cas_mem('casx','g0'))
176mem.append(SS_flush_mem('flush','fn'))
177
178
179
180if sys.argv[2] == 's':
181
182 s_file=open('%sAsm.s' % sys.argv[3],'w')
183 s_file.write('#if !defined(ARCH_X64)\n')
184 s_file.write('#include "SS_Assembly.h"\n')
185 s_file.write('\n')
186 s_file.write('.section\t".text"\n')
187 s_file.write('\n')
188 s_file.write('.register\t%g2,#scratch\n')
189 s_file.write('.register\t%g3,#scratch\n')
190 s_file.write('\n')
191 s_file.write('/* cas and casx are not sun sparc instructions so for now do*/\n')
192 s_file.write('#define run_dec_cas run_dec_casa\n')
193 s_file.write('#define run_dec_casx run_dec_casxa\n')
194 s_file.write('\n')
195 s_file.write('#if defined(ARCH_V9)\n')
196 s_file.write('#define V8_PC\n')
197 s_file.write('#elif defined(ARCH_V8)\n')
198 s_file.write('#define V8_PC\\\n')
199 s_file.write(' srl %o0,0,%o1;\\\n')
200 s_file.write(' srlx %o0,32,%o0\n')
201 s_file.write('#else\n')
202 s_file.write('#error "Need ARCH option in make\n')
203 s_file.write('#endif\n')
204 s_file.write('\n')
205 s_file.write('#include "SS_Float.s"\n')
206 s_file.write('#include "SS_LsuTrap.s"\n')
207
208 s_file.write('\n')
209 for i in mem:
210 i.idx_mem_s(s_file)
211
212 s_file.write('\n')
213 exe.exe_idx_s(s_file)
214
215 exe.run_dec_s(s_file)
216 exe.run_exe_s(s_file)
217
218 s_file.write('#endif\n')
219 s_file.close()
220
221elif sys.argv[2] == 'h':
222
223 h_base_name = sys.argv[3].split('/')[-1]
224 h_file=open('%sCpp.h' % sys.argv[3],'w')
225 h_file.write('#ifndef __'+h_base_name+'Cpp_h__\n')
226 h_file.write('#define __'+h_base_name+'Cpp_h__\n')
227 h_file.write('\n')
228
229 h_file.write('\n')
230 h_file.write('extern SS_Memop mem_run_table[][4];\n')
231 h_file.write('extern SS_Memop mem_trc_table[][4];\n')
232 h_file.write('extern SS_Memop mem_ras_table[][4];\n')
233 h_file.write('\n')
234 h_file.write('extern SS_DecodeTable run_dec_xx_xxxxxx;\n')
235 h_file.write('\n')
236
237 h_file.write('\nenum ExeIdx\n')
238 h_file.write('{\n')
239 exe.gen_exe_tbl(h_file,mode='idx')
240 h_file.write(' idx_exe_table_size\n')
241 h_file.write('};\n\n')
242
243 h_file.write('#endif\n')
244 h_file.close()
245
246elif sys.argv[2] == 'cc':
247
248 c_file=open('%sCpp.cc' % sys.argv[3],'w')
249 c_file.write('#include "BL_Endian.h"\n')
250 c_file.write('#include "SS_Strand.h"\n')
251 c_file.write('#include "SS_Tlb.h"\n')
252 c_file.write('#include "SS_Decode.h"\n')
253 c_file.write('#include "SS_TrcExe.h"\n')
254 c_file.write('#include "SS_V8Code.h"\n')
255
256 if setup.product in ['N2']:
257 c_file.write('#include "BL_Hamming_64_8_Synd.h"\n')
258 c_file.write('#include "N2_Model.h"\n')
259 c_file.write('#include "N2_RunCpp.h"\n')
260 c_file.write('#include "N2_Strand.h"\n')
261 c_file.write('#include "N2_MemErrDetector.h"\n')
262
263 c_file.write('\nenum MemIdx\n')
264 c_file.write('{\n')
265 c_file.write(' idx_mem_xxxxx,\n')
266 for i in mem:
267 i.gen_mem_tbl(c_file,'idx')
268 c_file.write(' mem_idx_table_size\n')
269 c_file.write('};\n\n')
270
271 c_file.write('static inline uint64_t endianess_partial( uint64_t b )\n')
272 c_file.write('{\n')
273 c_file.write(' uint64_t v = 0;\n')
274 c_file.write(' for (int i=0; i<8; i++)\n')
275 c_file.write(' {\n')
276 c_file.write(' v = (v << 1) | (b & 1);\n')
277 c_file.write(' b >>= 1;\n')
278 c_file.write(' }\n')
279 c_file.write(' return v;\n')
280 c_file.write('}\n')
281 c_file.write('\n')
282
283 exe.run_exe_c(c_file)
284
285 for i in mem:
286 i.mem_c(c_file)
287
288 c_file.write('\n')
289 c_file.write('SS_Execute '+setup.product+'_Strand::run_exe_table[] =\n')
290 c_file.write('{\n')
291 exe.gen_exe_tbl(c_file,'run')
292 c_file.write(' 0\n')
293 c_file.write('};\n\n')
294
295 c_file.write('#if !defined(ARCH_X64)\n')
296 c_file.write('SS_Execute '+setup.product+'_Strand::v8_run_exe_table[] =\n')
297 c_file.write('{\n')
298 exe.gen_exe_tbl(c_file,'v8_run')
299 c_file.write(' 0\n')
300 c_file.write('};\n\n')
301 c_file.write('#endif\n')
302
303 c_file.write('SS_Execute '+setup.product+'_Strand::trc_exe_table[] =\n')
304 c_file.write('{\n')
305 exe.gen_exe_tbl(c_file,'trc')
306 c_file.write(' 0\n')
307 c_file.write('};\n\n')
308
309 c_file.write('SS_Memop '+setup.product+'_Strand::mem_run_table[][4] =\n')
310 c_file.write('{\n')
311 c_file.write(' mem_run_fetch512,\n')
312 c_file.write(' io_run_fetch512,\n')
313 c_file.write(' 0,\n')
314 c_file.write(' 0,\n')
315 for i in mem:
316 i.gen_mem_tbl(c_file,'run')
317 c_file.write(' 0\n')
318 c_file.write('};\n\n')
319
320 c_file.write('SS_Memop '+setup.product+'_Strand::mem_trc_table[][4] =\n')
321 c_file.write('{\n')
322 c_file.write(' mem_trc_fetch512,\n')
323 c_file.write(' io_trc_fetch512,\n')
324 c_file.write(' 0,\n')
325 c_file.write(' 0,\n')
326 for i in mem:
327 i.gen_mem_tbl(c_file,'trc')
328 c_file.write(' 0\n')
329 c_file.write('};\n\n')
330
331 c_file.write('SS_Memop '+setup.product+'_Strand::mem_ras_table[][4] =\n')
332 c_file.write('{\n')
333 c_file.write(' mem_trc_fetch512,\n')
334 c_file.write(' io_trc_fetch512,\n')
335 c_file.write(' 0,\n')
336 c_file.write(' 0,\n')
337 for i in mem:
338 i.gen_mem_tbl(c_file,'ras')
339 c_file.write(' 0\n')
340 c_file.write('};\n\n')
341
342 exe.run_dec_c(c_file)
343
344 c_file.close()
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.