projects / OpenSPARC-T2-SAM / blame
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|---|---|---|
| 920dae64 AT |
1 | # ========== Copyright Header Begin ========================================== |
| 2 | # | |
| 3 | # OpenSPARC T2 Processor File: SS_StateAsr.py | |
| 4 | # Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 5 | # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 6 | # | |
| 7 | # The above named program is free software; you can redistribute it and/or | |
| 8 | # modify it under the terms of the GNU General Public | |
| 9 | # License version 2 as published by the Free Software Foundation. | |
| 10 | # | |
| 11 | # The above named program is distributed in the hope that it will be | |
| 12 | # useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | # General Public License for more details. | |
| 15 | # | |
| 16 | # You should have received a copy of the GNU General Public | |
| 17 | # License along with this work; if not, write to the Free Software | |
| 18 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 19 | # | |
| 20 | # ========== Copyright Header End ============================================ | |
| 21 | ||
| 22 | import sys | |
| 23 | ||
| 24 | from SS_State import * | |
| 25 | from SS_Setup import * | |
| 26 | ||
| 27 | setup = setups[sys.argv[1]] | |
| 28 | ||
| 29 | ctr_regs = [ | |
| 30 | SS_CtrReg('SS','y' ,'asr', 0,RWRWRW,32, | |
| 31 | [ | |
| 32 | ]) | |
| 33 | , SS_CtrReg('SS','ccr' ,'asr', 2,RWRWRW, 8, | |
| 34 | [ | |
| 35 | ('icc' , 0, 3, RW, X), | |
| 36 | ('xcc' , 4, 7, RW, X) | |
| 37 | ]) | |
| 38 | , SS_CtrReg('SS','asi_reg' ,'asr', 3,RWRWRW, 8, | |
| 39 | [ | |
| 40 | ]) | |
| 41 | , SS_CtrReg('SS','tick' ,'asr', 4,RORORO,64, | |
| 42 | [ | |
| 43 | ('counter' , 0,62, RW, 0), | |
| 44 | ('npt' ,63,63, RW, 0) | |
| 45 | ]) | |
| 46 | , SS_CtrReg('SS','pc' ,'asr', 5,RORORO,64, | |
| 47 | [ | |
| 48 | ('' , 2,63, RW, 0)]) | |
| 49 | , SS_CtrReg('SS','fprs' ,'asr', 6,RWRWRW, 8, | |
| 50 | [ | |
| 51 | ('dl' , 0, 0, RW, 0), | |
| 52 | ('du' , 1, 1, RW, 0), | |
| 53 | ('fef' , 2, 2, RW, 0) | |
| 54 | ]) | |
| 55 | , SS_CtrReg('SS','gsr' ,'asr',19,RWRWRW,64, | |
| 56 | [ | |
| 57 | ('align' , 0, 2, RW, 0), | |
| 58 | ('scale' , 3, 7, RW, 0), | |
| 59 | ('irnd' ,25,26, RW, 0), | |
| 60 | ('im' ,27,27, RW, 0), | |
| 61 | ('mask' ,32,63, RW, 0) | |
| 62 | ]) | |
| 63 | , SS_CtrReg('SS','softint_set','asr',20,WOWO__, 8, | |
| 64 | [ | |
| 65 | # This register is the same as softint | |
| 66 | ]) | |
| 67 | , SS_CtrReg('SS','softint_clr','asr',21,WOWO__, 8, | |
| 68 | [ | |
| 69 | # This register is the same as softint | |
| 70 | ]) | |
| 71 | , SS_CtrReg('SS','softint' ,'asr',22,RWRW__,32, | |
| 72 | [ | |
| 73 | ('tm' , 0, 0, RW, 0), | |
| 74 | ('level' , 1,15, RW, 0), | |
| 75 | ('sm' ,16,16, RW, 0) | |
| 76 | ]) | |
| 77 | , SS_CtrReg('SS','tick_cmpr' ,'asr',23,RWRW__,64, | |
| 78 | [ | |
| 79 | ('cmpr' , 0,62, RW, 0), | |
| 80 | ('int_dis' ,63,63, RW, 1) | |
| 81 | ]) | |
| 82 | , SS_CtrReg('SS','stick' ,'asr',24,RWRORO,64, | |
| 83 | [ | |
| 84 | ('counter' , 0,62, RW, 0), | |
| 85 | ('npt' ,63,63, RW, 0) | |
| 86 | ]) | |
| 87 | , SS_CtrReg('SS','stick_cmpr' ,'asr',25,RWRW__,64, | |
| 88 | [ | |
| 89 | ('cmpr' , 0,62, RW, 0), | |
| 90 | ('int_dis' ,63,63, RW, 1) | |
| 91 | ]) | |
| 92 | ] | |
| 93 | ||
| 94 | # ToDo For now we add the asr registers here. The full definition appears in | |
| 95 | # N2_State.py ... somehow this code needs to be cleaned up. | |
| 96 | # The only reason they appear here is that the list is used in SS_InstrCrt.py | |
| 97 | # to make our life easier for generating the various rdctr/wrctr instructions. | |
| 98 | ||
| 99 | if setup.product in ['N2']: | |
| 100 | ctr_regs.append(SS_CtrReg('N2','pcr','asr',16,RWRW__,0,[])) | |
| 101 | ctr_regs.append(SS_CtrReg('N2','pic','asr',17,RWRWRW,0,[])) | |
| 102 | ||
| 103 | ctr_table = SS_CtrTable(ctr_regs) |