Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_StateHrf.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: SS_StateHrf.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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# ========== Copyright Header End ============================================

import sys

from SS_State import *
from SS_Setup import *

setup = setups[sys.argv[1]]

ctr_regs = [
  SS_CtrReg('SS','hpstate'   , 'hrf', 0,RW____,16,
  [
    ('tlz'   , 0, 0, RW, 0),
    ('hpriv' , 2, 2, RW, 1),
    ('red'   , 5, 5, RW, 1),
    ('ibe'   ,10,10, RW, 0)
  ])
, SS_CtrReg('SS','htstate'   , 'hrf', 1,RW____,16,
  [
    ('hpstate',0,11, RO, 0),
    (''      , 0, 0, RW, X),
    (''      , 2, 2, RW, X),
    (''      , 5, 5, RW, X),
    (''      ,10,10, RW, X)
  ])
, SS_CtrReg('SS','hintp'     , 'hrf', 3,RW____, 8,
  [
    ('hsp'   , 0, 0, RW, 0)
  ])
, SS_CtrReg('SS','htba'      , 'hrf', 5,RW____,64,
  [
    (''      ,14,63, RW, X)
  ])
, SS_CtrReg('SS','hver'      , 'hrf', 6,RO____,64,
  [
    # HVER is read-only (RO____). This means a wrhrf_hver instruction 
    # is not generated. It is thus safe to make all the fields RW, and 
    # allow for cosim environments to accurately set the HVER to their
    # required value through say valsync (SS_Strand::set_state followme).

    ('maxwin', 0, 4, RW, X),
    ('maxtl' , 8,15, RW, X),
    ('maxgl' ,16,18, RW, X),
    ('mask'  ,24,31, RW, X),
    ('impl'  ,32,47, RW, X),
    ('manuf' ,48,63, RW, X)
  ])
, SS_CtrReg('SS','halt'      , 'hrf',30,RW____,64,
  [
    (''      , 0,63, RO, X)
  ])
, SS_CtrReg('SS','hstick_cmpr','hrf',31,RW____,64,
  [
    ('cmpr'     , 0,62, RW, 0),
    ('int_dis'  ,63,63, RW, 1)
  ])
]

ctr_table = SS_CtrTable(ctr_regs)

if not setup.product in ['N2']:
  ctr_table.reg_at(30).access = OOOOOO  # rd/wr halt is only implemented on product n2