Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_StateSrf.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: SS_StateSrf.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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# ========== Copyright Header End ============================================

from SS_State import *

ctr_regs = [
  SS_CtrReg('SS','strand_id' , 'sim', 0,OOOOOO, 16,
  [
  ])
, SS_CtrReg('SS','max_wp'    , 'sim', 1,OOOOOO, 8,
  [
  ])
, SS_CtrReg('SS','max_tl'    , 'sim', 2,OOOOOO, 8,
  [
  ])
, SS_CtrReg('SS','max_ptl'   , 'sim', 3,OOOOOO, 8,
  [
  ])
, SS_CtrReg('SS','max_gl'    , 'sim', 4,OOOOOO, 8,
  [
  ])
, SS_CtrReg('SS','max_pgl'   , 'sim', 5,OOOOOO, 8,
  [
  ])
, SS_CtrReg('SS','va_bits'   , 'sim', 6,OOOOOO, 8,
  [
    # The size of the virtual (real) address in bits
  ])
, SS_CtrReg('SS','pa_bits'   , 'sim', 7,OOOOOO, 8,
  [
    # The size of the physical address in bits
  ])
, SS_CtrReg('SS','rstv_addr' , 'sim', 8,OOOOOO,64,
  [
    ('',16,63, RW, X)
  ])
, SS_CtrReg('SS','npc'       , 'sim', 9,OOOOOO,64,
  [
    ('', 2,63, RW, X)
  ])
, SS_CtrReg('SS','fsr'       , 'sim',10,OOOOOO,64,
  [
    ('cexc'	, 0, 4,RW,0),
    ('nxc'	, 0, 0,RW,0),
    ('dzc'	, 1, 1,RW,0),
    ('ufc'	, 2, 2,RW,0),
    ('ofc'	, 3, 3,RW,0),
    ('nvc'	, 4, 4,RW,0),

    ('aexc'	, 5, 9,RW,0),
    ('nxa'	, 5, 5,RW,0),
    ('dza'	, 6, 6,RW,0),
    ('ufa'	, 7, 7,RW,0),
    ('ofa'	, 8, 8,RW,0),
    ('nva'	, 9, 9,RW,0),

    ('fcc0'	,10,11,RW,0),
    ('qne'	,13,13,RO,0),
    ('ftt'	,14,16,RW,0),
    ('ver'	,17,19,RO,0),
    ('ns'	,22,22,RW,0),

    ('tem'	,23,27,RW,0),
    ('nxm'	,23,23,RW,0),
    ('dzm'	,24,24,RW,0),
    ('ufm'	,25,25,RW,0),
    ('ofm'	,26,26,RW,0),
    ('nvm'	,27,27,RW,0),

    ('rd'	,30,31,RW,0),
    ('fcc1'	,32,33,RW,0),
    ('fcc2'	,34,35,RW,0),
    ('fcc3'	,36,37,RW,0)
  ])
, SS_CtrReg('SS','sim_state' , 'sim',11,OOOOOO,64,
  [
    # priv = pstate.priv + hpstate.hpriv * 2
    ('priv'        , 0, 1, RW, X),	

    # red = hpstate.red
    ('red'         , 2, 2, RW, X),	

    # mode = priv and red bits together 
    ('mode'        , 0, 2, RO, X),	

    # lsu_ctr.im or inst mmu enabled
    ('inst_mmu'    , 3, 3, RW, X),	

    # lsu_ctr.dm or data mmu enabled
    ('data_mmu'    , 4, 4, RW, X),	

    # fp_disabled = fprs.pef & pstate.fef 
    ('fp_disabled' , 5, 5, RW, X),	

    # ib_enabled = hpstate.ibe if available else the value of
    # ibe_sig below when set by some event
    ('ib_enabled'  , 6, 6, RW, X), 	
    
    # ibe_sig(): signal instr break enable : ibe_sig = sgn->ib_enable;  
    # Used by processors the removed hpstate.ibe
    ('ibe_sig'	   , 7, 7, RW, X),	

    # irq_pending is set when an intrrupt has been found and is signalled
    ('irq_pending' , 8, 8, RW, X), 	

    # running = cmp running status
    ('running'     , 9, 9, RW, X),	

    # cosim = set to 1 when we're in cosim mode
    ('cosim'       ,10,10, RW, X),	

    # XIR at tl == maxtl behaviour was changed late 2005. N2
    # does not go through error state on maxtl.
    ('xir_error_state', 12,12, RW, X),

    # exec_driven is true when tools like xx use Vonk
    ('exec_driven', 13,13, RW, 0),

    # ras_enabled is true when Vonk is doing all sort if RAS checks
    ('ras_enabled' ,14,14, RW, 0),

    # trap_taken is true when some part of execute resulted in a trap
    ('trap_taken'  ,15,15, RW, X),

    # red_tl = tl value when in red state
    ('red_tl'	   ,16,18, RW, X),	

    # use_victim_tlb = set to 1 when victim tlb is turned on
    # should be set only if cosim() is turned on and tlb trap follow-me 
    # is being used
    # Currently, the plan is to use it only in. May be used in other
    # places if needed by RTL-cosim strategy
    ('use_victim_tlb',19,19, RW, X),
    
    # tlb_slamming is set to 1 to enable tlb initialization to run a diag
    ('tlb_slamming',20,20, RW, X),
    	
    # hintp_bit0_clear when set clear hintp.hsp bit on hstick match trap
    ('hintp_hsp_clear',21,21,RW,X)

  ])
, SS_CtrReg('SS','inst_count','sim',12,OOOOOO,64,
  [
    # count number instructions executed on strand
  ])
]