Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / src / SS_Trap.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: SS_Trap.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23#ifndef __SS_Trap_h__
24#define __SS_Trap_h__
25
26#include "SS_Types.h"
27
28class SS_TrapInfo
29{
30 public:
31 uint_t trap_type; // TT value of trap
32 char* name; // Name of the trap
33 uint_t priority; // Priority * 10
34 bool privileged; // True if trap to privileged, false if trap to hyperprivileged
35 bool disrupting; // True if the trap is disrupting, false if precise
36};
37
38
39class SS_Trap
40{
41 public:
42 SS_Trap();
43
44 enum Type
45 {
46 NO_TRAP = 0, // internal value for Vonk
47 RESERVED = 0x000,
48 POWER_ON_RESET = 0x001,
49 WATCHDOG_RESET = 0x002,
50 EXTERNALLY_INITIATED_RESET = 0x003,
51 SOFTWARE_INITIATED_RESET = 0x004,
52 RED_STATE_EXCEPTION = 0x005,
53 STORE_ERROR = 0x007,
54 IAE_PRIVILEGE_VIOLATION = 0x008,
55 INSTRUCTION_ACCESS_MMU_MISS = 0x009,
56 INSTRUCTION_ACCESS_ERROR = 0x00a,
57 IAE_UNAUTH_ACCESS = 0x00b,
58 IAE_NFO_PAGE = 0x00c,
59 INSTRUCTION_ADDRESS_RANGE = 0x00d,
60 INSTRUCTION_REAL_RANGE = 0x00e,
61 ILLEGAL_INSTRUCTION = 0x010,
62 PRIVILEGED_OPCODE = 0x011,
63 UNIMPLEMENTED_LDD = 0x012,
64 UNIMPLEMENTED_STD = 0x013,
65 DAE_INVALID_ASI = 0x014,
66 DAE_PRIVILEGE_VIOLATION = 0x015,
67 DAE_NC_PAGE = 0x016,
68 DAE_NFO_PAGE = 0x017,
69 FP_DISABLED = 0x020,
70 FP_EXCEPTION_IEEE_754 = 0x021,
71 FP_EXCEPTION_OTHER = 0x022,
72 TAG_OVERFLOW = 0x023,
73 CLEAN_WINDOW = 0x024,
74 DIVISION_BY_ZERO = 0x028,
75 INTERNAL_PROCESSOR_ERROR = 0x029,
76 INSTRUCTION_INVALID_TSB_ENTRY = 0x02a,
77 DATA_INVALID_TSB_ENTRY = 0x02b,
78 PERFORMANCE_EVENT = 0x02c,
79 MEM_REAL_RANGE = 0x02d,
80 MEM_ADDRESS_RANGE = 0x02e,
81 DAE_SO_PAGE = 0x030,
82 DATA_ACCESS_MMU_MISS = 0x031,
83 DATA_ACCESS_ERROR = 0x032,
84 DATA_ACCESS_PROTECTION = 0x033,
85 MEM_ADDRESS_NOT_ALIGNED = 0x034,
86 LDDF_MEM_ADDRESS_NOT_ALIGNED = 0x035,
87 STDF_MEM_ADDRESS_NOT_ALIGNED = 0x036,
88 PRIVILEGED_ACTION = 0x037,
89 LDQF_MEM_ADDRESS_NOT_ALIGNED = 0x038,
90 STQF_MEM_ADDRESS_NOT_ALIGNED = 0x039,
91 UNSUPPORTED_PAGE_SIZE = 0x03b,
92 CTRL_WORD_QUEUE_INT = 0x03c,
93 MODULAR_ARITH_INT = 0x03d,
94 INST_REAL_TRANSLATION_MISS = 0x03e,
95 DATA_REAL_TRANSLATION_MISS = 0x03f,
96 SW_RECOVERABLE_ERROR = 0x040,
97 INTERRUPT_LEVEL_1 = 0x041,
98 INTERRUPT_LEVEL_2 = 0x042,
99 INTERRUPT_LEVEL_3 = 0x043,
100 INTERRUPT_LEVEL_4 = 0x044,
101 INTERRUPT_LEVEL_5 = 0x045,
102 INTERRUPT_LEVEL_6 = 0x046,
103 INTERRUPT_LEVEL_7 = 0x047,
104 INTERRUPT_LEVEL_8 = 0x048,
105 INTERRUPT_LEVEL_9 = 0x049,
106 INTERRUPT_LEVEL_10 = 0x04a,
107 INTERRUPT_LEVEL_11 = 0x04b,
108 INTERRUPT_LEVEL_12 = 0x04c,
109 INTERRUPT_LEVEL_13 = 0x04d,
110 INTERRUPT_LEVEL_14 = 0x04e,
111 INTERRUPT_LEVEL_15 = 0x04f,
112 PIC_OVERFLOW = 0x04F,
113 HSTICK_MATCH = 0x05e,
114 TRAP_LEVEL_ZERO = 0x05f,
115 INTERRUPT_VECTOR = 0x060,
116 PA_WATCHPOINT = 0x061,
117 VA_WATCHPOINT = 0x062,
118 HW_CORRECTED_ERROR = 0x063,
119 FAST_INSTRUCTION_ACCESS_MMU_MISS = 0x064,
120 FAST_DATA_ACCESS_MMU_MISS = 0x068,
121 FAST_DATA_ACCESS_PROTECTION = 0x06c,
122 INSTRUCTION_ACCESS_MMU_ERROR = 0x071,
123 DATA_ACCESS_MMU_ERROR = 0x072,
124 CONTROL_TRANSFER_INSTRUCTION = 0x074,
125 INSTRUCTION_VA_WATCHPOINT = 0x075,
126 INSTRUCTION_BREAKPOINT = 0x076,
127 NO_RETIRE = 0x077,
128 SIU_INBOUND_EXCEPTION = 0x078,
129 DATA_ACCESS_SIU_ERROR = 0x079,
130 HYPERPRIV_QUEUE_0 = 0x07a,
131 HYPERPRIV_QUEUE_1 = 0x07b,
132 CPU_MONDO_TRAP = 0x07c,
133 DEV_MONDO_TRAP = 0x07d,
134 RESUMABLE_ERROR = 0x07e,
135 NONRESUMABLE_ERROR = 0x07f,
136 SPILL_N_NORMAL = 0x080,
137 SPILL_N_OTHER = 0x0a0,
138 FILL_N_NORMAL = 0x0c0,
139 FILL_N_OTHER = 0x0e0,
140 TCC_INSTRUCTION = 0x100,
141 TCC_INSTRUCTION_HPRV = 0x180,
142 RESET_GEN_WMR = 0x201,
143 RESET_GEN_DBR = 0x202
144 };
145
146 enum Limit
147 {
148 MAX_TT = 0x203
149 };
150
151 static bool is_fill ( Type tt ) { return ( FILL_N_NORMAL <= tt) && (tt < TCC_INSTRUCTION); }
152 static bool is_spill( Type tt ) { return (SPILL_N_NORMAL <= tt) && (tt < FILL_N_NORMAL ); }
153 static bool is_trap_to_priv( Type tt ) { return SS_Trap::table[tt].privileged; }
154
155 SS_TrapInfo& operator[]( Type tt ) { return table[tt]; }
156
157 static Type fill_normal( uint_t n ) { return Type(uint_t(FILL_N_NORMAL) + n * 4); }
158 static Type fill_other( uint_t n ) { return Type(uint_t(FILL_N_OTHER) + n * 4); }
159 static Type spill_normal( uint_t n ) { return Type(uint_t(SPILL_N_NORMAL) + n * 4); }
160 static Type spill_other( uint_t n ) { return Type(uint_t(SPILL_N_OTHER) + n * 4); }
161
162 static SS_TrapInfo table[MAX_TT];
163};
164
165#endif
166