Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / dummy_mods / rom / rom.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: rom.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
/* rom.cc
 * fake rom device for  T1 in blaze/SAM
 *
 *
 * Copyright (c) 2004 by Sun Microsystems, Inc.
 * All rights reserved.
 *
 */


#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <sys/syscall.h>	// get exec number
#include <sys/types.h>		// uid_t
#include <unistd.h>		// getuid()
#include <inttypes.h>
#include <stdarg.h>

#include <thread.h>

#include "mmi.h"
#include "ui.h"
#include "mem.h"

struct sam_rom_s 
{
  uint64_t startpa;
  uint64_t endpa;
  uint64_t sz;
}; 


extern "C" int	rom_access(uint32_t cpuid, void* obj, uint64_t paddr, mmi_bool_t wr, uint32_t size, uint64_t* buf, uint8_t bytemask);

int	rom_ld_operation (void *cd, uint64_t paddr, uint64_t *buf, int sz, uint32_t cpuid);
int	rom_st_operation (void *cd, uint64_t paddr, uint64_t *buf, int sz, uint32_t cpuid);

extern "C" void rom_create_instance (const char *modname, const char *instance_name);


extern "C" void _init()
{
  if (! mmi_register_instance_creator("rom", rom_create_instance) ) {
    ui->error("Cannot register instance creator for rom\n");
  }
} // _init()



void rom_create_instance (const char *modname, const char *instance_name)
{
  sam_rom_s * rom_obj = new sam_rom_s;

  mmi_instance_t instance = mmi_register_instance(modname, instance_name, (void *) &rom_obj, "rom dummy device");

  rom_obj->startpa = 0x0;
  rom_obj->endpa = 0x0;
  rom_obj->sz = 0;

  // expected syntax: sysconf rom rom1 startpa=<0xblah> endpa=<0xblah>
  int argc = mmi_argc(instance);
  int i;

  for (i=0; i<argc; i++) {
    char * arg = strdup(mmi_argv(instance, i));
    char * marker;
    char * lv = strtok_r(arg, "=", &marker);
    if (strcmp(lv, "startpa") == 0) {
      errno = 0;
      char * rv = strtok_r(NULL, "=", &marker);
      rom_obj->startpa = strtoull(rv, NULL, 0);
      if (errno) {
        perror("rom: error parsing startpa");
        exit(1);
      }
    } else if (strcmp(lv, "endpa") == 0) {
      errno = 0;
      char * rv = strtok_r(NULL, "=", &marker);
      rom_obj->endpa = strtoull(rv, NULL, 0);
      if (errno) {
        perror("rom: error parsing startpa");
        exit(1);
      }
    } else {
      ui->error("%s - unknown parameter of rom device %s\n",lv,instance_name);
      exit(-1);
    }
  }

  rom_obj->sz = rom_obj->endpa - rom_obj->startpa + 1;
  
  if (mmi_map_physio(rom_obj->startpa, rom_obj->sz, (void *) rom_obj, rom_access)) { 
    ui->error("rom: unable to register IO interceptor\n");
    return;
  }
}


int rom_access(uint32_t cpuid, void* obj, uint64_t paddr, mmi_bool_t wr, uint32_t size, uint64_t* buf, uint8_t bytemask)
{
  if (wr) {
    return rom_st_operation(obj, paddr, buf, size, cpuid);
  } else {
    return rom_ld_operation(obj, paddr, buf, size, cpuid);
  }
} // rom_access()

int rom_ld_operation (void *obj, uint64_t paddr, uint64_t *buf, int size, uint32_t cpuid)
{
  
    // redirect load to access sparse mem 
    switch (size) 
    {
         case 1:  *buf = memread8u  (mm1, paddr); break;
         case 2:  *buf = memread16u (mm1, paddr); break; 
         case 4:  *buf = memread32u (mm1, paddr); break; 
         case 8:  *buf = memread64u (mm1, paddr); break; 
         default: 
                  ui->error("rom: ld_operation pa 0x%llx size %d cpu %d, ignored\n", 
                                  paddr, size, cpuid);
                  *buf = 0;                
                  break; 
    }
    
    return 0;
} // int rom_ld_operation (void *cd, uint64_t paddr, uint64_t *buf, int size, uint32_t cpuid)


int rom_st_operation (void *obj, uint64_t paddr, uint64_t *buf, int size, uint32_t cpuid)
{
  
  // redirect store to access sparse mem
  switch (size) 
  {
      case 1:  memwrite8u  (mm1, paddr, *buf); break;
      case 2:  memwrite16u (mm1, paddr, *buf); break; 
      case 4:  memwrite32u (mm1, paddr, *buf); break; 
      case 8:  memwrite64u (mm1, paddr, *buf); break; 
      default: 
               ui->error("rom: st_operation pa 0x%llx size %d cpu %d, ignored\n", 
                                  paddr, size, cpuid);
               break; 
  }
   
  return 0;
} // int rom_st_operation (void *cd, uint64_t paddr, uint64_t *buf, int size, uint32_t cpuid)


/////////////////////////////////////////////////

extern "C" void _fini ()
{
}

/////////////////////////////////////////////////