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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / n2_piu / include / piu.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: piu.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _PIU_H
29#define _PIU_H
30#include "pcie.h"
31
32#pragma ident "@(#)piu.h 1.5 06/06/05 SMI"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#include "defs.h"
39
40
41/*
42 * PCIE CSRs implemented by Niagara 2
43 */
44#define MAX_PCIE_REGX 1706
45#define NUM_PCIE_CSRS 146
46// #define UND_PCIE_CSRS -1
47
48
49enum PCIE_CSR {
50 PIU_Interrupt_Mapping_Registers,
51 PIU_Interrupt_Clear_Registers,
52 PIU_Interrupt_Retry_Timer_Register,
53 PIU_Interrupt_State_Status_Register_1,
54 PIU_Interrupt_State_Status_Register_2,
55 PIU_INTX_Status_Register,
56 PIU_INT_A_Clear_Register,
57 PIU_INT_B_Clear_Register,
58 PIU_INT_C_Clear_Register,
59 PIU_INT_D_Clear_Register,
60 PIU_Event_Queue_Base_Address_Register,
61 PIU_Event_Queue_Control_Set_Register,
62 PIU_Event_Queue_Control_Clear_Register,
63 PIU_Event_Queue_State_Register,
64 PIU_Event_Queue_Tail_Register,
65 PIU_Event_Queue_Head_Register,
66 PIU_MSI_Mapping_Register,
67 PIU_MSI_Clear_Registers,
68 PIU_Interrupt_Mondo_Data_0_Register,
69 PIU_Interrupt_Mondo_Data_1_Register,
70 PIU_ERR_COR_Mapping_Register,
71 PIU_ERR_NONFATAL_Mapping_Register,
72 PIU_ERR_FATAL_Mapping_Register,
73 PIU_PM_PME_Mapping_Register,
74 PIU_PME_To_ACK_Mapping_Register,
75 PIU_IMU_Error_Log_Enable_Register,
76 PIU_IMU_Interrupt_Enable_Register,
77 PIU_IMU_Interrupt_Status_Register,
78 PIU_IMU_Error_Status_Clear_Register,
79 PIU_IMU_Error_Status_Set_Register,
80 PIU_IMU_RDS_Error_Log_Register,
81 PIU_IMU_SCS_Error_Log_Register,
82 PIU_IMU_EQS_Error_Log_Register,
83 PIU_DMC_Core_and_Block_Interrupt_Enable_Register,
84 PIU_DMC_Core_and_Block_Error_Status_Register,
85 PIU_IMU_Performance_Counter_Select_Register,
86 PIU_IMU_Performance_Counter_Zero_Register,
87 PIU_IMU_Performance_Counter_One_Register,
88 PIU_MSI_32_bit_Address_Register,
89 PIU_MSI_64_bit_Address_Register,
90 PIU_Mem_64_PCIE_Offset_Register,
91 PIU_MMU_Control_and_Status_Register,
92 PIU_MMU_TSB_Control_Register,
93 PIU_MMU_TTE_Cache_Invalidate_Register,
94 PIU_MMU_Error_Log_Enable_Register,
95 PIU_MMU_Interrupt_Enable_Register,
96 PIU_MMU_Interrupt_Status_Register,
97 PIU_MMU_Error_Status_Clear_Register,
98 PIU_MMU_Error_Status_Set_Register,
99 PIU_MMU_Translation_Fault_Address_Register,
100 PIU_MMU_Translation_Fault_Status_Register,
101 PIU_MMU_Performance_Counter_Select_Register,
102 PIU_MMU_Performance_Counter_Zero_Register,
103 PIU_MMU_Performance_Counter_One_Register,
104 PIU_MMU_TTE_Cache_Virtual_Tag_Registers,
105 PIU_MMU_TTE_Cache_Physical_Tag_Registers,
106 PIU_MMU_TTE_Cache_Data_Registers,
107 PIU_MMU_DEV2IOTSB_Registers,
108 PIU_MMU_IOTSBDESC_Registers,
109 PIU_ILU_Error_Log_Enable_Register,
110 PIU_ILU_Interrupt_Enable_Register,
111 PIU_ILU_Interrupt_Status_Register,
112 PIU_ILU_Error_Status_Clear_Register,
113 PIU_ILU_Error_Status_Set_Register,
114 PIU_PEU_Core_and_Block_Interrupt_Enable_Register,
115 PIU_PEU_Core_and_Block_Interrupt_Status_Register,
116 PIU_ILU_Diagnostic_Register,
117 PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_A,
118 PIU_DMU_Debug_Select_Register_for_DMU_Debug_Bus_B,
119 PIU_DMU_PCI_Express_Configuration_Register,
120 PIU_Packet_Scoreboard_DMA_Register_Set,
121 PIU_Packet_Scoreboard_PIO_Register_Set,
122 PIU_Transaction_Scoreboard_Register_Set,
123 PIU_Transaction_Scoreboard_Status_Register,
124 PIU_PEU_Control_Register,
125 PIU_PEU_Status_Register,
126 PIU_PEU_PME_Turn_Off_Generate_Register,
127 PIU_PEU_Ingress_Credits_Initial_Register,
128 PIU_PEU_Diagnostic_Register,
129 PIU_PEU_Egress_Credits_Consumed_Register,
130 PIU_PEU_Egress_Credit_Limit_Register,
131 PIU_PEU_Egress_Retry_Buffer_Register,
132 PIU_PEU_Ingress_Credits_Allocated_Register,
133 PIU_PEU_Ingress_Credits_Received_Register,
134 PIU_PEU_Other_Event_Log_Enable_Register,
135 PIU_PEU_Other_Event_Interrupt_Enable_Register,
136 PIU_PEU_Other_Event_Interrupt_Status_Register,
137 PIU_PEU_Other_Event_Status_Clear_Register,
138 PIU_PEU_Other_Event_Status_Set_Register,
139 PIU_PEU_Receive_Other_Event_Header1_Log_Register,
140 PIU_PEU_Receive_Other_Event_Header2_Log_Register,
141 PIU_PEU_Transmit_Other_Event_Header1_Log_Register,
142 PIU_PEU_Transmit_Other_Event_Header2_Log_Register,
143 PIU_PEU_Performance_Counter_Select_Register,
144 PIU_PEU_Performance_Counter_Zero_Register,
145 PIU_PEU_Performance_Counter_One_Register,
146 PIU_PEU_Performance_Counter_Two_Register,
147 PIU_PEU_Debug_Select_A_Register,
148 PIU_PEU_Debug_Select_B_Register,
149 PIU_PEU_Device_Capabilities_Register,
150 PIU_PEU_Device_Control_Register,
151 PIU_PEU_Device_Status_Register,
152 PIU_PEU_Link_Capabilities_Register,
153 PIU_PEU_Link_Control_Register,
154 PIU_PEU_Link_Status_Register,
155 PIU_PEU_Slot_Capabilities_Register,
156 PIU_PEU_Uncorrectable_Error_Log_Enable_Register,
157 PIU_PEU_Uncorrectable_Error_Interrupt_Enable_Register,
158 PIU_PEU_Uncorrectable_Error_Interrupt_Status_Register,
159 PIU_PEU_Uncorrectable_Error_Status_Clear_Register,
160 PIU_PEU_Uncorrectable_Error_Status_Set_Register,
161 PIU_PEU_Receive_Uncorrectable_Error_Header1_Log_Register,
162 PIU_PEU_Receive_Uncorrectable_Error_Header2_Log_Register,
163 PIU_PEU_Transmit_Uncorrectable_Error_Header1_Log_Register,
164 PIU_PEU_Transmit_Uncorrectable_Error_Header2_Log_Register,
165 PIU_PEU_Correctable_Error_Log_Enable_Register,
166 PIU_PEU_Correctable_Error_Interrupt_Enable_Register,
167 PIU_PEU_Correctable_Error_Interrupt_Status_Register,
168 PIU_PEU_Correctable_Error_Status_Clear_Register,
169 PIU_PEU_Correctable_Error_Status_Set_Register,
170 PIU_PEU_CXPL_SERDES_Revision_Register,
171 PIU_PEU_CXPL_AckNak_Latency_Threshold_Register,
172 PIU_PEU_CXPL_AckNak_Latency_Timer_Register,
173 PIU_PEU_CXPL_Replay_Timer_Threshold_Register,
174 PIU_PEU_CXPL_Replay_Timer_Register,
175 PIU_PEU_CXPL_Vendor_DLLP_Message_Register,
176 PIU_PEU_CXPL_LTSSM_Control_Register,
177 PIU_PEU_CXPL_DLL_Control_Register,
178 PIU_PEU_CXPL_MACL_PCS_Control_Register,
179 PIU_PEU_CXPL_MACL_Lane_Skew_Control_Register,
180 PIU_PEU_CXPL_MACL_Symbol_Number_Register,
181 PIU_PEU_CXPL_MACL_Symbol_Timer_Register,
182 PIU_PEU_CXPL_Core_Status_Register,
183 PIU_PEU_CXPL_Event_Error_Log_Enable_Register,
184 PIU_PEU_CXPL_Event_Error_Interrupt_Enable_Register,
185 PIU_PEU_CXPL_Event_Error_Interrupt_Status_Register,
186 PIU_PEU_CXPL_Event_Error_Status_Clear_Register,
187 PIU_PEU_CXPL_Event_Error_Set_Register,
188 PIU_PEU_Link_Bit_Error_Counter_I_Register,
189 PIU_PEU_Link_Bit_Error_Counter_II_Register,
190 PIU_PEU_SERDES_PLL_Control_Register,
191 PIU_PEU_SERDES_Receiver_Lane_Control_Register,
192 PIU_PEU_SERDES_Receiver_Lane_Status_Register,
193 PIU_PEU_SERDES_Transmitter_Control_Register,
194 PIU_PEU_SERDES_Transmitter_Status_Register,
195 PIU_PEU_SERDES_Test_Configuration_Register,
196 UND_PCIE_CSRS
197};
198
199/*
200 * CSR descrptor, used to specify each of the PCIE CSRs implemented
201 * by Niagara 2 PIU
202 */
203struct PCIE_CSR_DESC {
204 int offset;
205 int nwords;
206 int regx;
207 const char *name;
208};
209
210
211typedef enum PCIE_CSR pcie_csr_t;
212typedef struct PCIE_CSR_DESC pcie_csr_desc_t;
213
214
215
216
217typedef struct {
218 uint64_t Interrupt_Mapping_Registers[44];
219 uint64_t Interrupt_Clear_Registers[44];
220 uint64_t Interrupt_Retry_Timer_Register;
221 uint64_t Interrupt_State_Status_Register_1;
222 uint64_t Interrupt_State_Status_Register_2;
223 uint64_t INTX_Status_Register;
224 uint64_t INT_A_Clear_Register;
225 uint64_t INT_B_Clear_Register;
226 uint64_t INT_C_Clear_Register;
227 uint64_t INT_D_Clear_Register;
228 uint64_t Event_Queue_Base_Address_Register;
229 uint64_t Event_Queue_Control_Set_Register[36];
230 uint64_t Event_Queue_Control_Clear_Register[36];
231 uint64_t Event_Queue_State_Register[36];
232 uint64_t Event_Queue_Tail_Register[36];
233 uint64_t Event_Queue_Head_Register[36];
234 uint64_t MSI_Mapping_Register[256];
235 uint64_t MSI_Clear_Registers[256];
236 uint64_t Interrupt_Mondo_Data_0_Register;
237 uint64_t Interrupt_Mondo_Data_1_Register;
238 uint64_t ERR_COR_Mapping_Register;
239 uint64_t ERR_NONFATAL_Mapping_Register;
240 uint64_t ERR_FATAL_Mapping_Register;
241 uint64_t PM_PME_Mapping_Register;
242 uint64_t PME_To_ACK_Mapping_Register;
243 uint64_t IMU_Error_Log_Enable_Register;
244 uint64_t IMU_Interrupt_Enable_Register;
245 uint64_t IMU_Interrupt_Status_Register;
246 uint64_t IMU_Error_Status_Clear_Register;
247 uint64_t IMU_Error_Status_Set_Register;
248 uint64_t IMU_RDS_Error_Log_Register;
249 uint64_t IMU_SCS_Error_Log_Register;
250 uint64_t IMU_EQS_Error_Log_Register;
251 uint64_t DMC_Core_and_Block_Interrupt_Enable_Register;
252 uint64_t DMC_Core_and_Block_Error_Status_Register;
253 uint64_t IMU_Performance_Counter_Select_Register;
254 uint64_t IMU_Performance_Counter_Zero_Register;
255 uint64_t IMU_Performance_Counter_One_Register;
256 uint64_t MSI_32_bit_Address_Register;
257 uint64_t MSI_64_bit_Address_Register;
258 uint64_t Mem_64_PCIE_Offset_Register;
259 uint64_t MMU_Control_and_Status_Register;
260 uint64_t MMU_TSB_Control_Register;
261 uint64_t MMU_TTE_Cache_Invalidate_Register;
262 uint64_t MMU_Error_Log_Enable_Register;
263 uint64_t MMU_Interrupt_Enable_Register;
264 uint64_t MMU_Interrupt_Status_Register;
265 uint64_t MMU_Error_Status_Clear_Register;
266 uint64_t MMU_Error_Status_Set_Register;
267 uint64_t MMU_Translation_Fault_Address_Register;
268 uint64_t MMU_Translation_Fault_Status_Register;
269 uint64_t MMU_Performance_Counter_Select_Register;
270 uint64_t MMU_Performance_Counter_Zero_Register;
271 uint64_t MMU_Performance_Counter_One_Register;
272 uint64_t MMU_TTE_Cache_Virtual_Tag_Registers[64];
273 uint64_t MMU_TTE_Cache_Physical_Tag_Registers[64];
274 uint64_t MMU_TTE_Cache_Data_Registers[512];
275 uint64_t MMU_DEV2IOTSB_Registers[16];
276 uint64_t MMU_IOTSBDESC_Registers[32];
277 uint64_t ILU_Error_Log_Enable_Register;
278 uint64_t ILU_Interrupt_Enable_Register;
279 uint64_t ILU_Interrupt_Status_Register;
280 uint64_t ILU_Error_Status_Clear_Register;
281 uint64_t ILU_Error_Status_Set_Register;
282 uint64_t PEU_Core_and_Block_Interrupt_Enable_Register;
283 uint64_t PEU_Core_and_Block_Interrupt_Status_Register;
284 uint64_t ILU_Diagnostic_Register;
285 uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_A;
286 uint64_t DMU_Debug_Select_Register_for_DMU_Debug_Bus_B;
287 uint64_t DMU_PCI_Express_Configuration_Register;
288 uint64_t Packet_Scoreboard_DMA_Register_Set[32];
289 uint64_t Packet_Scoreboard_PIO_Register_Set[16];
290 uint64_t Transaction_Scoreboard_Register_Set[32];
291 uint64_t Transaction_Scoreboard_Status_Register;
292 uint64_t PEU_Control_Register;
293 uint64_t PEU_Status_Register;
294 uint64_t PEU_PME_Turn_Off_Generate_Register;
295 uint64_t PEU_Ingress_Credits_Initial_Register;
296 uint64_t PEU_Diagnostic_Register;
297 uint64_t PEU_Egress_Credits_Consumed_Register;
298 uint64_t PEU_Egress_Credit_Limit_Register;
299 uint64_t PEU_Egress_Retry_Buffer_Register;
300 uint64_t PEU_Ingress_Credits_Allocated_Register;
301 uint64_t PEU_Ingress_Credits_Received_Register;
302 uint64_t PEU_Other_Event_Log_Enable_Register;
303 uint64_t PEU_Other_Event_Interrupt_Enable_Register;
304 uint64_t PEU_Other_Event_Interrupt_Status_Register;
305 uint64_t PEU_Other_Event_Status_Clear_Register;
306 uint64_t PEU_Other_Event_Status_Set_Register;
307 uint64_t PEU_Receive_Other_Event_Header1_Log_Register;
308 uint64_t PEU_Receive_Other_Event_Header2_Log_Register;
309 uint64_t PEU_Transmit_Other_Event_Header1_Log_Register;
310 uint64_t PEU_Transmit_Other_Event_Header2_Log_Register;
311 uint64_t PEU_Performance_Counter_Select_Register;
312 uint64_t PEU_Performance_Counter_Zero_Register;
313 uint64_t PEU_Performance_Counter_One_Register;
314 uint64_t PEU_Performance_Counter_Two_Register;
315 uint64_t PEU_Debug_Select_A_Register;
316 uint64_t PEU_Debug_Select_B_Register;
317 uint64_t PEU_Device_Capabilities_Register;
318 uint64_t PEU_Device_Control_Register;
319 uint64_t PEU_Device_Status_Register;
320 uint64_t PEU_Link_Capabilities_Register;
321 uint64_t PEU_Link_Control_Register;
322 uint64_t PEU_Link_Status_Register;
323 uint64_t PEU_Slot_Capabilities_Register;
324 uint64_t PEU_Uncorrectable_Error_Log_Enable_Register;
325 uint64_t PEU_Uncorrectable_Error_Interrupt_Enable_Register;
326 uint64_t PEU_Uncorrectable_Error_Interrupt_Status_Register;
327 uint64_t PEU_Uncorrectable_Error_Status_Clear_Register;
328 uint64_t PEU_Uncorrectable_Error_Status_Set_Register;
329 uint64_t PEU_Receive_Uncorrectable_Error_Header1_Log_Register;
330 uint64_t PEU_Receive_Uncorrectable_Error_Header2_Log_Register;
331 uint64_t PEU_Transmit_Uncorrectable_Error_Header1_Log_Register;
332 uint64_t PEU_Transmit_Uncorrectable_Error_Header2_Log_Register;
333 uint64_t PEU_Correctable_Error_Log_Enable_Register;
334 uint64_t PEU_Correctable_Error_Interrupt_Enable_Register;
335 uint64_t PEU_Correctable_Error_Interrupt_Status_Register;
336 uint64_t PEU_Correctable_Error_Status_Clear_Register;
337 uint64_t PEU_Correctable_Error_Status_Set_Register;
338 uint64_t PEU_CXPL_SERDES_Revision_Register;
339 uint64_t PEU_CXPL_AckNak_Latency_Threshold_Register;
340 uint64_t PEU_CXPL_AckNak_Latency_Timer_Register;
341 uint64_t PEU_CXPL_Replay_Timer_Threshold_Register;
342 uint64_t PEU_CXPL_Replay_Timer_Register;
343 uint64_t PEU_CXPL_Vendor_DLLP_Message_Register;
344 uint64_t PEU_CXPL_LTSSM_Control_Register;
345 uint64_t PEU_CXPL_DLL_Control_Register;
346 uint64_t PEU_CXPL_MACL_PCS_Control_Register;
347 uint64_t PEU_CXPL_MACL_Lane_Skew_Control_Register;
348 uint64_t PEU_CXPL_MACL_Symbol_Number_Register;
349 uint64_t PEU_CXPL_MACL_Symbol_Timer_Register;
350 uint64_t PEU_CXPL_Core_Status_Register;
351 uint64_t PEU_CXPL_Event_Error_Log_Enable_Register;
352 uint64_t PEU_CXPL_Event_Error_Interrupt_Enable_Register;
353 uint64_t PEU_CXPL_Event_Error_Interrupt_Status_Register;
354 uint64_t PEU_CXPL_Event_Error_Status_Clear_Register;
355 uint64_t PEU_CXPL_Event_Error_Set_Register;
356 uint64_t PEU_Link_Bit_Error_Counter_I_Register;
357 uint64_t PEU_Link_Bit_Error_Counter_II_Register;
358 uint64_t PEU_SERDES_PLL_Control_Register;
359 uint64_t PEU_SERDES_Receiver_Lane_Control_Register[8];
360 uint64_t PEU_SERDES_Receiver_Lane_Status_Register[8];
361 uint64_t PEU_SERDES_Transmitter_Control_Register[8];
362 uint64_t PEU_SERDES_Transmitter_Status_Register[8];
363 uint64_t PEU_SERDES_Test_Configuration_Register[2];
364} piu_csr_t;
365
366#define WRITE_PIU_CSR(_r, _v, _m) ((_r) = ((_v) & (_m)) | ((_r) & ~(_m)))
367
368/*
369 * Error macro to build lookup table for simulating PIU errors:
370 *
371 * <type, name, error bit, interrupt enable bit>
372 */
373#define PIU_ERR( _name, _i) _name, #_name, ((uint64_t)1<<_i), ((uint64_t)1<<_i)
374
375/*
376 * IMMU error
377 */
378#define IMU_ERROR_MAXNUM 64
379
380typedef enum {
381 RDS,
382 SCS,
383 EQS
384} imu_group_t;
385
386typedef enum imu_error_type {
387 IMU_NONE = -1,
388 MSI_NOT_EN_P = 0,
389 COR_MES_NOT_EN_P = 1,
390 NONFATAL_MES_NOT_EN_P = 2,
391 FATAL_MES_NOT_EN_P = 3,
392 PMPME_MES_NOT_EN_P = 4,
393 PMEACK_MES_NOT_EN_P = 5,
394 MSI_PAR_ERR_P = 6,
395 MSI_MAL_ERR_P = 7,
396 EQ_NOT_EN_P = 8,
397 EQ_OVER_P = 9,
398 MSI_NOT_EN_S = 32,
399 COR_MES_NOT_EN_S = 33,
400 NONFATAL_MES_NOT_EN_S = 34,
401 FATAL_MES_NOT_EN_S = 35,
402 PMPME_MES_NOT_EN_SEQ_OVER_S = 36,
403 PMEACK_MES_NOT_EN_S = 37,
404 MSI_PAR_ERR_S = 38,
405 MSI_MAL_ERR_S = 39,
406 EQ_NOT_EN_S = 40,
407 EQ_OVER_S = 41
408} imu_error_type_t;
409
410typedef struct imu_error_entry {
411 imu_error_type_t error_type;
412 char *error_name;
413 uint64_t error_code;
414 uint64_t intr_enable;
415} imu_error_entry_t;
416
417imu_error_entry_t imu_error_list[IMU_ERROR_MAXNUM];
418
419/*
420 * MMU error
421 */
422#define MMU_ERROR_MAXNUM 64
423
424typedef enum mmu_error_type {
425 MMU_NONE = -1,
426 BYP_ERR_P = 0,
427 BYP_OOR_P = 1,
428 SUN4V_INV_PG_SZ_P = 2,
429 SPARE1_P = 3,
430 TRN_ERR_P = 4,
431 TRN_OOR_P = 5,
432 TTE_INV_P = 6,
433 TTE_PRT_P = 7,
434 TTC_DPE_P = 8,
435 TTC_CAE_P = 9,
436 SPARE2_P = 10,
437 SPARE3_P = 11,
438 TBW_DME_P = 12,
439 TBW_UDE_P = 13,
440 TBW_ERR_P = 14,
441 TBW_DPE_P = 15,
442 IOTSBDESC_INV_P = 16,
443 IOTSBDESC_DPE_P = 17,
444 SUN4V_VA_OOR_P = 18,
445 SUN4V_VA_ADJ_UF_P = 19,
446 SUN4V_KEY_ERR_P = 20,
447 BYP_ERR_S = 32,
448 BYP_OOR_S = 33,
449 SUN4V_INV_PG_SZ_S = 34,
450 SPARE1_S = 35,
451 TRN_ERR_S = 36,
452 TRN_OOR_S = 37,
453 TTE_INV_S = 38,
454 TTE_PRT_S = 39,
455 TTC_DPE_S = 40,
456 TTC_CAE_S = 41,
457 SPARE2_S = 42,
458 SPARE3_S = 43,
459 TBW_DME_S = 44,
460 TBW_UDE_S = 45,
461 TBW_ERR_S = 46,
462 TBW_DPE_S = 47,
463 IOTSBDESC_INV_S = 48,
464 IOTSBDESC_DPE_S = 49,
465 SUN4V_VA_OOR_S = 50,
466 SUN4V_VA_ADJ_UF_S = 51,
467 SUN4V_KEY_ERR_S = 52
468} mmu_error_type_t;
469
470typedef struct mmu_error_entry {
471 mmu_error_type_t error_type;
472 char *error_name;
473 uint64_t error_code;
474 uint64_t intr_enable;
475} mmu_error_entry_t;
476
477mmu_error_entry_t mmu_error_list[MMU_ERROR_MAXNUM];
478
479/*
480 * PCIE interface unit (PIU) for Niagara 2
481 */
482#define MAX_PCIE_INO_NUM 64 /* max interrupt number */
483#define PCIE_IO_ADDR_MASK MASK64(27,0)
484#define PCIE_IOCON_ADDR_MASK MASK64(28,0)
485#define PCIE_MEM64_ADDR_MASK MASK64(35,0)
486
487struct PCIE_MODEL {
488 char *proc_type_namep; /* processor type name */
489 piu_csr_t csrs; /* PCIE CSRs */
490 uint8_t interrupt[MAX_PCIE_INO_NUM];
491 config_dev_t *config_devp; /* back pointer to device tree */
492 config_proc_t *config_procp; /* back pointer to processor */
493 void * sam_piu;
494};
495
496typedef struct PCIE_MODEL pcie_model_t;
497
498/*
499 * Interrupt Mondo INO mapping info
500 */
501typedef enum {
502 INO_INTA = 20,
503 INO_INTB = 21,
504 INO_INTC = 22,
505 INO_INTD = 23,
506 INO_EQLO = 24,
507 INO_EQHI = 59,
508 INO_DMU = 62,
509 INO_PEU = 63
510} irq_ino_t;
511
512/*
513 * Interrupt Mondo State (see N2 PRM section 16.4.3.2 for Interrupt Clear Register)
514 */
515typedef enum {
516 IRQ_IDLE = 0,
517 IRQ_RECEIVED = 1,
518 IRQ_RESERVED = 2, /* not used */
519 IRQ_PENDING = 3
520} irq_state_t;
521
522#define IRQ_STATE_MASK 0x3LL
523
524/*
525 * Event Queue Interrupt State (INO 24 - 59)
526 */
527typedef enum {
528 EQ_IDLE = 1,
529 EQ_ACTIVE = 2,
530 EQ_ERROR = 4
531} eq_state_t;
532
533#define EQ_NUM_ENTRIES 128
534#define EQ_RECORD_SIZE 64
535
536/*
537 * Event Queue Record
538 */
539typedef struct eq_record {
540 /*
541 * bit fields for record[0]
542 */
543 uint32_t reserved :1; /* reserved, bit 63 */
544 uint32_t fmt_type :7; /* bit 62:56 */
545 uint32_t length :10; /* bit 55:46 */
546 uint32_t addr_15_2 :14; /* bit 45:32, copy of msi/msi-x addr[15:2] */
547 uint32_t rid :16; /* bit 31:16, requester Id */
548 uint32_t data0 :16; /* bit 15:0, msi/msi-x data[15,0] */
549 /*
550 * bit fields for record[1]
551 */
552 uint32_t addr_hi :32; /* bit 63:32, copy of msi/msi-x addr[63:32] */
553 uint32_t addr_31_16 :16; /* bit 31:16, copy of msi/msi-x addr[31:16] */
554 uint32_t data1 :16; /* bit 15:0, msi-x data[31:16], not valid for msi */
555 /*
556 * the rest of the records
557 */
558 uint64_t record[6]; /* reserved */
559} eq_record_t;
560
561/*
562 * PCIE TLP Fmt[1:0] and Type[4:0] Field Encodings
563 */
564#define TLP_MRd_FMT_TYPE_IS32 0 /* 32-bit addressed memory read */
565#define TLP_MRd_FMT_TYPE_IS64 (0x1<<5) /* 64-bit addressed memory read */
566#define TLP_MWr_FMT_TYPE_IS32 (0x2<<5) /* 32-bit addressed memory write */
567#define TLP_MWr_FMT_TYPE_IS64 (0x3<<5) /* 64-bit addressed memory write */
568#define TLP_MSI_FMT_TYPE_IS32 ((0x2<<5) | (0x18)) /* 32-bit addressed MSI */
569#define TLP_MSI_FMT_TYPE_IS64 ((0x3<<5) | (0x18)) /* 64-bit addressed MSI */
570
571/*
572 * Macros, functions used for handling PCIE downbound transactions
573 */
574#define PCIE_BUS_NO_MASK MASK64(27,20)
575#define PCIE_DEV_NO_MASK MASK64(19,15)
576#define PCIE_FUN_NO_MASK MASK64(14,12)
577#define PCIE_REG_NO_MASK MASK64(11, 0)
578
579#define PCIE_BUS_NO_SHIFT 20
580#define PCIE_DEV_NO_SHIFT 15
581#define PCIE_FUN_NO_SHIFT 12
582
583
584// piu_region_t piu_decode_region(simcpu_t *sp, pcie_model_t *piup, uint64_t pa, uint64_t *offset);
585piu_region_t piu_decode_region(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
586
587bool piu_decode_cfgio(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
588bool piu_decode_mem32(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
589bool piu_decode_mem64(pcie_model_t *piup, uint64_t pa, uint64_t *offset);
590
591// bool_t piu_csr_access(simcpu_t *sp, pcie_model_t *piup, maccess_t op, uint64_t offset, uint64_t *regp);
592pcieCompleter piu_csr_access(pcie_model_t *piup, maccess_t memop, uint64_t offset, uint64_t *regp);
593
594// bool_t piu_cfg_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
595pcieCompleter piu_cfg_access(pcie_model_t *piup, maccess_t memop, uint64_t ioaddr, uint32_t count, uint64_t *regp,SAM_DeviceId * id);
596
597// bool_t piu_io_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp);
598pcieCompleter piu_io_access(pcie_model_t *piup, maccess_t memop, uint64_t ioaddr, uint32_t count, uint64_t *regp,SAM_DeviceId * id);
599
600//bool_t piu_mem_access(pcie_model_t *piup, maccess_t op, uint64_t ioaddr, uint32_t count, uint64_t *regp,
601pcieCompleter piu_mem_access(pcie_model_t *piup, maccess_t memop, uint64_t paddr, uint32_t count, uint64_t *regp,
602 pcie_space_t space_id, SAM_DeviceId * id);
603
604/*
605 * Macros, functions used for handling PCIE upbound transactions
606 */
607bool piu_dma_access(pcie_model_t *piup, tvaddr_t va, uint8_t *datap, int count, uint16_t req_id,
608 dev_access_t type, dev_mode_t mode,SAM_DeviceId samId);
609bool piu_assert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
610bool piu_deassert_intx(pcie_model_t *piup, uint8_t pin, uint8_t dev_no);
611
612bool piu_iommu(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type, \
613 dev_mode_t mode, tpaddr_t *pa,SAM_DeviceId samId);
614bool piu_iommu_sun4u(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type, \
615 dev_mode_t mode, tpaddr_t *pa,SAM_DeviceId samId);
616bool piu_iommu_sun4v(pcie_model_t *piup, tvaddr_t va, uint16_t req_id, dev_access_t type, \
617 dev_mode_t mode, tpaddr_t *pa,SAM_DeviceId samId);
618bool piu_iommu_va2pa(pcie_model_t *piup,uint64_t tte, int ps, tvaddr_t va, uint16_t req_id, dev_access_t type, \
619 dev_mode_t mode, tpaddr_t *pa);
620
621void piu_set_irq_state(pcie_model_t *piup, uint8_t ino, irq_state_t );
622int piu_get_irq_state(pcie_model_t *piup, uint8_t ino);
623void piu_set_intx_state(pcie_model_t *piup, uint8_t ino, irq_state_t );
624int piu_get_intx_state(pcie_model_t *piup, uint8_t ino);
625void piu_mondo_interrupt(pcie_model_t *piup, uint8_t ino, irq_state_t );
626bool piu_eq_write(pcie_model_t *piup, int eqnum, eq_record_t *record, uint16_t req_id,
627 dev_mode_t mode,SAM_DeviceId samId);
628bool piu_msi_write(pcie_model_t *piup, uint64_t msi_addr, uint8_t *msi_datap, int count,
629 uint16_t req_id, dev_mode_t mode,SAM_DeviceId samId);
630
631pcieCompleter piu_cpu_access(pcie_model_t *piup, tpaddr_t paddr, maccess_t memop, uint64_t *regp,SAM_DeviceId * id);
632
633/*
634 * piu error handling routines
635 */
636void piu_init_error_list();
637void piu_simulate_imu_error(pcie_model_t *piup, uint64_t error);
638void piu_simulate_mmu_error(pcie_model_t *piup, uint64_t error);
639void piu_raise_imu_error(pcie_model_t *piup, uint64_t error_code);
640void piu_raise_mmu_error(pcie_model_t *piup, uint64_t error_code);
641
642/*
643 * internal function prototypes
644 */
645pcie_csr_t piu_offset2reg(uint64_t offset, int *regx);
646
647void piu_init_csr(pcie_model_t *);
648
649
650#ifdef __cplusplus
651}
652#endif
653
654#endif /* _PIU_H */
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